AU1330897A - Electroplated interconnection structures on integrated circuit chips - Google Patents
Electroplated interconnection structures on integrated circuit chipsInfo
- Publication number
- AU1330897A AU1330897A AU13308/97A AU1330897A AU1330897A AU 1330897 A AU1330897 A AU 1330897A AU 13308/97 A AU13308/97 A AU 13308/97A AU 1330897 A AU1330897 A AU 1330897A AU 1330897 A AU1330897 A AU 1330897A
- Authority
- AU
- Australia
- Prior art keywords
- integrated circuit
- circuit chips
- interconnection structures
- electroplated
- electroplated interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US1996/019592 WO1998027585A1 (en) | 1996-12-16 | 1996-12-16 | Electroplated interconnection structures on integrated circuit chips |
Publications (1)
Publication Number | Publication Date |
---|---|
AU1330897A true AU1330897A (en) | 1998-07-15 |
Family
ID=22256261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU13308/97A Abandoned AU1330897A (en) | 1996-12-16 | 1996-12-16 | Electroplated interconnection structures on integrated circuit chips |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0932913A1 (en) |
JP (1) | JP2000510289A (en) |
KR (1) | KR20000057470A (en) |
AU (1) | AU1330897A (en) |
WO (1) | WO1998027585A1 (en) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5989623A (en) * | 1997-08-19 | 1999-11-23 | Applied Materials, Inc. | Dual damascene metallization |
WO1999040615A1 (en) | 1998-02-04 | 1999-08-12 | Semitool, Inc. | Method and apparatus for low-temperature annealing of metallization micro-structures in the production of a microelectronic device |
US6297154B1 (en) | 1998-08-28 | 2001-10-02 | Agere System Guardian Corp. | Process for semiconductor device fabrication having copper interconnects |
JP3631392B2 (en) | 1998-11-02 | 2005-03-23 | 株式会社神戸製鋼所 | Method for forming wiring film |
TW436990B (en) * | 1998-11-24 | 2001-05-28 | Motorola Inc | Process for forming a semiconductor device |
US6184137B1 (en) * | 1998-11-25 | 2001-02-06 | Applied Materials, Inc. | Structure and method for improving low temperature copper reflow in semiconductor features |
US6610190B2 (en) | 2000-11-03 | 2003-08-26 | Nutool, Inc. | Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate |
US7427337B2 (en) | 1998-12-01 | 2008-09-23 | Novellus Systems, Inc. | System for electropolishing and electrochemical mechanical polishing |
US6413388B1 (en) | 2000-02-23 | 2002-07-02 | Nutool Inc. | Pad designs and structures for a versatile materials processing apparatus |
US7204924B2 (en) | 1998-12-01 | 2007-04-17 | Novellus Systems, Inc. | Method and apparatus to deposit layers with uniform properties |
US6497800B1 (en) | 2000-03-17 | 2002-12-24 | Nutool Inc. | Device providing electrical contact to the surface of a semiconductor workpiece during metal plating |
US6544399B1 (en) * | 1999-01-11 | 2003-04-08 | Applied Materials, Inc. | Electrodeposition chemistry for filling apertures with reflective metal |
US6333560B1 (en) * | 1999-01-14 | 2001-12-25 | International Business Machines Corporation | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies |
DE19915146C1 (en) * | 1999-01-21 | 2000-07-06 | Atotech Deutschland Gmbh | Production of highly pure copper wiring trace on semiconductor wafer for integrated circuit by applying metal base coat, plating and structurization uses dimensionally-stable insoluble counter-electrode in electroplating |
US6297155B1 (en) * | 1999-05-03 | 2001-10-02 | Motorola Inc. | Method for forming a copper layer over a semiconductor wafer |
US6423636B1 (en) * | 1999-11-19 | 2002-07-23 | Applied Materials, Inc. | Process sequence for improved seed layer productivity and achieving 3mm edge exclusion for a copper metalization process on semiconductor wafer |
US6612915B1 (en) | 1999-12-27 | 2003-09-02 | Nutool Inc. | Work piece carrier head for plating and polishing |
US6354916B1 (en) | 2000-02-11 | 2002-03-12 | Nu Tool Inc. | Modified plating solution for plating and planarization and process utilizing same |
US7141146B2 (en) | 2000-02-23 | 2006-11-28 | Asm Nutool, Inc. | Means to improve center to edge uniformity of electrochemical mechanical processing of workpiece surface |
US6482307B2 (en) | 2000-05-12 | 2002-11-19 | Nutool, Inc. | Method of and apparatus for making electrical contact to wafer surface for full-face electroplating or electropolishing |
US6852208B2 (en) | 2000-03-17 | 2005-02-08 | Nutool, Inc. | Method and apparatus for full surface electrotreating of a wafer |
AU2001247109A1 (en) | 2000-04-27 | 2001-11-12 | Nutool, Inc. | Conductive structure for use in multi-level metallization and process |
US6695962B2 (en) | 2001-05-01 | 2004-02-24 | Nutool Inc. | Anode designs for planar metal deposits with enhanced electrolyte solution blending and process of supplying electrolyte solution using such designs |
US6478936B1 (en) | 2000-05-11 | 2002-11-12 | Nutool Inc. | Anode assembly for plating and planarizing a conductive layer |
US7195696B2 (en) | 2000-05-11 | 2007-03-27 | Novellus Systems, Inc. | Electrode assembly for electrochemical processing of workpiece |
KR20020029626A (en) * | 2000-10-13 | 2002-04-19 | 마티네즈 길러모 | Electrolyte |
KR100852636B1 (en) | 2000-10-13 | 2008-08-18 | 롬 앤드 하스 일렉트로닉 머트어리얼즈, 엘.엘.씨 | Seed repair and electroplating bath |
US6802946B2 (en) | 2000-12-21 | 2004-10-12 | Nutool Inc. | Apparatus for controlling thickness uniformity of electroplated and electroetched layers |
US6866763B2 (en) | 2001-01-17 | 2005-03-15 | Asm Nutool. Inc. | Method and system monitoring and controlling film thickness profile during plating and electroetching |
US6740221B2 (en) * | 2001-03-15 | 2004-05-25 | Applied Materials Inc. | Method of forming copper interconnects |
US6736954B2 (en) * | 2001-10-02 | 2004-05-18 | Shipley Company, L.L.C. | Plating bath and method for depositing a metal layer on a substrate |
KR100429770B1 (en) * | 2001-11-15 | 2004-05-03 | 한국과학기술연구원 | Copper electroplating solution |
US7316772B2 (en) * | 2002-03-05 | 2008-01-08 | Enthone Inc. | Defect reduction in electrodeposited copper for semiconductor applications |
US8002962B2 (en) | 2002-03-05 | 2011-08-23 | Enthone Inc. | Copper electrodeposition in microelectronics |
US7416975B2 (en) | 2005-09-21 | 2008-08-26 | Novellus Systems, Inc. | Method of forming contact layers on substrates |
US9398700B2 (en) | 2013-06-21 | 2016-07-19 | Invensas Corporation | Method of forming a reliable microelectronic assembly |
CN106521573B (en) * | 2016-11-23 | 2019-10-01 | 苏州昕皓新材料科技有限公司 | Prepare the method and its application with the copper electroplating layer of preferred orientation growth structure |
CN106757191B (en) * | 2016-11-23 | 2019-10-01 | 苏州昕皓新材料科技有限公司 | A kind of copper crystal particle and preparation method thereof with high preferred orientation |
KR102562279B1 (en) | 2018-01-26 | 2023-07-31 | 삼성전자주식회사 | Plating solution and metal composite and method of manufacturing the same |
KR20200109549A (en) | 2019-03-13 | 2020-09-23 | 삼성전자주식회사 | Polishing slurry and method of manufacturing semiconductor device |
US11424133B2 (en) | 2019-07-25 | 2022-08-23 | Samsung Electronics Co., Ltd. | Metal structure and method of manufacturing the same and metal wire and semiconductor device and electronic device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5256274A (en) * | 1990-08-01 | 1993-10-26 | Jaime Poris | Selective metal electrodeposition process |
US5391517A (en) * | 1993-09-13 | 1995-02-21 | Motorola Inc. | Process for forming copper interconnect structure |
-
1996
- 1996-12-16 JP JP10527646A patent/JP2000510289A/en active Pending
- 1996-12-16 EP EP96944775A patent/EP0932913A1/en not_active Withdrawn
- 1996-12-16 WO PCT/US1996/019592 patent/WO1998027585A1/en not_active Application Discontinuation
- 1996-12-16 AU AU13308/97A patent/AU1330897A/en not_active Abandoned
- 1996-12-16 KR KR1019990705116A patent/KR20000057470A/en active Search and Examination
Also Published As
Publication number | Publication date |
---|---|
EP0932913A1 (en) | 1999-08-04 |
JP2000510289A (en) | 2000-08-08 |
KR20000057470A (en) | 2000-09-15 |
WO1998027585A1 (en) | 1998-06-25 |
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