ATE350752T1 - Verfahren und vorrichtung zur vermeidung von speicherzugriffskonflikten - Google Patents
Verfahren und vorrichtung zur vermeidung von speicherzugriffskonfliktenInfo
- Publication number
- ATE350752T1 ATE350752T1 AT02368107T AT02368107T ATE350752T1 AT E350752 T1 ATE350752 T1 AT E350752T1 AT 02368107 T AT02368107 T AT 02368107T AT 02368107 T AT02368107 T AT 02368107T AT E350752 T1 ATE350752 T1 AT E350752T1
- Authority
- AT
- Austria
- Prior art keywords
- read
- access
- asynchronous
- memory access
- access conflicts
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Dram (AREA)
- Storage Device Security (AREA)
- Memory System (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02368107A EP1406265B1 (de) | 2002-10-02 | 2002-10-02 | Verfahren und Vorrichtung zur Vermeidung von Speicherzugriffskonflikten |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE350752T1 true ATE350752T1 (de) | 2007-01-15 |
Family
ID=31985161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT02368107T ATE350752T1 (de) | 2002-10-02 | 2002-10-02 | Verfahren und vorrichtung zur vermeidung von speicherzugriffskonflikten |
Country Status (6)
Country | Link |
---|---|
US (1) | US6915400B2 (de) |
EP (1) | EP1406265B1 (de) |
JP (1) | JP2004171522A (de) |
KR (1) | KR101013425B1 (de) |
AT (1) | ATE350752T1 (de) |
DE (1) | DE60217346T2 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW548923B (en) * | 2001-06-12 | 2003-08-21 | Realtek Semiconductor Corp | Data register in communication system and method thereof |
JP4052192B2 (ja) * | 2003-03-14 | 2008-02-27 | セイコーエプソン株式会社 | 半導体集積回路 |
US7363436B1 (en) * | 2004-02-26 | 2008-04-22 | Integrated Device Technology, Inc. | Collision detection in a multi-port memory system |
US7916574B1 (en) * | 2004-03-05 | 2011-03-29 | Netlist, Inc. | Circuit providing load isolation and memory domain translation for memory module |
JP2006163124A (ja) * | 2004-12-09 | 2006-06-22 | Seiko Epson Corp | 半導体集積回路 |
US7206251B1 (en) * | 2005-03-08 | 2007-04-17 | Altera Corporation | Dual port PLD embedded memory block to support read-before-write in one clock cycle |
KR100725100B1 (ko) * | 2005-12-22 | 2007-06-04 | 삼성전자주식회사 | 포트간 데이터 전송기능을 갖는 멀티패쓰 억세스블 반도체메모리 장치 |
KR100780945B1 (ko) * | 2006-02-15 | 2007-12-03 | 삼성전자주식회사 | 디스플레이 패널 구동 장치 |
US8055865B2 (en) * | 2007-08-06 | 2011-11-08 | International Business Machines Corporation | Managing write requests to data sets in a primary volume subject to being copied to a secondary volume |
US20090063786A1 (en) * | 2007-08-29 | 2009-03-05 | Hakjune Oh | Daisy-chain memory configuration and usage |
KR100897173B1 (ko) | 2007-12-06 | 2009-05-14 | 삼성모바일디스플레이주식회사 | 유기전계발광 표시장치 |
US8995210B1 (en) | 2013-11-26 | 2015-03-31 | International Business Machines Corporation | Write and read collision avoidance in single port memory devices |
US9396116B2 (en) | 2013-11-26 | 2016-07-19 | Globalfoundries Inc. | Write and read collision avoidance in single port memory devices |
US9684622B2 (en) * | 2014-06-09 | 2017-06-20 | Micron Technology, Inc. | Method and apparatus for controlling access to a common bus by multiple components |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5001671A (en) * | 1989-06-27 | 1991-03-19 | Vitelic Corporation | Controller for dual ported memory |
JPH06161870A (ja) * | 1992-11-26 | 1994-06-10 | Nec Corp | デュアルポートram回路 |
US5974482A (en) | 1996-09-20 | 1999-10-26 | Honeywell Inc. | Single port first-in-first-out (FIFO) device having overwrite protection and diagnostic capabilities |
US5761147A (en) | 1997-02-21 | 1998-06-02 | International Business Machines Corporation | Virtual two-port memory structure with fast write-thru operation |
US5781480A (en) * | 1997-07-29 | 1998-07-14 | Motorola, Inc. | Pipelined dual port integrated circuit memory |
US6049487A (en) * | 1998-03-16 | 2000-04-11 | Actel Corporation | Embedded static random access memory for field programmable gate array |
JP3223964B2 (ja) * | 1998-04-03 | 2001-10-29 | 日本電気株式会社 | 半導体記憶装置 |
KR20010028881A (ko) * | 1999-09-27 | 2001-04-06 | 서평원 | 싱글포트램의 프로세서간 공유장치 |
US6144604A (en) * | 1999-11-12 | 2000-11-07 | Haller; Haggai Haim | Simultaneous addressing using single-port RAMs |
US6314047B1 (en) | 1999-12-30 | 2001-11-06 | Texas Instruments Incorporated | Low cost alternative to large dual port RAM |
US6259648B1 (en) * | 2000-03-21 | 2001-07-10 | Systran Corporation | Methods and apparatus for implementing pseudo dual port memory |
US6459650B1 (en) * | 2001-05-15 | 2002-10-01 | Jmos Technology, Inc. | Method and apparatus for asynchronously controlling a DRAM array in a SRAM environment |
-
2002
- 2002-10-02 AT AT02368107T patent/ATE350752T1/de not_active IP Right Cessation
- 2002-10-02 DE DE60217346T patent/DE60217346T2/de not_active Expired - Lifetime
- 2002-10-02 EP EP02368107A patent/EP1406265B1/de not_active Expired - Lifetime
- 2002-10-21 US US10/277,066 patent/US6915400B2/en not_active Expired - Lifetime
-
2003
- 2003-10-02 JP JP2003344204A patent/JP2004171522A/ja active Pending
- 2003-10-02 KR KR1020030068804A patent/KR101013425B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1406265B1 (de) | 2007-01-03 |
KR20040030381A (ko) | 2004-04-09 |
EP1406265A1 (de) | 2004-04-07 |
JP2004171522A (ja) | 2004-06-17 |
US6915400B2 (en) | 2005-07-05 |
KR101013425B1 (ko) | 2011-02-14 |
DE60217346T2 (de) | 2007-10-04 |
US20040068633A1 (en) | 2004-04-08 |
DE60217346D1 (de) | 2007-02-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |