JPS57191748A - Buffer memory controlling system - Google Patents

Buffer memory controlling system

Info

Publication number
JPS57191748A
JPS57191748A JP7496181A JP7496181A JPS57191748A JP S57191748 A JPS57191748 A JP S57191748A JP 7496181 A JP7496181 A JP 7496181A JP 7496181 A JP7496181 A JP 7496181A JP S57191748 A JPS57191748 A JP S57191748A
Authority
JP
Japan
Prior art keywords
buffer memory
data
memory
buffer
data read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7496181A
Other languages
Japanese (ja)
Inventor
Shigemi Nishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7496181A priority Critical patent/JPS57191748A/en
Publication of JPS57191748A publication Critical patent/JPS57191748A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To shorten the time from the start of data write to the end of data read on a buffer memory, by performing the data write processing and the data read processing for the buffer memory in parallel in the memory cycle stage. CONSTITUTION:A buffer memory writing device 1 writes data, which is fetched from a channel (a), in order from the beginning of a buffer memory 3 through a bus (b) by the direct memory access (DMA), and an interrupt signal (c) is generated each time a constant guantity of information is written, and DMA is continued hereafter. A buffer memory reading device 4 reads data of said constant quantity of information in order from beginning of the buffer memory 3 and edits this data and stores it in an output buffer 5 through a bus (f). Thus, the data write to the buffer memory 3 and the data read from the buffer memory 3 are performed in parallel in the memory cycle steal system.
JP7496181A 1981-05-20 1981-05-20 Buffer memory controlling system Pending JPS57191748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7496181A JPS57191748A (en) 1981-05-20 1981-05-20 Buffer memory controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7496181A JPS57191748A (en) 1981-05-20 1981-05-20 Buffer memory controlling system

Publications (1)

Publication Number Publication Date
JPS57191748A true JPS57191748A (en) 1982-11-25

Family

ID=13562411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7496181A Pending JPS57191748A (en) 1981-05-20 1981-05-20 Buffer memory controlling system

Country Status (1)

Country Link
JP (1) JPS57191748A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59218575A (en) * 1983-04-21 1984-12-08 エルシント・リミテツド Buffer memory and use thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50131724A (en) * 1974-04-05 1975-10-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50131724A (en) * 1974-04-05 1975-10-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59218575A (en) * 1983-04-21 1984-12-08 エルシント・リミテツド Buffer memory and use thereof

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