ATE336066T1 - Mram-zelle und speicherarchitektur mit maximalem lesesignal und reduzierter elektromagnetischer interferenz - Google Patents

Mram-zelle und speicherarchitektur mit maximalem lesesignal und reduzierter elektromagnetischer interferenz

Info

Publication number
ATE336066T1
ATE336066T1 AT03727796T AT03727796T ATE336066T1 AT E336066 T1 ATE336066 T1 AT E336066T1 AT 03727796 T AT03727796 T AT 03727796T AT 03727796 T AT03727796 T AT 03727796T AT E336066 T1 ATE336066 T1 AT E336066T1
Authority
AT
Austria
Prior art keywords
maximum read
electromagnetic interference
read signal
mram
memory architecture
Prior art date
Application number
AT03727796T
Other languages
English (en)
Inventor
Anthonie M H Ditewig
Roger Cuppens
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE336066T1 publication Critical patent/ATE336066T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
AT03727796T 2002-05-22 2003-05-19 Mram-zelle und speicherarchitektur mit maximalem lesesignal und reduzierter elektromagnetischer interferenz ATE336066T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02076999 2002-05-22

Publications (1)

Publication Number Publication Date
ATE336066T1 true ATE336066T1 (de) 2006-09-15

Family

ID=29433170

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03727796T ATE336066T1 (de) 2002-05-22 2003-05-19 Mram-zelle und speicherarchitektur mit maximalem lesesignal und reduzierter elektromagnetischer interferenz

Country Status (9)

Country Link
US (1) US7206220B2 (de)
EP (1) EP1509922B1 (de)
JP (1) JP2005526351A (de)
KR (1) KR20050004162A (de)
AT (1) ATE336066T1 (de)
AU (1) AU2003232996A1 (de)
DE (1) DE60307459T2 (de)
TW (1) TW200405338A (de)
WO (1) WO2003098637A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050083986A (ko) 2002-11-28 2005-08-26 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 자기저항 메모리 셀을 갖는 매트릭스와 이를 포함하는비휘발성 메모리 및 자기저항 소자 기록 방법
DE602004004253T2 (de) 2003-03-20 2007-11-15 Koninklijke Philips Electronics N.V. Gleichzeitiges lesen von und schreiben in verschiedene speicherzellen
KR100744125B1 (ko) * 2006-02-04 2007-08-01 삼성전자주식회사 데이터 라인들의 전자파 간섭을 감소시킬 수 있는 메모리시스템
JP2008211058A (ja) * 2007-02-27 2008-09-11 Toshiba Corp 磁気ランダムアクセスメモリ及びその書き込み方法
US8625339B2 (en) * 2011-04-11 2014-01-07 Grandis, Inc. Multi-cell per memory-bit circuit and method
US8315090B2 (en) * 2010-06-07 2012-11-20 Grandis, Inc. Pseudo page mode memory architecture and method
US8331126B2 (en) * 2010-06-28 2012-12-11 Qualcomm Incorporated Non-volatile memory with split write and read bitlines
KR101847890B1 (ko) 2010-10-12 2018-04-12 삼성세미콘덕터, 인코포레이티드 슈도 페이지 모드 메모리 아키텍쳐 및 방법
US8482968B2 (en) * 2010-11-13 2013-07-09 International Business Machines Corporation Non-volatile magnetic tunnel junction transistor
US9548117B2 (en) 2013-12-06 2017-01-17 Empire Technology Development Llc Non-volatile SRAM with multiple storage states
US9349440B1 (en) 2014-12-11 2016-05-24 Empire Technology Development Llc Non-volatile SRAM with multiple storage states
JP6495980B2 (ja) 2017-08-08 2019-04-03 株式会社東芝 磁気メモリ
JP6642773B2 (ja) 2017-09-07 2020-02-12 Tdk株式会社 スピン流磁化反転素子、スピン軌道トルク型磁気抵抗効果素子、及びスピン流磁化反転素子の製造方法
US10971293B2 (en) 2017-12-28 2021-04-06 Tdk Corporation Spin-orbit-torque magnetization rotational element, spin-orbit-torque magnetoresistance effect element, and spin-orbit-torque magnetization rotational element manufacturing method
CN113614920A (zh) 2020-03-05 2021-11-05 Tdk株式会社 磁记录阵列
JP7028372B2 (ja) * 2020-03-05 2022-03-02 Tdk株式会社 磁気記録アレイ及び磁気抵抗効果ユニット
US11164610B1 (en) 2020-06-05 2021-11-02 Qualcomm Incorporated Memory device with built-in flexible double redundancy
US11177010B1 (en) 2020-07-13 2021-11-16 Qualcomm Incorporated Bitcell for data redundancy

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541868A (en) * 1995-02-21 1996-07-30 The United States Of America As Represented By The Secretary Of The Navy Annular GMR-based memory element
US5699293A (en) * 1996-10-09 1997-12-16 Motorola Method of operating a random access memory device having a plurality of pairs of memory cells as the memory device
TW440835B (en) * 1998-09-30 2001-06-16 Siemens Ag Magnetoresistive memory with raised interference security
US6473336B2 (en) * 1999-12-16 2002-10-29 Kabushiki Kaisha Toshiba Magnetic memory device
US6215707B1 (en) * 2000-04-10 2001-04-10 Motorola Inc. Charge conserving write method and system for an MRAM
US6335890B1 (en) * 2000-11-01 2002-01-01 International Business Machines Corporation Segmented write line architecture for writing magnetic random access memories
US6498747B1 (en) * 2002-02-08 2002-12-24 Infineon Technologies Ag Magnetoresistive random access memory (MRAM) cross-point array with reduced parasitic effects

Also Published As

Publication number Publication date
US7206220B2 (en) 2007-04-17
DE60307459D1 (de) 2006-09-21
EP1509922A1 (de) 2005-03-02
AU2003232996A1 (en) 2003-12-02
EP1509922B1 (de) 2006-08-09
WO2003098637A1 (en) 2003-11-27
KR20050004162A (ko) 2005-01-12
DE60307459T2 (de) 2007-04-12
US20060056223A1 (en) 2006-03-16
JP2005526351A (ja) 2005-09-02
TW200405338A (en) 2004-04-01

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