ATE292824T1 - Automatische prüfung von zyklischen betriebsbedingungen für soi schaltungssimulation - Google Patents

Automatische prüfung von zyklischen betriebsbedingungen für soi schaltungssimulation

Info

Publication number
ATE292824T1
ATE292824T1 AT01955380T AT01955380T ATE292824T1 AT E292824 T1 ATE292824 T1 AT E292824T1 AT 01955380 T AT01955380 T AT 01955380T AT 01955380 T AT01955380 T AT 01955380T AT E292824 T1 ATE292824 T1 AT E292824T1
Authority
AT
Austria
Prior art keywords
simulation
circuit simulation
operating conditions
cyclic
automatic check
Prior art date
Application number
AT01955380T
Other languages
English (en)
Inventor
Karl-Eugen Kroell
Juergen Pille
Helmut Schettler
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE292824T1 publication Critical patent/ATE292824T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT01955380T 2000-08-05 2001-07-28 Automatische prüfung von zyklischen betriebsbedingungen für soi schaltungssimulation ATE292824T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00116934 2000-08-05
PCT/EP2001/008780 WO2002013041A2 (en) 2000-08-05 2001-07-28 Automatic check for cyclic operating conditions for soi circuit simulation

Publications (1)

Publication Number Publication Date
ATE292824T1 true ATE292824T1 (de) 2005-04-15

Family

ID=8169458

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01955380T ATE292824T1 (de) 2000-08-05 2001-07-28 Automatische prüfung von zyklischen betriebsbedingungen für soi schaltungssimulation

Country Status (8)

Country Link
US (1) US7194399B2 (de)
EP (1) EP1320813B1 (de)
JP (1) JP3906149B2 (de)
AT (1) ATE292824T1 (de)
AU (1) AU2001277558A1 (de)
DE (1) DE60109944T8 (de)
TW (1) TW548596B (de)
WO (1) WO2002013041A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003222112A1 (en) * 2002-03-28 2003-10-13 Celion Networks, Inc. Apparatus and method for aggregation and transportation for plesiosynchronous framing oriented data formats
WO2004021252A1 (en) * 2002-08-27 2004-03-11 Freescale Semiconductor, Inc. Fast simulation of circuitry having soi transistors
US7656905B2 (en) * 2002-12-24 2010-02-02 Samir Sheth Apparatus and method for aggregation and transportation of gigabit ethernet and other packet based data formats
FR2868181B1 (fr) * 2004-03-29 2006-05-26 Soisic Sa Procede de simulation d'un circuit a l'etat stationnaire
US8856700B1 (en) * 2007-03-17 2014-10-07 Cadence Design Systems, Inc. Methods, systems, and apparatus for reliability synthesis
US8108816B2 (en) * 2009-06-15 2012-01-31 International Business Machines Corporation Device history based delay variation adjustment during static timing analysis
US8141014B2 (en) * 2009-08-10 2012-03-20 International Business Machines Corporation System and method for common history pessimism relief during static timing analysis
JP2011129029A (ja) * 2009-12-21 2011-06-30 Elpida Memory Inc 回路シミュレーション装置および過渡解析方法
TWI587160B (zh) * 2011-04-08 2017-06-11 瑞昱半導體股份有限公司 漏電檢測方法
US20210181250A1 (en) * 2019-12-17 2021-06-17 Bayes Electronics Technology Co., Ltd System and method for identifying design faults or semiconductor modeling errors by analyzing failed transient simulation of an integrated circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4918643A (en) 1988-06-21 1990-04-17 At&T Bell Laboratories Method and apparatus for substantially improving the throughput of circuit simulators
US5555201A (en) * 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
JP2976888B2 (ja) * 1996-06-27 1999-11-10 日本電気株式会社 回路シミュレーション方法
US6442735B1 (en) * 2000-03-15 2002-08-27 International Business Machines Corp. SOI circuit design method

Also Published As

Publication number Publication date
EP1320813B1 (de) 2005-04-06
DE60109944T8 (de) 2006-04-27
DE60109944T2 (de) 2006-02-23
US20020016705A1 (en) 2002-02-07
WO2002013041A2 (en) 2002-02-14
DE60109944D1 (de) 2005-05-12
WO2002013041A3 (en) 2003-02-13
AU2001277558A1 (en) 2002-02-18
JP2004506268A (ja) 2004-02-26
US7194399B2 (en) 2007-03-20
EP1320813A2 (de) 2003-06-25
JP3906149B2 (ja) 2007-04-18
TW548596B (en) 2003-08-21

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