ATE230528T1 - Verfahren und gerät zur taktsteuerung - Google Patents
Verfahren und gerät zur taktsteuerungInfo
- Publication number
- ATE230528T1 ATE230528T1 AT94300709T AT94300709T ATE230528T1 AT E230528 T1 ATE230528 T1 AT E230528T1 AT 94300709 T AT94300709 T AT 94300709T AT 94300709 T AT94300709 T AT 94300709T AT E230528 T1 ATE230528 T1 AT E230528T1
- Authority
- AT
- Austria
- Prior art keywords
- generates
- reference clock
- control signals
- clock signal
- oscillator
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/354—Astable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
- H03K2005/00032—Dc control of switching transistors
- H03K2005/00039—Dc control of switching transistors having four transistors serially
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Selective Calling Equipment (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1412193A | 1993-02-05 | 1993-02-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE230528T1 true ATE230528T1 (de) | 2003-01-15 |
Family
ID=21763652
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT94300709T ATE230528T1 (de) | 1993-02-05 | 1994-01-31 | Verfahren und gerät zur taktsteuerung |
Country Status (3)
Country | Link |
---|---|
EP (3) | EP1120913A1 (de) |
AT (1) | ATE230528T1 (de) |
DE (1) | DE69431936T2 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6115769A (en) * | 1996-06-28 | 2000-09-05 | Lsi Logic Corporation | Method and apparatus for providing precise circuit delays |
US6247138B1 (en) * | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
EP0917292A3 (de) * | 1997-11-13 | 2001-08-16 | Lsi Logic Corporation | Phasenregelschleife mit Doppelkreis |
US6557066B1 (en) | 1999-05-25 | 2003-04-29 | Lsi Logic Corporation | Method and apparatus for data dependent, dual level output driver |
US6294937B1 (en) | 1999-05-25 | 2001-09-25 | Lsi Logic Corporation | Method and apparatus for self correcting parallel I/O circuitry |
KR100738552B1 (ko) | 2006-01-18 | 2007-07-11 | 삼성전자주식회사 | 통신 시스템의 망동기 클럭 검사 방법 및 그 장치 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4352074A (en) * | 1980-02-01 | 1982-09-28 | Westinghouse Electric Corp. | Phase-locked loop filter |
FR2480048A1 (fr) * | 1980-04-04 | 1981-10-09 | Labo Cent Telecommunicat | Boucle analogique a verrouillage en frequence |
AU549343B2 (en) * | 1981-06-08 | 1986-01-23 | British Telecommunications Public Limited Company | Phase locking |
JPS5887902A (ja) * | 1981-11-18 | 1983-05-25 | Mitsubishi Electric Corp | Fm復調器 |
US5086238A (en) * | 1985-07-22 | 1992-02-04 | Hitachi, Ltd. | Semiconductor supply incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
US4791326A (en) * | 1987-01-22 | 1988-12-13 | Intel Corporation | Current controlled solid state switch |
US4813005A (en) * | 1987-06-24 | 1989-03-14 | Hewlett-Packard Company | Device for synchronizing the output pulses of a circuit with an input clock |
DE3806461A1 (de) * | 1988-03-01 | 1989-09-14 | Licentia Gmbh | Split-loop-filter |
US4875108A (en) * | 1988-08-02 | 1989-10-17 | Magnetic Peripherals Inc. | Phase lock loop |
US4928075A (en) * | 1989-06-26 | 1990-05-22 | Digital Equipment Corporation | Multiple bandwidth filter system for phase locked loop |
US5081380A (en) * | 1989-10-16 | 1992-01-14 | Advanced Micro Devices, Inc. | Temperature self-compensated time delay circuits |
JPH0799807B2 (ja) * | 1990-03-09 | 1995-10-25 | 株式会社東芝 | 位相同期回路 |
US5136260A (en) * | 1991-03-08 | 1992-08-04 | Western Digital Corporation | PLL clock synthesizer using current controlled ring oscillator |
US5146121A (en) * | 1991-10-24 | 1992-09-08 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
-
1994
- 1994-01-31 AT AT94300709T patent/ATE230528T1/de not_active IP Right Cessation
- 1994-01-31 EP EP01201022A patent/EP1120913A1/de not_active Withdrawn
- 1994-01-31 DE DE69431936T patent/DE69431936T2/de not_active Expired - Fee Related
- 1994-01-31 EP EP01201021A patent/EP1120912A1/de not_active Withdrawn
- 1994-01-31 EP EP94300709A patent/EP0610052B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69431936D1 (de) | 2003-02-06 |
EP1120912A1 (de) | 2001-08-01 |
EP0610052A3 (de) | 1995-07-19 |
EP0610052B1 (de) | 2003-01-02 |
DE69431936T2 (de) | 2003-08-28 |
EP0610052A2 (de) | 1994-08-10 |
EP1120913A1 (de) | 2001-08-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |