DE69214055D1 - Verfahren und Schaltungsanordnung zur Synchronisierung eines Signals - Google Patents

Verfahren und Schaltungsanordnung zur Synchronisierung eines Signals

Info

Publication number
DE69214055D1
DE69214055D1 DE69214055T DE69214055T DE69214055D1 DE 69214055 D1 DE69214055 D1 DE 69214055D1 DE 69214055 T DE69214055 T DE 69214055T DE 69214055 T DE69214055 T DE 69214055T DE 69214055 D1 DE69214055 D1 DE 69214055D1
Authority
DE
Germany
Prior art keywords
synchronizing
signal
circuit arrangement
arrangement
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69214055T
Other languages
English (en)
Other versions
DE69214055T2 (de
Inventor
Jacques Meyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of DE69214055D1 publication Critical patent/DE69214055D1/de
Application granted granted Critical
Publication of DE69214055T2 publication Critical patent/DE69214055T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
DE69214055T 1991-07-30 1992-07-27 Verfahren und Schaltungsanordnung zur Synchronisierung eines Signals Expired - Fee Related DE69214055T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9109925A FR2680058B1 (fr) 1991-07-30 1991-07-30 Procede et dispositif de synchronisation d'un signal.

Publications (2)

Publication Number Publication Date
DE69214055D1 true DE69214055D1 (de) 1996-10-31
DE69214055T2 DE69214055T2 (de) 1997-04-03

Family

ID=9415924

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69214055T Expired - Fee Related DE69214055T2 (de) 1991-07-30 1992-07-27 Verfahren und Schaltungsanordnung zur Synchronisierung eines Signals

Country Status (5)

Country Link
US (2) US5319681A (de)
EP (1) EP0526359B1 (de)
JP (1) JPH05243982A (de)
DE (1) DE69214055T2 (de)
FR (1) FR2680058B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832048A (en) * 1993-12-30 1998-11-03 International Business Machines Corporation Digital phase-lock loop control system
US5570066A (en) * 1994-08-30 1996-10-29 Motorola, Inc. Method of programming a frequency synthesizer
US6310922B1 (en) * 1995-12-12 2001-10-30 Thomson Consumer Electronics, Inc. Method and apparatus for generating variable rate synchronization signals
US5784332A (en) * 1996-12-12 1998-07-21 Micron Technology Corporation Clock frequency detector for a synchronous memory device
US6172935B1 (en) 1997-04-25 2001-01-09 Micron Technology, Inc. Synchronous dynamic random access memory device
US6628276B1 (en) 2000-03-24 2003-09-30 Stmicroelectronics, Inc. System for high precision signal phase difference measurement
US6826247B1 (en) 2000-03-24 2004-11-30 Stmicroelectronics, Inc. Digital phase lock loop

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3646452A (en) * 1971-02-16 1972-02-29 Ibm Second order digital phaselock loop
DE2413604A1 (de) * 1974-03-21 1975-09-25 Blaupunkt Werke Gmbh Phasenverriegelte regelschleife
US4280099A (en) * 1979-11-09 1981-07-21 Sperry Corporation Digital timing recovery system
US4400817A (en) * 1980-12-30 1983-08-23 Motorola, Inc. Method and means of clock recovery in a received stream of digital data
DE3374829D1 (en) * 1983-09-07 1988-01-14 Ibm Phase-locked clock
US4748644A (en) * 1986-01-29 1988-05-31 Digital Equipment Corporation Method and apparatus for a constant frequency clock source in phase with a variable frequency system clock
JPH0744448B2 (ja) * 1986-03-31 1995-05-15 株式会社東芝 デジタル位相同期ル−プ回路
JPH0770991B2 (ja) * 1986-08-27 1995-07-31 日本電気株式会社 クロツク再生回路
US4820993A (en) * 1987-08-17 1989-04-11 Cyclotomics, Inc. Digital phase lock loop
DE3882489T2 (de) * 1987-11-16 1994-02-17 Sanyo Electric Co PLL-Schaltung zum Generieren eines mit einem Eingangssignal mittels eines geschalteten Teilers synchronisierten Ausgangssignals.
US4890305A (en) * 1988-02-12 1989-12-26 Northern Telecom Limited Dual-tracking phase-locked loop
US5077529A (en) * 1989-07-19 1991-12-31 Level One Communications, Inc. Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter

Also Published As

Publication number Publication date
FR2680058B1 (fr) 1994-01-28
US5319681A (en) 1994-06-07
EP0526359A1 (de) 1993-02-03
JPH05243982A (ja) 1993-09-21
USRE36090E (en) 1999-02-09
FR2680058A1 (fr) 1993-02-05
DE69214055T2 (de) 1997-04-03
EP0526359B1 (de) 1996-09-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee