ATE22632T1 - Verfahren zur herstellung elektrisch leitender bereiche in integrierten monolythischen halbleiteranordnungen sowie danach hergestellte halbleiteranordnung hoher packungsdichte. - Google Patents

Verfahren zur herstellung elektrisch leitender bereiche in integrierten monolythischen halbleiteranordnungen sowie danach hergestellte halbleiteranordnung hoher packungsdichte.

Info

Publication number
ATE22632T1
ATE22632T1 AT83810057T AT83810057T ATE22632T1 AT E22632 T1 ATE22632 T1 AT E22632T1 AT 83810057 T AT83810057 T AT 83810057T AT 83810057 T AT83810057 T AT 83810057T AT E22632 T1 ATE22632 T1 AT E22632T1
Authority
AT
Austria
Prior art keywords
conductive film
semiconductor device
monolythic
integrated
openings
Prior art date
Application number
AT83810057T
Other languages
German (de)
English (en)
Inventor
Richard Percival
Ernst Uhlmann
Original Assignee
Lasarray Holding Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lasarray Holding Ag filed Critical Lasarray Holding Ag
Application granted granted Critical
Publication of ATE22632T1 publication Critical patent/ATE22632T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/046—Electron beam treatment of devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/093—Laser beam treatment in general
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/94—Laser ablative material removal

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT83810057T 1982-02-19 1983-02-09 Verfahren zur herstellung elektrisch leitender bereiche in integrierten monolythischen halbleiteranordnungen sowie danach hergestellte halbleiteranordnung hoher packungsdichte. ATE22632T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH103682 1982-02-19
EP83810057A EP0088045B1 (de) 1982-02-19 1983-02-09 Verfahren zur Herstellung elektrisch leitender Bereiche in integrierten monolythischen Halbleiteranordnungen sowie danach hergestellte Halbleiteranordnung hoher Packungsdichte

Publications (1)

Publication Number Publication Date
ATE22632T1 true ATE22632T1 (de) 1986-10-15

Family

ID=4200953

Family Applications (1)

Application Number Title Priority Date Filing Date
AT83810057T ATE22632T1 (de) 1982-02-19 1983-02-09 Verfahren zur herstellung elektrisch leitender bereiche in integrierten monolythischen halbleiteranordnungen sowie danach hergestellte halbleiteranordnung hoher packungsdichte.

Country Status (5)

Country Link
US (2) US4691434A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0088045B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS58202549A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AT (1) ATE22632T1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3366507D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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US4691434A (en) * 1982-02-19 1987-09-08 Lasarray Holding Ag Method of making electrically conductive regions in monolithic semiconductor devices as applied to a semiconductor device
US4979012A (en) * 1984-10-05 1990-12-18 Honeywell Inc. Semiconductor device with bonding pad contacts
US4924287A (en) * 1985-01-20 1990-05-08 Avner Pdahtzur Personalizable CMOS gate array device and technique
US4778771A (en) * 1985-02-14 1988-10-18 Nec Corporation Process of forming input/output wiring areas for semiconductor integrated circuit
CH670211A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1986-06-25 1989-05-31 Lasarray Holding Ag
JPS63102342A (ja) * 1986-10-20 1988-05-07 Mitsubishi Electric Corp 半導体集積回路装置の配線構造
IL82113A (en) * 1987-04-05 1992-08-18 Zvi Orbach Fabrication of customized integrated circuits
US4872140A (en) * 1987-05-19 1989-10-03 Gazelle Microcircuits, Inc. Laser programmable memory array
JP2690929B2 (ja) * 1988-02-26 1997-12-17 株式会社日立製作所 Ｍｏｓトランジスタ間の配線方法
US5139963A (en) * 1988-07-02 1992-08-18 Hitachi, Ltd. Method and a system for assisting mending of a semiconductor integrated circuit, and a wiring structure and a wiring method suited for mending a semiconductor integrated circuit
US4989063A (en) * 1988-12-09 1991-01-29 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US5008213A (en) * 1988-12-09 1991-04-16 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US4974048A (en) * 1989-03-10 1990-11-27 The Boeing Company Integrated circuit having reroutable conductive paths
US5021856A (en) * 1989-03-15 1991-06-04 Plessey Overseas Limited Universal cell for bipolar NPN and PNP transistors and resistive elements
US5459340A (en) * 1989-10-03 1995-10-17 Trw Inc. Adaptive configurable gate array
US5217916A (en) * 1989-10-03 1993-06-08 Trw Inc. Method of making an adaptive configurable gate array
US5037771A (en) * 1989-11-28 1991-08-06 Cross-Check Technology, Inc. Method for implementing grid-based crosscheck test structures and the structures resulting therefrom
EP0433720A3 (en) * 1989-12-22 1992-08-26 Siemens Aktiengesellschaft Method of applying a solder stop coating on printed circuit boards
JPH06314692A (ja) * 1993-04-27 1994-11-08 Intel Corp 集積回路におけるビア／接点被覆範囲を改善する方法
US5874754A (en) * 1993-07-01 1999-02-23 Lsi Logic Corporation Microelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gates
US5440154A (en) * 1993-07-01 1995-08-08 Lsi Logic Corporation Non-rectangular MOS device configurations for gate array type integrated circuits
US5585016A (en) * 1993-07-20 1996-12-17 Integrated Device Technology, Inc. Laser patterned C-V dot
US5557534A (en) * 1995-01-03 1996-09-17 Xerox Corporation Forming array with metal scan lines to control semiconductor gate lines
US5985518A (en) * 1997-03-24 1999-11-16 Clear Logic, Inc. Method of customizing integrated circuits using standard masks and targeting energy beams
US6060330A (en) * 1997-03-24 2000-05-09 Clear Logic, Inc. Method of customizing integrated circuits by selective secondary deposition of interconnect material
US5911850A (en) * 1997-06-20 1999-06-15 International Business Machines Corporation Separation of diced wafers
US5840627A (en) * 1997-03-24 1998-11-24 Clear Logic, Inc. Method of customizing integrated circuits using standard masks and targeting energy beams for single resist development
US5885749A (en) * 1997-06-20 1999-03-23 Clear Logic, Inc. Method of customizing integrated circuits by selective secondary deposition of layer interconnect material
US5953577A (en) * 1998-09-29 1999-09-14 Clear Logic, Inc. Customization of integrated circuits
US7708993B2 (en) 1999-02-03 2010-05-04 Amgen Inc. Polypeptides involved in immune response
WO2005099331A1 (ja) * 2004-03-30 2005-10-20 Matsushita Electric Industrial Co., Ltd. モジュール部品およびその製造方法

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US4231149A (en) * 1978-10-10 1980-11-04 Texas Instruments Incorporated Narrow band-gap semiconductor CCD imaging device and method of fabrication
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US4691434A (en) * 1982-02-19 1987-09-08 Lasarray Holding Ag Method of making electrically conductive regions in monolithic semiconductor devices as applied to a semiconductor device
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Also Published As

Publication number Publication date
DE3366507D1 (en) 1986-11-06
EP0088045B1 (de) 1986-10-01
EP0088045A1 (de) 1983-09-07
JPS58202549A (ja) 1983-11-25
US4691434A (en) 1987-09-08
US4689657A (en) 1987-08-25
JPH0572745B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-10-12

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Legal Events

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REN Ceased due to non-payment of the annual fee