ATE211854T1 - Polyzid-ätzverfahren für submikron-gate-stapel - Google Patents
Polyzid-ätzverfahren für submikron-gate-stapelInfo
- Publication number
- ATE211854T1 ATE211854T1 AT95116065T AT95116065T ATE211854T1 AT E211854 T1 ATE211854 T1 AT E211854T1 AT 95116065 T AT95116065 T AT 95116065T AT 95116065 T AT95116065 T AT 95116065T AT E211854 T1 ATE211854 T1 AT E211854T1
- Authority
- AT
- Austria
- Prior art keywords
- etching process
- gate stacks
- submicron gate
- reaction chamber
- gate array
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- 238000005530 etching Methods 0.000 title 1
- 230000001939 inductive effect Effects 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3343—Problems associated with etching
- H01J2237/3348—Problems associated with etching control of ion bombardment energy
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/359,789 US5529197A (en) | 1994-12-20 | 1994-12-20 | Polysilicon/polycide etch process for sub-micron gate stacks |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE211854T1 true ATE211854T1 (de) | 2002-01-15 |
Family
ID=23415277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT95116065T ATE211854T1 (de) | 1994-12-20 | 1995-10-11 | Polyzid-ätzverfahren für submikron-gate-stapel |
Country Status (7)
Country | Link |
---|---|
US (1) | US5529197A (de) |
EP (1) | EP0718868B1 (de) |
JP (1) | JPH08236512A (de) |
KR (1) | KR100376001B1 (de) |
AT (1) | ATE211854T1 (de) |
DE (1) | DE69524934T2 (de) |
TW (1) | TW345702B (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0166205B1 (ko) * | 1995-10-11 | 1999-02-01 | 김광호 | 반도체장치의 폴리사이드 게이트 형성방법 |
US5880033A (en) * | 1996-06-17 | 1999-03-09 | Applied Materials, Inc. | Method for etching metal silicide with high selectivity to polysilicon |
KR100230430B1 (ko) * | 1997-07-16 | 1999-11-15 | 윤종용 | 가스 혼합물 및 이를 이용한 전극층 식각 방법 |
US6797188B1 (en) | 1997-11-12 | 2004-09-28 | Meihua Shen | Self-cleaning process for etching silicon-containing material |
US6322714B1 (en) | 1997-11-12 | 2001-11-27 | Applied Materials Inc. | Process for etching silicon-containing material on substrates |
US6136211A (en) | 1997-11-12 | 2000-10-24 | Applied Materials, Inc. | Self-cleaning etch process |
US6872322B1 (en) | 1997-11-12 | 2005-03-29 | Applied Materials, Inc. | Multiple stage process for cleaning process chambers |
US6261934B1 (en) | 1998-03-31 | 2001-07-17 | Texas Instruments Incorporated | Dry etch process for small-geometry metal gates over thin gate dielectric |
US6399432B1 (en) | 1998-11-24 | 2002-06-04 | Philips Semiconductors Inc. | Process to control poly silicon profiles in a dual doped poly silicon process |
US6399515B1 (en) | 1999-06-21 | 2002-06-04 | Taiwan Semiconductor Manufacturing Company | Plasma etch method for forming patterned chlorine containing plasma etchable silicon containing layer with enhanced sidewall profile uniformity |
US6527968B1 (en) * | 2000-03-27 | 2003-03-04 | Applied Materials Inc. | Two-stage self-cleaning silicon etch process |
EP1156519A1 (de) * | 2000-05-16 | 2001-11-21 | Semiconductor 300 GmbH & Co. KG | Gateätzverfahren für 12 Zoll-Wafern |
US6809769B1 (en) | 2000-06-22 | 2004-10-26 | Pixim, Inc. | Designs of digital pixel sensors |
US6905800B1 (en) | 2000-11-21 | 2005-06-14 | Stephen Yuen | Etching a substrate in a process zone |
US20090104776A1 (en) * | 2007-10-18 | 2009-04-23 | International Business Machines Corporation | Methods for forming nested and isolated lines in semiconductor devices |
US8118946B2 (en) * | 2007-11-30 | 2012-02-21 | Wesley George Lau | Cleaning process residues from substrate processing chamber components |
US7909389B2 (en) | 2008-01-31 | 2011-03-22 | Cnh America Llc | Protection device for a pivotable cab structure |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4358340A (en) * | 1980-07-14 | 1982-11-09 | Texas Instruments Incorporated | Submicron patterning without using submicron lithographic technique |
US4561907A (en) * | 1984-07-12 | 1985-12-31 | Bruha Raicu | Process for forming low sheet resistance polysilicon having anisotropic etch characteristics |
US4659426A (en) * | 1985-05-03 | 1987-04-21 | Texas Instruments Incorporated | Plasma etching of refractory metals and their silicides |
JPS62162362A (ja) * | 1986-01-10 | 1987-07-18 | Mitsubishi Electric Corp | Mos型集積回路及びその製造方法 |
US4785337A (en) * | 1986-10-17 | 1988-11-15 | International Business Machines Corporation | Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes |
US4778563A (en) * | 1987-03-26 | 1988-10-18 | Applied Materials, Inc. | Materials and methods for etching tungsten polycides using silicide as a mask |
JPS6482533A (en) * | 1987-09-25 | 1989-03-28 | Toshiba Corp | Dry etching |
US5106776A (en) * | 1988-06-01 | 1992-04-21 | Texas Instruments Incorporated | Method of making high performance composed pillar dRAM cell |
JP2859288B2 (ja) * | 1989-03-20 | 1999-02-17 | 株式会社日立製作所 | 半導体集積回路装置及びその製造方法 |
US5275972A (en) * | 1990-02-19 | 1994-01-04 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window |
JPH03257182A (ja) * | 1990-03-07 | 1991-11-15 | Hitachi Ltd | 表面加工装置 |
JPH047822A (ja) * | 1990-04-25 | 1992-01-13 | Fuji Xerox Co Ltd | 半導体装置の製造方法 |
US5212116A (en) * | 1990-06-18 | 1993-05-18 | At&T Bell Laboratories | Method for forming planarized films by preferential etching of the center of a wafer |
US5022958A (en) * | 1990-06-27 | 1991-06-11 | At&T Bell Laboratories | Method of etching for integrated circuits with planarized dielectric |
US5304279A (en) * | 1990-08-10 | 1994-04-19 | International Business Machines Corporation | Radio frequency induction/multipole plasma processing tool |
JP2519364B2 (ja) * | 1990-12-03 | 1996-07-31 | アプライド マテリアルズ インコーポレイテッド | Uhf/vhf共振アンテナ供給源を用いたプラズマリアクタ |
JPH0582481A (ja) * | 1991-09-18 | 1993-04-02 | Nippon Telegr & Teleph Corp <Ntt> | ガーネツト膜加工方法 |
US5126916A (en) * | 1991-12-20 | 1992-06-30 | Industrial Technology Research Institute | Stacked capacitor dram cell and method of fabricating |
JP3181406B2 (ja) * | 1992-02-18 | 2001-07-03 | 松下電器産業株式会社 | 半導体記憶装置 |
EP0562207B1 (de) * | 1992-03-27 | 1996-06-05 | International Business Machines Corporation | Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur |
US5227325A (en) * | 1992-04-02 | 1993-07-13 | Micron Technology, Incl | Method of forming a capacitor |
US5286344A (en) * | 1992-06-15 | 1994-02-15 | Micron Technology, Inc. | Process for selectively etching a layer of silicon dioxide on an underlying stop layer of silicon nitride |
US5346578A (en) * | 1992-11-04 | 1994-09-13 | Novellus Systems, Inc. | Induction plasma source |
US5346586A (en) * | 1992-12-23 | 1994-09-13 | Micron Semiconductor, Inc. | Method for selectively etching polysilicon to gate oxide using an insitu ozone photoresist strip |
JP2842125B2 (ja) * | 1993-02-04 | 1998-12-24 | 日本電気株式会社 | 電界効果型トランジスタの製造方法 |
US5667631A (en) * | 1996-06-28 | 1997-09-16 | Lam Research Corporation | Dry etching of transparent electrodes in a low pressure plasma reactor |
-
1994
- 1994-12-20 US US08/359,789 patent/US5529197A/en not_active Expired - Lifetime
-
1995
- 1995-10-11 TW TW084110648A patent/TW345702B/zh not_active IP Right Cessation
- 1995-10-11 AT AT95116065T patent/ATE211854T1/de not_active IP Right Cessation
- 1995-10-11 EP EP95116065A patent/EP0718868B1/de not_active Expired - Lifetime
- 1995-10-11 DE DE69524934T patent/DE69524934T2/de not_active Expired - Lifetime
- 1995-12-15 JP JP7347119A patent/JPH08236512A/ja active Pending
- 1995-12-20 KR KR1019950052441A patent/KR100376001B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0718868B1 (de) | 2002-01-09 |
US5529197A (en) | 1996-06-25 |
KR960026305A (ko) | 1996-07-22 |
TW345702B (en) | 1998-11-21 |
DE69524934T2 (de) | 2002-06-06 |
JPH08236512A (ja) | 1996-09-13 |
DE69524934D1 (de) | 2002-02-14 |
EP0718868A2 (de) | 1996-06-26 |
EP0718868A3 (de) | 1998-05-06 |
KR100376001B1 (ko) | 2003-06-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |