ATE209794T1 - Absendung von befehlen an mehrere verarbeitungseinheiten - Google Patents
Absendung von befehlen an mehrere verarbeitungseinheitenInfo
- Publication number
- ATE209794T1 ATE209794T1 AT94306765T AT94306765T ATE209794T1 AT E209794 T1 ATE209794 T1 AT E209794T1 AT 94306765 T AT94306765 T AT 94306765T AT 94306765 T AT94306765 T AT 94306765T AT E209794 T1 ATE209794 T1 AT E209794T1
- Authority
- AT
- Austria
- Prior art keywords
- instruction
- instructions
- buffer
- unit
- dependent
- Prior art date
Links
- 239000000872 buffer Substances 0.000 abstract 6
- 230000001419 dependent effect Effects 0.000 abstract 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
- Selective Calling Equipment (AREA)
- Supplying Of Containers To The Packaging Station (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12382893A | 1993-09-20 | 1993-09-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE209794T1 true ATE209794T1 (de) | 2001-12-15 |
Family
ID=22411140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT94306765T ATE209794T1 (de) | 1993-09-20 | 1994-09-15 | Absendung von befehlen an mehrere verarbeitungseinheiten |
Country Status (11)
Country | Link |
---|---|
US (1) | US5613080A (de) |
EP (1) | EP0644482B1 (de) |
JP (1) | JP2788605B2 (de) |
KR (1) | KR0133238B1 (de) |
CN (1) | CN1047677C (de) |
AT (1) | ATE209794T1 (de) |
BR (1) | BR9403516A (de) |
CA (1) | CA2123442A1 (de) |
DE (1) | DE69429226T2 (de) |
ES (1) | ES2165375T3 (de) |
TW (1) | TW393622B (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5684971A (en) * | 1993-12-27 | 1997-11-04 | Intel Corporation | Reservation station with a pseudo-FIFO circuit for scheduling dispatch of instructions |
US5717882A (en) * | 1994-01-04 | 1998-02-10 | Intel Corporation | Method and apparatus for dispatching and executing a load operation to memory |
TW353732B (en) * | 1994-03-31 | 1999-03-01 | Ibm | Processing system and method of operation |
JP3180175B2 (ja) * | 1995-02-13 | 2001-06-25 | 株式会社日立製作所 | 命令レベルの並列処理制御方法およびプロセッサ |
TW448403B (en) * | 1995-03-03 | 2001-08-01 | Matsushita Electric Ind Co Ltd | Pipeline data processing device and method for executing multiple data processing data dependent relationship |
US5802346A (en) * | 1995-06-02 | 1998-09-01 | International Business Machines Corporation | Method and system for minimizing the delay in executing branch-on-register instructions |
GB9514433D0 (en) * | 1995-07-14 | 1995-09-13 | Sgs Thomson Microelectronics | Computer instruction execution |
US5930490A (en) * | 1996-01-02 | 1999-07-27 | Advanced Micro Devices, Inc. | Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions |
US5799167A (en) * | 1996-05-15 | 1998-08-25 | Hewlett-Packard Company | Instruction nullification system and method for a processor that executes instructions out of order |
US5796975A (en) * | 1996-05-24 | 1998-08-18 | Hewlett-Packard Company | Operand dependency tracking system and method for a processor that executes instructions out of order |
US6049864A (en) * | 1996-08-20 | 2000-04-11 | Intel Corporation | Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor |
KR100222039B1 (ko) * | 1996-12-20 | 1999-10-01 | 윤종용 | 수퍼 스칼라 프로세서의 명령 종속성 검증 장치 및 방법 |
US5963723A (en) * | 1997-03-26 | 1999-10-05 | International Business Machines Corporation | System for pairing dependent instructions having non-contiguous addresses during dispatch |
US5928355A (en) * | 1997-06-27 | 1999-07-27 | Sun Microsystems Incorporated | Apparatus for reducing instruction issue stage stalls through use of a staging register |
US6035388A (en) | 1997-06-27 | 2000-03-07 | Sandcraft, Inc. | Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units |
US5918034A (en) * | 1997-06-27 | 1999-06-29 | Sun Microsystems, Inc. | Method for decoupling pipeline stages |
US5870578A (en) * | 1997-12-09 | 1999-02-09 | Advanced Micro Devices, Inc. | Workload balancing in a microprocessor for reduced instruction dispatch stalling |
US6393551B1 (en) | 1999-05-26 | 2002-05-21 | Infineon Technologies North America Corp. | Reducing instruction transactions in a microprocessor |
US6490653B1 (en) * | 1999-06-03 | 2002-12-03 | International Business Machines Corporation | Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system |
JP3878508B2 (ja) * | 2001-11-08 | 2007-02-07 | 松下電器産業株式会社 | 回路群制御システム |
US6895497B2 (en) | 2002-03-06 | 2005-05-17 | Hewlett-Packard Development Company, L.P. | Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority |
KR100473390B1 (ko) * | 2002-05-24 | 2005-03-08 | 창 원 석 | 케이블티브이용 채널분배기 |
US20040128476A1 (en) * | 2002-12-26 | 2004-07-01 | Robert Nuckolls | Scheme to simplify instruction buffer logic supporting multiple strands |
US20080168260A1 (en) * | 2007-01-08 | 2008-07-10 | Victor Zyuban | Symbolic Execution of Instructions on In-Order Processors |
JP5491071B2 (ja) | 2009-05-20 | 2014-05-14 | エヌイーシーコンピュータテクノ株式会社 | 命令融合演算装置および命令融合演算方法 |
US9122487B2 (en) * | 2009-06-23 | 2015-09-01 | Oracle America, Inc. | System and method for balancing instruction loads between multiple execution units using assignment history |
US9733941B2 (en) * | 2012-10-09 | 2017-08-15 | Advanced Micro Devices, Inc. | Technique for translating dependent instructions |
US9372695B2 (en) | 2013-06-28 | 2016-06-21 | Globalfoundries Inc. | Optimization of instruction groups across group boundaries |
US9348596B2 (en) | 2013-06-28 | 2016-05-24 | International Business Machines Corporation | Forming instruction groups based on decode time instruction optimization |
US10417152B2 (en) * | 2016-06-03 | 2019-09-17 | International Business Machines Corporation | Operation of a multi-slice processor implementing datapath steering |
JP7032647B2 (ja) * | 2018-04-17 | 2022-03-09 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
CN112559054B (zh) * | 2020-12-22 | 2022-02-01 | 上海壁仞智能科技有限公司 | 用于同步指令的方法和计算系统 |
Family Cites Families (40)
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US3771141A (en) * | 1971-11-08 | 1973-11-06 | Culler Harrison Inc | Data processor with parallel operations per instruction |
JPS5140043A (ja) * | 1974-10-01 | 1976-04-03 | Nippon Telegraph & Telephone | Hanyonyushutsuryokuseigyosochi |
JPS5263038A (en) * | 1975-10-01 | 1977-05-25 | Hitachi Ltd | Data processing device |
US4130885A (en) * | 1976-08-19 | 1978-12-19 | Massachusetts Institute Of Technology | Packet memory system for processing many independent memory transactions concurrently |
US4232366A (en) * | 1978-10-25 | 1980-11-04 | Digital Equipment Corporation | Bus for a data processing system with overlapped sequences |
US4376976A (en) * | 1980-07-31 | 1983-03-15 | Sperry Corporation | Overlapped macro instruction control system |
JPS58151655A (ja) * | 1982-03-03 | 1983-09-08 | Fujitsu Ltd | 情報処理装置 |
JPS5932045A (ja) * | 1982-08-16 | 1984-02-21 | Hitachi Ltd | 情報処理装置 |
US4594655A (en) * | 1983-03-14 | 1986-06-10 | International Business Machines Corporation | (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions |
US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
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US5051940A (en) * | 1990-04-04 | 1991-09-24 | International Business Machines Corporation | Data dependency collapsing hardware apparatus |
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US4766566A (en) * | 1986-08-18 | 1988-08-23 | International Business Machines Corp. | Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing |
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EP0312764A3 (de) * | 1987-10-19 | 1991-04-10 | International Business Machines Corporation | Datenprozessor mit mehrfachen Ausführungseinheiten zur parallelen Ausführung von mehreren Befehlsklassen |
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US4974155A (en) * | 1988-08-15 | 1990-11-27 | Evans & Sutherland Computer Corp. | Variable delay branch system |
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US5093908A (en) * | 1989-04-17 | 1992-03-03 | International Business Machines Corporation | Method and apparatus for executing instructions in a single sequential instruction stream in a main processor and a coprocessor |
US5197137A (en) * | 1989-07-28 | 1993-03-23 | International Business Machines Corporation | Computer architecture for the concurrent execution of sequential programs |
JP2816248B2 (ja) * | 1989-11-08 | 1998-10-27 | 株式会社日立製作所 | データプロセッサ |
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JP2866421B2 (ja) * | 1990-01-19 | 1999-03-08 | 株式会社日立製作所 | 複数パス並列処理方法 |
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US5283874A (en) * | 1991-10-21 | 1994-02-01 | Intel Corporation | Cross coupling mechanisms for simultaneously completing consecutive pipeline instructions even if they begin to process at the same microprocessor of the issue fee |
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GB2263565B (en) * | 1992-01-23 | 1995-08-30 | Intel Corp | Microprocessor with apparatus for parallel execution of instructions |
-
1994
- 1994-05-12 CA CA002123442A patent/CA2123442A1/en not_active Abandoned
- 1994-07-15 JP JP6163633A patent/JP2788605B2/ja not_active Expired - Fee Related
- 1994-09-12 BR BR9403516A patent/BR9403516A/pt not_active Application Discontinuation
- 1994-09-14 CN CN94115166A patent/CN1047677C/zh not_active Expired - Fee Related
- 1994-09-14 KR KR1019940023113A patent/KR0133238B1/ko not_active IP Right Cessation
- 1994-09-15 ES ES94306765T patent/ES2165375T3/es not_active Expired - Lifetime
- 1994-09-15 EP EP94306765A patent/EP0644482B1/de not_active Expired - Lifetime
- 1994-09-15 DE DE69429226T patent/DE69429226T2/de not_active Expired - Fee Related
- 1994-09-15 AT AT94306765T patent/ATE209794T1/de not_active IP Right Cessation
- 1994-09-23 TW TW083108818A patent/TW393622B/zh not_active IP Right Cessation
-
1996
- 1996-08-08 US US08/695,750 patent/US5613080A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1047677C (zh) | 1999-12-22 |
CA2123442A1 (en) | 1995-03-21 |
KR0133238B1 (ko) | 1998-04-24 |
DE69429226D1 (de) | 2002-01-10 |
CN1120195A (zh) | 1996-04-10 |
EP0644482A1 (de) | 1995-03-22 |
KR950009453A (ko) | 1995-04-24 |
DE69429226T2 (de) | 2002-08-08 |
US5613080A (en) | 1997-03-18 |
EP0644482B1 (de) | 2001-11-28 |
BR9403516A (pt) | 1995-06-20 |
JPH07105002A (ja) | 1995-04-21 |
ES2165375T3 (es) | 2002-03-16 |
JP2788605B2 (ja) | 1998-08-20 |
TW393622B (en) | 2000-06-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |