ATE202644T1 - Vorrichtung und verfahren zur abtastung einer befehlswarteschlange - Google Patents

Vorrichtung und verfahren zur abtastung einer befehlswarteschlange

Info

Publication number
ATE202644T1
ATE202644T1 AT95304957T AT95304957T ATE202644T1 AT E202644 T1 ATE202644 T1 AT E202644T1 AT 95304957 T AT95304957 T AT 95304957T AT 95304957 T AT95304957 T AT 95304957T AT E202644 T1 ATE202644 T1 AT E202644T1
Authority
AT
Austria
Prior art keywords
instruction
queue
instructions
logic
byte queue
Prior art date
Application number
AT95304957T
Other languages
English (en)
Inventor
Nathan L Yao
Michael D Goddard
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE202644T1 publication Critical patent/ATE202644T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Vehicle Body Suspensions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT95304957T 1994-08-18 1995-07-17 Vorrichtung und verfahren zur abtastung einer befehlswarteschlange ATE202644T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/292,649 US5630082A (en) 1993-10-29 1994-08-18 Apparatus and method for instruction queue scanning

Publications (1)

Publication Number Publication Date
ATE202644T1 true ATE202644T1 (de) 2001-07-15

Family

ID=23125583

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95304957T ATE202644T1 (de) 1994-08-18 1995-07-17 Vorrichtung und verfahren zur abtastung einer befehlswarteschlange

Country Status (6)

Country Link
US (2) US5630082A (de)
EP (1) EP0697650B1 (de)
JP (1) JP3714999B2 (de)
KR (1) KR100354324B1 (de)
AT (1) ATE202644T1 (de)
DE (1) DE69521461T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5822558A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
US5790824A (en) * 1996-03-18 1998-08-04 Advanced Micro Devices, Inc. Central processing unit including a DSP function preprocessor which scans instruction sequences for DSP functions
US6041403A (en) * 1996-09-27 2000-03-21 Intel Corporation Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction
DE19737658C2 (de) * 1996-10-18 1999-10-14 Nat Semiconductor Corp Befehlsdecoder für einen Mikroprozessor
US6148393A (en) * 1997-03-10 2000-11-14 Advanced Micro Devices, Inc. Apparatus for generating a valid mask
US5968163A (en) 1997-03-10 1999-10-19 Advanced Micro Devices, Inc. Microcode scan unit for scanning microcode instructions using predecode data
US6016544A (en) * 1997-06-09 2000-01-18 Ip First Llc Apparatus and method for tracking changes in address size and for different size retranslate second instruction with an indicator from address size
US5940602A (en) * 1997-06-11 1999-08-17 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations
US6105125A (en) * 1997-11-12 2000-08-15 National Semiconductor Corporation High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information
US6134649A (en) * 1997-11-17 2000-10-17 Advanced Micro Devices, Inc. Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction
US6167506A (en) 1997-11-17 2000-12-26 Advanced Micro Devices, Inc. Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
US6134650A (en) * 1997-12-12 2000-10-17 Advanced Micro Devices, Inc. Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data
US6061775A (en) * 1997-12-12 2000-05-09 Advanced Micro Devices, Inc. Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types
US6061786A (en) * 1998-04-23 2000-05-09 Advanced Micro Devices, Inc. Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction
WO2000000878A2 (en) * 1998-06-26 2000-01-06 Chi Lan Wong Derek Methods for increasing instruction-level parallelism in microprocessors and digital systems
US6988183B1 (en) 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US6636959B1 (en) 1999-10-14 2003-10-21 Advanced Micro Devices, Inc. Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition
US6647490B2 (en) 1999-10-14 2003-11-11 Advanced Micro Devices, Inc. Training line predictor for branch targets
US6546478B1 (en) 1999-10-14 2003-04-08 Advanced Micro Devices, Inc. Line predictor entry with location pointers and control information for corresponding instructions in a cache line
US6523108B1 (en) 1999-11-23 2003-02-18 Sony Corporation Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string
US20030188044A1 (en) * 2002-03-28 2003-10-02 International Business Machines Corporation System and method for verifying superscalar computer architectures
US7281120B2 (en) * 2004-03-26 2007-10-09 International Business Machines Corporation Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
US7774748B1 (en) * 2004-08-03 2010-08-10 Tensilica, Inc. System and method for automatic conversion of a partially-explicit instruction set to an explicit instruction set
CN100530164C (zh) 2007-12-29 2009-08-19 中国科学院计算技术研究所 一种risc处理器及其寄存器标志位处理方法
US8201067B2 (en) * 2008-02-25 2012-06-12 International Business Machines Corporation Processor error checking for instruction data
US10496412B2 (en) 2016-02-08 2019-12-03 International Business Machines Corporation Parallel dispatching of multi-operation instructions in a multi-slice computer processor
US11132599B2 (en) 2017-02-28 2021-09-28 Microsoft Technology Licensing, Llc Multi-function unit for programmable hardware nodes for neural network processing
US11467838B2 (en) * 2018-05-22 2022-10-11 Advanced Micro Devices, Inc. Fastpath microcode sequencer
CN111030788B (zh) * 2018-10-10 2022-05-31 上海朗帛通信技术有限公司 一种被用于无线通信的用户设备、基站中的方法和装置

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
AT354159B (de) * 1975-02-10 1979-12-27 Siemens Ag Assoziativspeicher mit getrennt assoziierbaren bereichen
US4179737A (en) * 1977-12-23 1979-12-18 Burroughs Corporation Means and methods for providing greater speed and flexibility of microinstruction sequencing
US4502111A (en) * 1981-05-29 1985-02-26 Harris Corporation Token generator
US4453212A (en) * 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4928223A (en) * 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
JPH0658631B2 (ja) * 1983-12-19 1994-08-03 株式会社日立製作所 デ−タ処理装置
US5426914A (en) * 1989-02-24 1995-06-27 Highland Supply Corporation Band applicator for applying a band about a sheet of material and a pot
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
CA1271561A (en) * 1986-07-02 1990-07-10 Jeffry M. Bram Instruction decoding microengines
CA1278382C (en) * 1986-12-15 1990-12-27 Brian J. Sprague Reduced instruction set computing apparatus and methods
US4992934A (en) * 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5131086A (en) * 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US5067069A (en) * 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
US5155816A (en) * 1989-02-10 1992-10-13 Intel Corporation Pipelined apparatus and method for controlled loading of floating point data in a microprocessor
US5155820A (en) * 1989-02-21 1992-10-13 Gibson Glenn A Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
JP2725450B2 (ja) * 1989-08-28 1998-03-11 日本電気株式会社 マイクロプロセッサ
US5185868A (en) * 1990-01-16 1993-02-09 Advanced Micro Devices, Inc. Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy
US5251306A (en) * 1990-01-16 1993-10-05 Advanced Micro Devices, Inc. Apparatus for controlling execution of a program in a computing device
US5128888A (en) * 1990-04-02 1992-07-07 Advanced Micro Devices, Inc. Arithmetic unit having multiple accumulators
CA2037708C (en) * 1990-05-04 1998-01-20 Richard J. Eickemeyer General purpose compound apparatus for instruction-level parallel processors
DE69123629T2 (de) * 1990-05-04 1997-06-12 International Business Machines Corp., Armonk, N.Y. Maschinenarchitektur für skalaren Verbundbefehlssatz
DE69130588T2 (de) * 1990-05-29 1999-05-27 National Semiconductor Corp., Santa Clara, Calif. Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
WO1992006426A1 (en) * 1990-10-09 1992-04-16 Nexgen Microsystems Method and apparatus for parallel decoding of instructions with branch prediction look-up
JPH04156613A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 命令バッファ装置
EP0498654B1 (de) * 1991-02-08 2000-05-10 Fujitsu Limited Cachespeicher zur Verarbeitung von Befehlsdaten und Datenprozessor mit demselben
JPH052484A (ja) * 1991-06-24 1993-01-08 Mitsubishi Electric Corp スーパースカラプロセツサ
KR100299691B1 (ko) * 1991-07-08 2001-11-22 구사마 사부로 확장가능알아이에스씨마이크로프로세서구조
US5345569A (en) * 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
SG45269A1 (en) * 1992-02-06 1998-01-16 Intel Corp End bit markers for instruction decode
GB2263985B (en) * 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5337415A (en) * 1992-12-04 1994-08-09 Hewlett-Packard Company Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency
IE80854B1 (en) * 1993-08-26 1999-04-07 Intel Corp Processor ordering consistency for a processor performing out-of-order instruction execution
EP0651320B1 (de) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
DE69429061T2 (de) * 1993-10-29 2002-07-18 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5632023A (en) * 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus

Also Published As

Publication number Publication date
KR960008542A (ko) 1996-03-22
EP0697650B1 (de) 2001-06-27
JPH08190482A (ja) 1996-07-23
JP3714999B2 (ja) 2005-11-09
KR100354324B1 (ko) 2003-01-08
DE69521461D1 (de) 2001-08-02
US5896518A (en) 1999-04-20
DE69521461T2 (de) 2002-04-18
EP0697650A3 (de) 1998-04-01
US5630082A (en) 1997-05-13
EP0697650A2 (de) 1996-02-21

Similar Documents

Publication Publication Date Title
ATE202644T1 (de) Vorrichtung und verfahren zur abtastung einer befehlswarteschlange
CA2029088A1 (en) Instructing method and execution system
DE69427265T2 (de) Superskalarbefehlsdekoder
EP0236745A3 (de) Verzweigungsstrom-Koprozessor
EP0380850A3 (de) Vorverarbeitung mehrerer Befehle
ES8700885A1 (es) Un dispositivo para identificar una etiqueta de codigo de barras adherida a una varilla alargada de combustible nuclear
GB2360111A (en) A method and apparatus for improved predicate prediction
CN1414468A (zh) 延伸微处理器指令集的装置及方法
FI981259A (fi) Menetelmä rungon kitkavastuksen vähentämiseksi, laiva, jonka kitkavastusta pienennetään menetelmällä ja menetelmä laivasta puhallettujen kuplien analysoimiseksi
DE69719235D1 (de) Prozessor und Verfahren zur spekulativen Ausführung von bedingten Verzweigungsbefehlen unter Verwendung einer von mehreren Verzweigungsvorhersageverfahren
KR100449238B1 (de)
EP0324308A3 (de) Dekodier-verfahren und -system für Befehle mit verschiedenen unvereinbaren Formaten
DE69826418D1 (de) Anordnung zum Abtasten mehrerer Instruktionen in einer Prozessorpipeline
PT927802E (pt) Mecanismo de fechadura
PL316532A1 (en) Data processing system and way of its operation
EP0087008A2 (de) Anordnung zur Operationsbefehlsdekodierung mit einer Mehrzahl von programmierbaren Logik-Matrizen
DK0624637T3 (da) Bifunktionel katalysator anvendelig ved hydroisomerisering af voks og fremgangsmåde til dens fremstilling
WO2001044929A2 (en) Length decoder to detect one-byte prefixes and branch instructions
NO975964L (no) Hj°rnekonstruksjon av pappdekket gipsplate og fremgangsmÕte for fremstilling av denne, samt hjelpedeler for utf°relse av fremgangsmÕten
KR900006853A (ko) 마이크로 프로세서
EP0170398B1 (de) Programmabtaster für Prozessor mit mehreren Daten und Instruktionsströmen
DE69421302D1 (de) Emulgierende Epoxydharzzusammensetzung und eine härtbare Zusammensetzung
WO2001069378A3 (en) Method and apparatus for enhancing the performance of a pipelined data processor
US6842852B1 (en) System and method for controlling conditional branching utilizing a control instruction having a reduced word length
FR2719545B1 (fr) Double coque allégée pour navire et sa méthode économique de fabrication.

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties