ATE201549T1 - Verfahren und anwendung zur herstellung von leiterplatten - Google Patents

Verfahren und anwendung zur herstellung von leiterplatten

Info

Publication number
ATE201549T1
ATE201549T1 AT93924845T AT93924845T ATE201549T1 AT E201549 T1 ATE201549 T1 AT E201549T1 AT 93924845 T AT93924845 T AT 93924845T AT 93924845 T AT93924845 T AT 93924845T AT E201549 T1 ATE201549 T1 AT E201549T1
Authority
AT
Austria
Prior art keywords
copper
foil
pct
layers
lamination
Prior art date
Application number
AT93924845T
Other languages
English (en)
Inventor
Bernt Ekstroem
Original Assignee
Foil Technology Dev Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Foil Technology Dev Corp filed Critical Foil Technology Dev Corp
Application granted granted Critical
Publication of ATE201549T1 publication Critical patent/ATE201549T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/068—Features of the lamination press or of the lamination process, e.g. using special separator sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Reinforced Plastic Materials (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • General Factory Administration (AREA)
AT93924845T 1992-11-06 1993-09-30 Verfahren und anwendung zur herstellung von leiterplatten ATE201549T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9203327A SE9203327L (sv) 1992-11-06 1992-11-06 Förfarande vid mönsterkortstillverkning samt användning därvid
PCT/SE1993/000786 WO1994012008A1 (en) 1992-11-06 1993-09-30 Process for production of printed circuit boards and use thereby

Publications (1)

Publication Number Publication Date
ATE201549T1 true ATE201549T1 (de) 2001-06-15

Family

ID=20387737

Family Applications (1)

Application Number Title Priority Date Filing Date
AT93924845T ATE201549T1 (de) 1992-11-06 1993-09-30 Verfahren und anwendung zur herstellung von leiterplatten

Country Status (8)

Country Link
US (1) US5617629A (de)
EP (1) EP0672334B1 (de)
JP (1) JPH08503174A (de)
AT (1) ATE201549T1 (de)
AU (1) AU5435394A (de)
DE (1) DE69330253D1 (de)
SE (1) SE9203327L (de)
WO (1) WO1994012008A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6085414A (en) * 1996-08-15 2000-07-11 Packard Hughes Interconnect Company Method of making a flexible circuit with raised features protruding from two surfaces and products therefrom
DE69926939T2 (de) * 1998-04-01 2006-07-13 Mitsui Mining & Smelting Co., Ltd. Verfahren zur Herstellung einer mehrschichtigen gedruckten Leiterplatte
JP3612594B2 (ja) * 1998-05-29 2005-01-19 三井金属鉱業株式会社 樹脂付複合箔およびその製造方法並びに該複合箔を用いた多層銅張り積層板および多層プリント配線板の製造方法
US6183880B1 (en) 1998-08-07 2001-02-06 Mitsui Mining & Smelting Co., Ltd. Composite foil of aluminum and copper
AU2105300A (en) * 1999-01-14 2000-08-01 Hans-Jurgen Schafer Method and device for producing copper foil which is coated with polymers on both sides and which is laminated onto printed circuit boards
US6356002B1 (en) * 1999-02-08 2002-03-12 Northrop Grumman Corporation Electrical slip ring having a higher circuit density
US6569543B2 (en) 2001-02-15 2003-05-27 Olin Corporation Copper foil with low profile bond enahncement
US6379487B1 (en) * 2000-05-05 2002-04-30 Ga-Tek Inc. Component of printed circuit board
US6467138B1 (en) * 2000-05-24 2002-10-22 Vermon Integrated connector backings for matrix array transducers, matrix array transducers employing such backings and methods of making the same
US6454878B1 (en) * 2000-11-01 2002-09-24 Visteon Global Technologies, Inc. Cladded material construction for etched-tri-metal circuits
US6588099B2 (en) * 2001-01-22 2003-07-08 Sankyo Kasei Kabushiki Kaisha Process for manufacturing molded circuit board
US6893742B2 (en) * 2001-02-15 2005-05-17 Olin Corporation Copper foil with low profile bond enhancement
US6984915B2 (en) 2002-01-22 2006-01-10 Electro-Tec Corp. Electrical slip ring platter multilayer printed circuit board and method for making same
US7132158B2 (en) * 2003-10-22 2006-11-07 Olin Corporation Support layer for thin copper foil
JP3972895B2 (ja) * 2003-12-10 2007-09-05 松下電器産業株式会社 回路基板の製造方法
JP4570070B2 (ja) * 2004-03-16 2010-10-27 三井金属鉱業株式会社 絶縁層形成用の樹脂層を備えたキャリア箔付電解銅箔、銅張積層板、プリント配線板、多層銅張積層板の製造方法及びプリント配線板の製造方法
US8861167B2 (en) 2011-05-12 2014-10-14 Global Plasma Solutions, Llc Bipolar ionization device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE29820E (en) * 1971-08-30 1978-10-31 Perstorp, Ab Method for the production of material for printed circuits
BE788117A (fr) * 1971-08-30 1973-02-28 Perstorp Ab Procede de production d'elements pour circuits imprimes
US3936548A (en) * 1973-02-28 1976-02-03 Perstorp Ab Method for the production of material for printed circuits and material for printed circuits
DE2413932C2 (de) 1973-04-25 1984-08-30 Yates Industries, Inc., Bordentown, N.J. Verfahren zum Herstellen einer Verbundfolie für die Ausbildung gedruckter Schaltkreise
US4073699A (en) * 1976-03-01 1978-02-14 Hutkin Irving J Method for making copper foil
US4088544A (en) * 1976-04-19 1978-05-09 Hutkin Irving J Composite and method for making thin copper foil
US4401521A (en) * 1980-11-28 1983-08-30 Asahi Kasei Kogyo Kabushiki Kaisha Method for manufacturing a fine-patterned thick film conductor structure
US4503112A (en) * 1981-06-12 1985-03-05 Oak Industries Inc. Printed circuit material
US4394419A (en) * 1981-06-12 1983-07-19 Oak Industries Inc. Printed circuit material
US4421608A (en) * 1982-03-01 1983-12-20 International Business Machines Corporation Method for stripping peel apart conductive structures
GB8333753D0 (en) * 1983-12-19 1984-01-25 Thorpe J E Dielectric boards
US5049434A (en) * 1984-04-30 1991-09-17 National Starch And Chemical Investment Holding Corporation Pre-patterned device substrate device-attach adhesive transfer system
JPS63103075A (ja) * 1986-10-14 1988-05-07 エドワ−ド　アドラ− マイクロ樹枝状体配列を介して結合された金属層で被覆可能とされる表面を有する樹脂製品並びに該金属層被覆樹脂製品

Also Published As

Publication number Publication date
SE470277B (sv) 1993-12-20
WO1994012008A1 (en) 1994-05-26
US5617629A (en) 1997-04-08
AU5435394A (en) 1994-06-08
SE9203327D0 (sv) 1992-11-06
JPH08503174A (ja) 1996-04-09
DE69330253D1 (de) 2001-06-28
EP0672334A1 (de) 1995-09-20
SE9203327L (sv) 1993-12-20
EP0672334B1 (de) 2001-05-23

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties