ATE172802T1 - Anordnung und verfahren zur auflösung von abhängigkeiten unter mehreren befehlen in einer speicheranordnung - Google Patents

Anordnung und verfahren zur auflösung von abhängigkeiten unter mehreren befehlen in einer speicheranordnung

Info

Publication number
ATE172802T1
ATE172802T1 AT92307185T AT92307185T ATE172802T1 AT E172802 T1 ATE172802 T1 AT E172802T1 AT 92307185 T AT92307185 T AT 92307185T AT 92307185 T AT92307185 T AT 92307185T AT E172802 T1 ATE172802 T1 AT E172802T1
Authority
AT
Austria
Prior art keywords
hit
enable signal
circuit generates
signal
storage device
Prior art date
Application number
AT92307185T
Other languages
English (en)
Inventor
Thang Minh Tran
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE172802T1 publication Critical patent/ATE172802T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/123—Contention resolution, i.e. resolving conflicts between simultaneous read and write operations
AT92307185T 1991-09-20 1992-08-06 Anordnung und verfahren zur auflösung von abhängigkeiten unter mehreren befehlen in einer speicheranordnung ATE172802T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/764,155 US5345569A (en) 1991-09-20 1991-09-20 Apparatus and method for resolving dependencies among a plurality of instructions within a storage device

Publications (1)

Publication Number Publication Date
ATE172802T1 true ATE172802T1 (de) 1998-11-15

Family

ID=25069840

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92307185T ATE172802T1 (de) 1991-09-20 1992-08-06 Anordnung und verfahren zur auflösung von abhängigkeiten unter mehreren befehlen in einer speicheranordnung

Country Status (5)

Country Link
US (1) US5345569A (de)
EP (1) EP0533337B1 (de)
JP (1) JP3342894B2 (de)
AT (1) ATE172802T1 (de)
DE (1) DE69227429T2 (de)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5826055A (en) * 1991-07-08 1998-10-20 Seiko Epson Corporation System and method for retiring instructions in a superscalar microprocessor
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
JP3637920B2 (ja) 1992-05-01 2005-04-13 セイコーエプソン株式会社 スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
KR100248903B1 (ko) * 1992-09-29 2000-03-15 야스카와 히데아키 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp System und Verfahren zur Änderung der Namen von Registern
US5604912A (en) * 1992-12-31 1997-02-18 Seiko Epson Corporation System and method for assigning tags to instructions to control instruction execution
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5465373A (en) * 1993-01-08 1995-11-07 International Business Machines Corporation Method and system for single cycle dispatch of multiple instructions in a superscalar processor system
KR0122528B1 (ko) * 1993-01-08 1997-11-20 윌리엄 티.엘리스 슈퍼스칼라 프로세서 시스템에서 중간 기억 버퍼의 할당을 인덱스하기 위한 방법 및 시스템
US5493669A (en) * 1993-03-03 1996-02-20 Motorola, Inc. Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits
US5627984A (en) * 1993-03-31 1997-05-06 Intel Corporation Apparatus and method for entry allocation for a buffer resource utilizing an internal two cycle pipeline
JPH06337843A (ja) * 1993-05-28 1994-12-06 Fujitsu Ltd データ転送制御方法
TW242673B (de) * 1993-08-18 1995-03-11 Ibm
US5826094A (en) * 1993-09-30 1998-10-20 Intel Corporation Register alias table update to indicate architecturally visible state
US5740393A (en) * 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US6138230A (en) * 1993-10-18 2000-10-24 Via-Cyrix, Inc. Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline
DE69427265T2 (de) * 1993-10-29 2002-05-02 Advanced Micro Devices Inc Superskalarbefehlsdekoder
US5878245A (en) 1993-10-29 1999-03-02 Advanced Micro Devices, Inc. High performance load/store functional unit and data cache
DE69429061T2 (de) * 1993-10-29 2002-07-18 Advanced Micro Devices Inc Superskalarmikroprozessoren
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
US6128721A (en) * 1993-11-17 2000-10-03 Sun Microsystems, Inc. Temporary pipeline register file for a superpipelined superscalar processor
US6101597A (en) * 1993-12-30 2000-08-08 Intel Corporation Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor
US6393550B1 (en) * 1993-12-30 2002-05-21 Intel Corporation Method and apparatus for pipeline streamlining where resources are immediate or certainly retired
US5564028A (en) * 1994-01-11 1996-10-08 Texas Instruments Incorporated Pipelined data processing including instruction trace
US5553256A (en) * 1994-02-28 1996-09-03 Intel Corporation Apparatus for pipeline streamlining where resources are immediate or certainly retired
DE69531933T2 (de) * 1994-03-01 2004-08-12 Intel Corp., Santa Clara Busarchitektur in hochgradiger pipeline-ausführung
US5564056A (en) * 1994-03-01 1996-10-08 Intel Corporation Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
US5490280A (en) * 1994-03-31 1996-02-06 Intel Corporation Apparatus and method for entry allocation for a resource buffer
US5689693A (en) * 1994-04-26 1997-11-18 Advanced Micro Devices, Inc. Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead
US5535345A (en) * 1994-05-12 1996-07-09 Intel Corporation Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed
US5465336A (en) * 1994-06-30 1995-11-07 International Business Machines Corporation Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
US5901302A (en) * 1995-01-25 1999-05-04 Advanced Micro Devices, Inc. Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions
US5878244A (en) * 1995-01-25 1999-03-02 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received
US6237082B1 (en) 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
EP0724215A1 (de) * 1995-01-26 1996-07-31 Sun Microsystems, Inc. Verfahren und Anordnung zum Rückgängigmachen von falsch vorhergesagten Verzweigungen in einem Pipeline-Prozessor
US5764946A (en) * 1995-04-12 1998-06-09 Advanced Micro Devices Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
US5848433A (en) * 1995-04-12 1998-12-08 Advanced Micro Devices Way prediction unit and a method for operating the same
US5634026A (en) * 1995-05-12 1997-05-27 International Business Machines Corporation Source identifier for result forwarding
US5617543A (en) * 1995-05-26 1997-04-01 National Semiconductor Corporation Non-arithmetical circular buffer cell availability status indicator circuit
US6112019A (en) * 1995-06-12 2000-08-29 Georgia Tech Research Corp. Distributed instruction queue
US6038657A (en) * 1995-10-06 2000-03-14 Advanced Micro Devices, Inc. Scan chains for out-of-order load/store execution control
US5754812A (en) * 1995-10-06 1998-05-19 Advanced Micro Devices, Inc. Out-of-order load/store execution control
US5933618A (en) * 1995-10-30 1999-08-03 Advanced Micro Devices, Inc. Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction
US5765035A (en) * 1995-11-20 1998-06-09 Advanced Micro Devices, Inc. Recorder buffer capable of detecting dependencies between accesses to a pair of caches
US5961580A (en) * 1996-02-20 1999-10-05 Advanced Micro Devices, Inc. Apparatus and method for efficiently calculating a linear address in a microprocessor
US5809275A (en) * 1996-03-01 1998-09-15 Hewlett-Packard Company Store-to-load hazard resolution system and method for a processor that executes instructions out of order
US5838942A (en) * 1996-03-01 1998-11-17 Hewlett-Packard Company Panic trap system and method
US6085302A (en) * 1996-04-17 2000-07-04 Advanced Micro Devices, Inc. Microprocessor having address generation units for efficient generation of memory operation addresses
US5835968A (en) * 1996-04-17 1998-11-10 Advanced Micro Devices, Inc. Apparatus for providing memory and register operands concurrently to functional units
US5761474A (en) * 1996-05-24 1998-06-02 Hewlett-Packard Co. Operand dependency tracking system and method for a processor that executes instructions out of order
US5805851A (en) * 1996-06-13 1998-09-08 Hewlett-Packard Co. System for determining data dependencies among intra-bundle instructions queued and prior instructions in the queue
US5946468A (en) * 1996-07-26 1999-08-31 Advanced Micro Devices, Inc. Reorder buffer having an improved future file for storing speculative instruction execution results
US5915110A (en) * 1996-07-26 1999-06-22 Advanced Micro Devices, Inc. Branch misprediction recovery in a reorder buffer having a future file
US5872951A (en) * 1996-07-26 1999-02-16 Advanced Micro Design, Inc. Reorder buffer having a future file for storing speculative instruction execution results
US5838944A (en) * 1996-07-31 1998-11-17 Hewlett-Packard Company System for storing processor register data after a mispredicted branch
US5983342A (en) * 1996-09-12 1999-11-09 Advanced Micro Devices, Inc. Superscalar microprocessor employing a future file for storing results into multiportion registers
US5848256A (en) * 1996-09-30 1998-12-08 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for address disambiguation using address component identifiers
US5805907A (en) * 1996-10-04 1998-09-08 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US5870616A (en) * 1996-10-04 1999-02-09 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US5860014A (en) * 1996-10-15 1999-01-12 International Business Machines Corporation Method and apparatus for improved recovery of processor state using history buffer
US5870612A (en) * 1996-10-15 1999-02-09 International Business Machines Corporation Method and apparatus for condensed history buffer
US5805906A (en) * 1996-10-15 1998-09-08 International Business Machines Corporation Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions
US6016540A (en) * 1997-01-08 2000-01-18 Intel Corporation Method and apparatus for scheduling instructions in waves
US5923900A (en) * 1997-03-10 1999-07-13 International Business Machines Corporation Circular buffer with n sequential real and virtual entry positions for selectively inhibiting n adjacent entry positions including the virtual entry positions
US6148393A (en) * 1997-03-10 2000-11-14 Advanced Micro Devices, Inc. Apparatus for generating a valid mask
US5930521A (en) * 1997-04-15 1999-07-27 Industrial Technology Research Institute Reorder buffer architecture for accessing partial word operands
US6073230A (en) * 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
US6070235A (en) * 1997-07-14 2000-05-30 International Business Machines Corporation Data processing system and method for capturing history buffer data
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6094716A (en) * 1998-07-14 2000-07-25 Advanced Micro Devices, Inc. Register renaming in which moves are accomplished by swapping rename tags
US6240503B1 (en) 1998-11-12 2001-05-29 Advanced Micro Devices, Inc. Cumulative lookahead to eliminate chained dependencies
JP3851228B2 (ja) * 2002-06-14 2006-11-29 松下電器産業株式会社 プロセッサ、プログラム変換装置及びプログラム変換方法、並びにコンピュータプログラム
US20040168045A1 (en) * 2003-02-21 2004-08-26 Dale Morris Out-of-order processor executing speculative-load instructions
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7043626B1 (en) 2003-10-01 2006-05-09 Advanced Micro Devices, Inc. Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
US20060149931A1 (en) * 2004-12-28 2006-07-06 Akkary Haitham Runahead execution in a central processing unit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4714994A (en) * 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
JPH0731615B2 (ja) * 1986-04-18 1995-04-10 日本電気株式会社 情報処理装置
US5125083A (en) * 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

Also Published As

Publication number Publication date
JPH05250159A (ja) 1993-09-28
EP0533337A1 (de) 1993-03-24
JP3342894B2 (ja) 2002-11-11
DE69227429D1 (de) 1998-12-03
EP0533337B1 (de) 1998-10-28
DE69227429T2 (de) 1999-06-10
US5345569A (en) 1994-09-06

Similar Documents

Publication Publication Date Title
ATE172802T1 (de) Anordnung und verfahren zur auflösung von abhängigkeiten unter mehreren befehlen in einer speicheranordnung
KR100371930B1 (de)
DE3486399D1 (de) Zentrale Verarbeitungseinheit mit der Fähigkeit, Befehle mit variablen Längen zu unterstützen.
ATE185205T1 (de) Risc mikroprozessorarchitektur mit mehrere registersätze von unterschiedlichen typen
DE68928812D1 (de) Vorrichtung zur Auflösung von einer variablen Anzahl von möglichen Speicherzugriffskonflikten in einem Pipeline-Rechnersystem und Verfahren dazu
SE8302511D0 (sv) Anordning for att skydda mot obehorig lesning av programord som er lagrade i ett minne
KR910012962A (ko) Dma제어기
KR930014089A (ko) 데이터 전송 장치
ID30041A (id) Metode dan alat pemroses informasi, dan media penyimpan program
KR850004821A (ko) 버퍼 스토레이지 시스템(buffer storage system)
KR840007190A (ko) 버퍼기억장치의 단일비트 에러처리 시스템
KR860000595A (ko) 정보처리장치를 위한 메모리액세스 제어방식
KR960001991A (ko) 정보 처리 장치
KR910001542A (ko) 정보 처리 장치의 비교 체크 기능 검사를 위한 시스템
GB2016753A (en) Data Processing System
DE69224710D1 (de) Geräteverwaltungssystem in einem Rechnerssystem
IT1165293B (it) Dispositivo per determinare la lunghezza di registri di spostamento
SE9501015L (sv) Anordning och förfarande avseende hantering av digitala signaler och en behandlingsanordning omfattande en dylik
DE68925524D1 (de) System zum Detektieren, dass Daten in einem Pufferspeicher gelöscht worden sind, insbesondere für einen Datenschalter
JPS6419387A (en) Bit map processor
KR890005607A (ko) 데이타 처리 시스템
DE58909627D1 (de) Anordnung zum Übertragen von in mehrere Teile unterteilten Datenwörtern
ATE408194T1 (de) Verfahren zur schnellen kommunikation in einem parallelen computersystem und mit diesem verfahren betriebenes paralleles computersystem
DE69231241D1 (de) Gerät und Verfahren zur Datenverarbeitung
ATE213865T1 (de) Verfahren und vorrichtung zur messung und registrierung von statistischen zeitänderungen für einen optischen datenträger

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties