JP3342894B2 - 記憶装置内の複数の命令間の依存を解決するための装置および方法 - Google Patents

記憶装置内の複数の命令間の依存を解決するための装置および方法

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Publication number
JP3342894B2
JP3342894B2 JP25014592A JP25014592A JP3342894B2 JP 3342894 B2 JP3342894 B2 JP 3342894B2 JP 25014592 A JP25014592 A JP 25014592A JP 25014592 A JP25014592 A JP 25014592A JP 3342894 B2 JP3342894 B2 JP 3342894B2
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JP
Japan
Prior art keywords
instructions
hit
instruction
enable
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25014592A
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English (en)
Japanese (ja)
Other versions
JPH05250159A (ja
Inventor
タン・ミン・トラン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JPH05250159A publication Critical patent/JPH05250159A/ja
Application granted granted Critical
Publication of JP3342894B2 publication Critical patent/JP3342894B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/123—Contention resolution, i.e. resolving conflicts between simultaneous read and write operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)
JP25014592A 1991-09-20 1992-09-18 記憶装置内の複数の命令間の依存を解決するための装置および方法 Expired - Lifetime JP3342894B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/764,155 US5345569A (en) 1991-09-20 1991-09-20 Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
US764155 1991-09-20

Publications (2)

Publication Number Publication Date
JPH05250159A JPH05250159A (ja) 1993-09-28
JP3342894B2 true JP3342894B2 (ja) 2002-11-11

Family

ID=25069840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25014592A Expired - Lifetime JP3342894B2 (ja) 1991-09-20 1992-09-18 記憶装置内の複数の命令間の依存を解決するための装置および方法

Country Status (5)

Country Link
US (1) US5345569A (de)
EP (1) EP0533337B1 (de)
JP (1) JP3342894B2 (de)
AT (1) ATE172802T1 (de)
DE (1) DE69227429T2 (de)

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Also Published As

Publication number Publication date
US5345569A (en) 1994-09-06
EP0533337B1 (de) 1998-10-28
JPH05250159A (ja) 1993-09-28
DE69227429T2 (de) 1999-06-10
ATE172802T1 (de) 1998-11-15
DE69227429D1 (de) 1998-12-03
EP0533337A1 (de) 1993-03-24

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