ATE156278T1 - Verfahren und vorrichtung zum ordnen und in warteschlangesetzen mehrerer speicherzugriffsanforderungen - Google Patents

Verfahren und vorrichtung zum ordnen und in warteschlangesetzen mehrerer speicherzugriffsanforderungen

Info

Publication number
ATE156278T1
ATE156278T1 AT90300877T AT90300877T ATE156278T1 AT E156278 T1 ATE156278 T1 AT E156278T1 AT 90300877 T AT90300877 T AT 90300877T AT 90300877 T AT90300877 T AT 90300877T AT E156278 T1 ATE156278 T1 AT E156278T1
Authority
AT
Austria
Prior art keywords
request
memory access
requests
prioritization scheme
memory
Prior art date
Application number
AT90300877T
Other languages
English (en)
Inventor
David A Webb Jr
John E Murray
Ricky C Hetherington
Tryggve Fossum
Dwight P Manley
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE156278T1 publication Critical patent/ATE156278T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Memory System (AREA)
AT90300877T 1989-02-03 1990-01-29 Verfahren und vorrichtung zum ordnen und in warteschlangesetzen mehrerer speicherzugriffsanforderungen ATE156278T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,870 US5222223A (en) 1989-02-03 1989-02-03 Method and apparatus for ordering and queueing multiple memory requests

Publications (1)

Publication Number Publication Date
ATE156278T1 true ATE156278T1 (de) 1997-08-15

Family

ID=23187232

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90300877T ATE156278T1 (de) 1989-02-03 1990-01-29 Verfahren und vorrichtung zum ordnen und in warteschlangesetzen mehrerer speicherzugriffsanforderungen

Country Status (7)

Country Link
US (1) US5222223A (de)
EP (1) EP0391517B1 (de)
JP (1) JPH02289013A (de)
AT (1) ATE156278T1 (de)
AU (1) AU628530B2 (de)
CA (1) CA1325285C (de)
DE (1) DE69031139T2 (de)

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Also Published As

Publication number Publication date
JPH0526215B2 (de) 1993-04-15
AU628530B2 (en) 1992-09-17
DE69031139D1 (de) 1997-09-04
DE69031139T2 (de) 1998-02-19
AU5394790A (en) 1991-12-19
CA1325285C (en) 1993-12-14
EP0391517B1 (de) 1997-07-30
JPH02289013A (ja) 1990-11-29
EP0391517A3 (de) 1992-09-02
EP0391517A2 (de) 1990-10-10
US5222223A (en) 1993-06-22

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