WO1989006397A3 - Method for prefetching vector data from memory in a memory system designed for scalar processing - Google Patents

Method for prefetching vector data from memory in a memory system designed for scalar processing Download PDF

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Publication number
WO1989006397A3
WO1989006397A3 PCT/US1989/000021 US8900021W WO8906397A3 WO 1989006397 A3 WO1989006397 A3 WO 1989006397A3 US 8900021 W US8900021 W US 8900021W WO 8906397 A3 WO8906397 A3 WO 8906397A3
Authority
WO
WIPO (PCT)
Prior art keywords
vector
cache
main memory
memory
processor
Prior art date
Application number
PCT/US1989/000021
Other languages
French (fr)
Other versions
WO1989006397A2 (en
Inventor
Tryggve Fossum
Ricky C Hetherington
David B Fite Jr
Dwight P Manley
Francis X Mckeen
John E Murray
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to DE68911398T priority Critical patent/DE68911398T2/en
Publication of WO1989006397A2 publication Critical patent/WO1989006397A2/en
Publication of WO1989006397A3 publication Critical patent/WO1989006397A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8061—Details on data memory access
    • G06F15/8069—Details on data memory access using a cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Abstract

A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a ''miss'' and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache. The scalar processor includes a microcode interpreter which sends a vector load command to the vector processing unit and which also generates vector prefetch requests. The addresses for the data blocks to be prefetched are computed based upon the vector address, the length of the vector and the ''stride'' or spacing between the addresses of the elements of the vector.
PCT/US1989/000021 1988-01-11 1989-01-04 Method for prefetching vector data from memory in a memory system designed for scalar processing WO1989006397A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE68911398T DE68911398T2 (en) 1988-01-11 1989-01-04 METHOD AND DIGITAL COMPUTER FOR Fetching VECTOR DATA FROM THE STORAGE IN A STORAGE SYSTEM DESIGNED FOR SCALE PROCESSING.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US142,794 1988-01-11
US07/142,794 US4888679A (en) 1988-01-11 1988-01-11 Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements

Publications (2)

Publication Number Publication Date
WO1989006397A2 WO1989006397A2 (en) 1989-07-13
WO1989006397A3 true WO1989006397A3 (en) 1989-08-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1989/000021 WO1989006397A2 (en) 1988-01-11 1989-01-04 Method for prefetching vector data from memory in a memory system designed for scalar processing

Country Status (6)

Country Link
US (1) US4888679A (en)
EP (1) EP0348495B1 (en)
AU (1) AU2939689A (en)
CA (1) CA1317032C (en)
DE (1) DE68911398T2 (en)
WO (1) WO1989006397A2 (en)

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Also Published As

Publication number Publication date
US4888679A (en) 1989-12-19
DE68911398T2 (en) 1994-06-09
DE68911398D1 (en) 1994-01-27
CA1317032C (en) 1993-04-27
EP0348495B1 (en) 1993-12-15
WO1989006397A2 (en) 1989-07-13
EP0348495A1 (en) 1990-01-03
AU2939689A (en) 1989-08-01

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