ATE130446T1 - Selbstgetakteter registerspeicher. - Google Patents

Selbstgetakteter registerspeicher.

Info

Publication number
ATE130446T1
ATE130446T1 AT89309849T AT89309849T ATE130446T1 AT E130446 T1 ATE130446 T1 AT E130446T1 AT 89309849 T AT89309849 T AT 89309849T AT 89309849 T AT89309849 T AT 89309849T AT E130446 T1 ATE130446 T1 AT E130446T1
Authority
AT
Austria
Prior art keywords
clock
streg
clock signal
high speed
clock pulse
Prior art date
Application number
AT89309849T
Other languages
English (en)
Inventor
William R Grundmann
Valerie R Hay
Lawrence O Herman
Dennis M Litwinetz
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE130446T1 publication Critical patent/ATE130446T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Shift Register Type Memory (AREA)
  • Information Transfer Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT89309849T 1989-02-03 1989-09-27 Selbstgetakteter registerspeicher. ATE130446T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,445 US5107462A (en) 1989-02-03 1989-02-03 Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink

Publications (1)

Publication Number Publication Date
ATE130446T1 true ATE130446T1 (de) 1995-12-15

Family

ID=23185313

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89309849T ATE130446T1 (de) 1989-02-03 1989-09-27 Selbstgetakteter registerspeicher.

Country Status (6)

Country Link
US (1) US5107462A (de)
EP (1) EP0380860B1 (de)
JP (1) JPH02235289A (de)
AT (1) ATE130446T1 (de)
AU (1) AU628162B2 (de)
DE (1) DE68924842T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2043493C (en) * 1990-10-05 1997-04-01 Ricky C. Hetherington Hierarchical integrated circuit cache memory
US5339399A (en) * 1991-04-12 1994-08-16 Intel Corporation Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
US5721875A (en) * 1993-11-12 1998-02-24 Intel Corporation I/O transceiver having a pulsed latch receiver circuit
US5727184A (en) * 1994-06-27 1998-03-10 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5812858A (en) * 1994-09-16 1998-09-22 Cirrus Logic, Inc. Method and apparatus for providing register and interrupt compatibility between non-identical integrated circuits
US6289476B1 (en) * 1998-06-10 2001-09-11 Micron Technology, Inc. Method and apparatus for testing the timing of integrated circuits
US20070133083A1 (en) * 2005-12-07 2007-06-14 Kangaslahti Pekka P Waveguide apparatus with integrated amplifier and associated transitions

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49122940A (de) * 1973-03-26 1974-11-25
US4176400A (en) * 1977-08-10 1979-11-27 Teletype Corporation Buffer storage and control
JPS5549091A (en) * 1978-10-04 1980-04-08 Hitachi Ltd Information coding circuit
JPS60247891A (ja) * 1984-05-23 1985-12-07 Hitachi Ltd 半導体メモリ
US4663741A (en) * 1984-10-16 1987-05-05 Trilogy Systems Corporation Strobed access semiconductor memory system
US4623990A (en) * 1984-10-31 1986-11-18 Advanced Micro Devices, Inc. Dual-port read/write RAM with single array
US4712190A (en) * 1985-01-25 1987-12-08 Digital Equipment Corporation Self-timed random access memory chip
JPS61222088A (ja) * 1985-03-28 1986-10-02 Nec Corp バイポ−ラ集積回路
US4933909A (en) * 1988-12-19 1990-06-12 Bull Hn Information Systems Inc. Dual read/write register file memory

Also Published As

Publication number Publication date
EP0380860B1 (de) 1995-11-15
AU628162B2 (en) 1992-09-10
US5107462A (en) 1992-04-21
JPH02235289A (ja) 1990-09-18
DE68924842T2 (de) 1996-07-18
AU5394190A (en) 1991-12-19
EP0380860A2 (de) 1990-08-08
EP0380860A3 (de) 1992-03-25
DE68924842D1 (de) 1995-12-21

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Legal Events

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