ATE12708T1 - Verfahren und vorrichtung zum steuern von konflikten bei mehrfachzugriffen zum selben cache-speicher eines digitalen datenverarbeitungssystems mit zumindest zwei, je einen cache enthaltenden, prozessoren. - Google Patents

Verfahren und vorrichtung zum steuern von konflikten bei mehrfachzugriffen zum selben cache-speicher eines digitalen datenverarbeitungssystems mit zumindest zwei, je einen cache enthaltenden, prozessoren.

Info

Publication number
ATE12708T1
ATE12708T1 AT81400062T AT81400062T ATE12708T1 AT E12708 T1 ATE12708 T1 AT E12708T1 AT 81400062 T AT81400062 T AT 81400062T AT 81400062 T AT81400062 T AT 81400062T AT E12708 T1 ATE12708 T1 AT E12708T1
Authority
AT
Austria
Prior art keywords
cache memory
processors
data processing
processing system
event
Prior art date
Application number
AT81400062T
Other languages
English (en)
Inventor
Pierre Charles Augustin Bacot
Michel Isert
Original Assignee
Cii Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cii Honeywell Bull filed Critical Cii Honeywell Bull
Application granted granted Critical
Publication of ATE12708T1 publication Critical patent/ATE12708T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
AT81400062T 1980-01-22 1981-01-19 Verfahren und vorrichtung zum steuern von konflikten bei mehrfachzugriffen zum selben cache-speicher eines digitalen datenverarbeitungssystems mit zumindest zwei, je einen cache enthaltenden, prozessoren. ATE12708T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8001351A FR2474201B1 (fr) 1980-01-22 1980-01-22 Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache
EP81400062A EP0032863B1 (de) 1980-01-22 1981-01-19 Verfahren und Vorrichtung zum Steuern von Konflikten bei Mehrfachzugriffen zum selben CACHE-Speicher eines digitalen Datenverarbeitungssystems mit zumindest zwei, je einen CACHE enthaltenden, Prozessoren

Publications (1)

Publication Number Publication Date
ATE12708T1 true ATE12708T1 (de) 1985-04-15

Family

ID=9237760

Family Applications (1)

Application Number Title Priority Date Filing Date
AT81400062T ATE12708T1 (de) 1980-01-22 1981-01-19 Verfahren und vorrichtung zum steuern von konflikten bei mehrfachzugriffen zum selben cache-speicher eines digitalen datenverarbeitungssystems mit zumindest zwei, je einen cache enthaltenden, prozessoren.

Country Status (5)

Country Link
US (1) US4426681A (de)
EP (1) EP0032863B1 (de)
AT (1) ATE12708T1 (de)
DE (1) DE3169774D1 (de)
FR (1) FR2474201B1 (de)

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Also Published As

Publication number Publication date
DE3169774D1 (en) 1985-05-15
FR2474201B1 (fr) 1986-05-16
US4426681A (en) 1984-01-17
EP0032863B1 (de) 1985-04-10
EP0032863A1 (de) 1981-07-29
FR2474201A1 (fr) 1981-07-24

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