AT302417B - Verfahren zum Herstellen eines Transistors mit einer integrierten Schottky-Sperrdiode - Google Patents

Verfahren zum Herstellen eines Transistors mit einer integrierten Schottky-Sperrdiode

Info

Publication number
AT302417B
AT302417B AT1104668A AT1104668A AT302417B AT 302417 B AT302417 B AT 302417B AT 1104668 A AT1104668 A AT 1104668A AT 1104668 A AT1104668 A AT 1104668A AT 302417 B AT302417 B AT 302417B
Authority
AT
Austria
Prior art keywords
transistor
manufacturing
schottky barrier
barrier diode
integrated schottky
Prior art date
Application number
AT1104668A
Other languages
German (de)
English (en)
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Application granted granted Critical
Publication of AT302417B publication Critical patent/AT302417B/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/617Combinations of vertical BJTs and only diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
AT1104668A 1967-11-15 1968-11-13 Verfahren zum Herstellen eines Transistors mit einer integrierten Schottky-Sperrdiode AT302417B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US68323867A 1967-11-15 1967-11-15

Publications (1)

Publication Number Publication Date
AT302417B true AT302417B (de) 1972-10-10

Family

ID=24743141

Family Applications (1)

Application Number Title Priority Date Filing Date
AT1104668A AT302417B (de) 1967-11-15 1968-11-13 Verfahren zum Herstellen eines Transistors mit einer integrierten Schottky-Sperrdiode

Country Status (9)

Country Link
AT (1) AT302417B (enrdf_load_stackoverflow)
BE (1) BE723876A (enrdf_load_stackoverflow)
CH (1) CH479163A (enrdf_load_stackoverflow)
DE (1) DE1808342A1 (enrdf_load_stackoverflow)
ES (1) ES360641A1 (enrdf_load_stackoverflow)
FR (1) FR1591489A (enrdf_load_stackoverflow)
GB (1) GB1252565A (enrdf_load_stackoverflow)
NL (1) NL6816152A (enrdf_load_stackoverflow)
SE (1) SE341222B (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614560A (en) * 1969-12-30 1971-10-19 Ibm Improved surface barrier transistor
CA965189A (en) * 1972-01-03 1975-03-25 Signetics Corporation Semiconductor structure using platinel silicide as a schottky barrier diode and method
US4035831A (en) * 1975-04-17 1977-07-12 Agency Of Industrial Science & Technology Radial emitter pressure contact type semiconductor devices
US4233337A (en) * 1978-05-01 1980-11-11 International Business Machines Corporation Method for forming semiconductor contacts

Also Published As

Publication number Publication date
GB1252565A (enrdf_load_stackoverflow) 1971-11-10
BE723876A (enrdf_load_stackoverflow) 1969-04-16
DE1808342B2 (enrdf_load_stackoverflow) 1970-09-10
DE1808342A1 (de) 1970-04-09
CH479163A (de) 1969-09-30
NL6816152A (enrdf_load_stackoverflow) 1969-05-19
ES360641A1 (es) 1970-07-16
FR1591489A (enrdf_load_stackoverflow) 1970-04-27
SE341222B (enrdf_load_stackoverflow) 1971-12-20

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Legal Events

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