AR213825A1 - Disposicion de circuito procesadora de datos - Google Patents

Disposicion de circuito procesadora de datos

Info

Publication number
AR213825A1
AR213825A1 AR258770A AR25877076A AR213825A1 AR 213825 A1 AR213825 A1 AR 213825A1 AR 258770 A AR258770 A AR 258770A AR 25877076 A AR25877076 A AR 25877076A AR 213825 A1 AR213825 A1 AR 213825A1
Authority
AR
Argentina
Prior art keywords
data processor
processor circuit
circuit layout
layout
data
Prior art date
Application number
AR258770A
Other languages
English (en)
Spanish (es)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of AR213825A1 publication Critical patent/AR213825A1/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AR258770A 1972-12-26 1976-05-13 Disposicion de circuito procesadora de datos AR213825A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00318344A US3806891A (en) 1972-12-26 1972-12-26 Logic circuit for scan-in/scan-out

Publications (1)

Publication Number Publication Date
AR213825A1 true AR213825A1 (es) 1979-03-30

Family

ID=23237781

Family Applications (1)

Application Number Title Priority Date Filing Date
AR258770A AR213825A1 (es) 1972-12-26 1976-05-13 Disposicion de circuito procesadora de datos

Country Status (11)

Country Link
US (1) US3806891A (ru)
JP (2) JPS5230337B2 (ru)
AR (1) AR213825A1 (ru)
BR (1) BR7308091D0 (ru)
CA (1) CA1001237A (ru)
CH (1) CH556544A (ru)
DE (1) DE2360762C3 (ru)
FR (1) FR2211819B2 (ru)
GB (1) GB1452077A (ru)
IT (1) IT1045395B (ru)
NL (1) NL7316988A (ru)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051353A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Accordion shift register and its application in the implementation of level sensitive logic system
JPS5373043A (en) * 1976-12-13 1978-06-29 Fujitsu Ltd Logical circuit device
GB2030807B (en) * 1978-10-02 1982-11-10 Ibm Latch circuit
JPS55132277A (en) * 1979-04-02 1980-10-14 Canon Inc Liquid-drip jet recording device
JPS55132278A (en) * 1979-04-02 1980-10-14 Canon Inc Liquid-drip jet recording device
US4293919A (en) * 1979-08-13 1981-10-06 International Business Machines Corporation Level sensitive scan design (LSSD) system
US4358826A (en) * 1980-06-30 1982-11-09 International Business Machines Corporation Apparatus for enabling byte or word addressing of storage organized on a word basis
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
JPS58121458A (ja) * 1981-12-09 1983-07-19 Fujitsu Ltd スキヤンアウト方式
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4513283A (en) * 1982-11-30 1985-04-23 International Business Machines Corporation Latch circuits with differential cascode current switch logic
US4692633A (en) * 1984-07-02 1987-09-08 International Business Machines Corporation Edge sensitive single clock latch apparatus with a skew compensated scan function
JPH0535498Y2 (ru) * 1986-02-05 1993-09-08
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
EP0264334B1 (en) * 1986-10-16 1994-12-28 Fairchild Semiconductor Corporation Synchronous array logic circuit
JPH0682146B2 (ja) * 1986-12-22 1994-10-19 日本電気株式会社 スキヤンパス方式の論理集積回路
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
US5157627A (en) * 1990-07-17 1992-10-20 Crosscheck Technology, Inc. Method and apparatus for setting desired signal level on storage element
US5202624A (en) * 1990-08-31 1993-04-13 Cross-Check Technology, Inc. Interface between ic operational circuitry for coupling test signal from internal test matrix
US5179534A (en) * 1990-10-23 1993-01-12 Crosscheck Technology, Inc. Method and apparatus for setting desired logic state at internal point of a select storage element
US5206862A (en) * 1991-03-08 1993-04-27 Crosscheck Technology, Inc. Method and apparatus for locally deriving test signals from previous response signals
US5230001A (en) * 1991-03-08 1993-07-20 Crosscheck Technology, Inc. Method for testing a sequential circuit by splicing test vectors into sequential test pattern
US5389556A (en) * 1992-07-02 1995-02-14 Lsi Logic Corporation Individually powering-up unsingulated dies on a wafer
US5648661A (en) * 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5442282A (en) * 1992-07-02 1995-08-15 Lsi Logic Corporation Testing and exercising individual, unsingulated dies on a wafer
US5495486A (en) * 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer
TW307927B (ru) * 1994-08-29 1997-06-11 Matsushita Electric Ind Co Ltd
US5729553A (en) * 1994-08-29 1998-03-17 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit with a testable block
US5821773A (en) * 1995-09-06 1998-10-13 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US5869979A (en) 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US6314550B1 (en) 1997-06-10 2001-11-06 Altera Corporation Cascaded programming with multiple-purpose pins
US6691267B1 (en) 1997-06-10 2004-02-10 Altera Corporation Technique to test an integrated circuit using fewer pins
US6184707B1 (en) 1998-10-07 2001-02-06 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
JP2000162277A (ja) * 1998-11-25 2000-06-16 Mitsubishi Electric Corp 半導体集積回路
JP2000214220A (ja) * 1999-01-19 2000-08-04 Texas Instr Inc <Ti> オンチップモジュ―ルおよびオンチップモジュ―ル間の相互接続をテストするシステムおよび方法
US7805648B2 (en) * 2008-04-07 2010-09-28 Open-Silicon Inc. Shift-frequency scaling
JP6667257B2 (ja) 2015-10-28 2020-03-18 アンデン株式会社 電磁継電器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3582902A (en) * 1968-12-30 1971-06-01 Honeywell Inc Data processing system having auxiliary register storage
US3651472A (en) * 1970-03-04 1972-03-21 Honeywell Inc Multistate flip-flop element including a local memory for use in constructing a data processing system
US3631402A (en) * 1970-03-19 1971-12-28 Ncr Co Input and output circuitry

Also Published As

Publication number Publication date
NL7316988A (ru) 1974-06-28
DE2360762B2 (de) 1981-01-22
GB1452077A (en) 1976-10-06
BR7308091D0 (pt) 1974-08-15
FR2211819B2 (ru) 1976-06-25
FR2211819A2 (ru) 1974-07-19
CH556544A (de) 1974-11-29
US3806891A (en) 1974-04-23
DE2360762C3 (de) 1981-11-05
JPS5439537A (en) 1979-03-27
JPS4991559A (ru) 1974-09-02
CA1001237A (en) 1976-12-07
IT1045395B (it) 1980-05-10
JPS564942B2 (ru) 1981-02-02
DE2360762A1 (de) 1974-07-11
JPS5230337B2 (ru) 1977-08-08

Similar Documents

Publication Publication Date Title
AR213825A1 (es) Disposicion de circuito procesadora de datos
SE392524B (sv) Elektronisk termometer
DK143875C (da) Databehandlingsanlaeg
AT333530B (de) Elektronischer taxameter
FR2295490A1 (fr) Processeur de donnees
FR2334151A1 (fr) Processeur de donnees
BR7208403D0 (pt) Circuito processador desinais
SE395805B (sv) Nivaskiftningskrets
IT1001316B (it) Circuito multivibratore
AT334661B (de) Elektronischer rechner
IT978033B (it) Circuito integrato
SE383462B (sv) Bigfet-krets
AT334114B (de) Datenverarbeitungsgerat
BR7303339D0 (pt) Circuito de interface acoplado otocamente
BR7305734D0 (pt) Aparelho de interrupcao de circuito
IT993311B (it) Circuito di memoria per elaboratori elettronici
AT324481B (de) Schaltungsanordnung
NL154847B (nl) Gegevensdetectiecircuit.
BR7308817D0 (pt) Circuito amplificador
IT987339B (it) Circuito monitore
SU480206A1 (ru) Радиоэлектронный блок
AR194148A1 (es) Disposicion de circuito impreso flexible
AR206998A1 (es) Disposicion de circuito procesadora de datos
AT345899B (de) Integrierschaltung
SE382540B (sv) Kretsanordning.