AR025674A1 - Metodo de implantacion de turbo codificador en paralelo y un producto de programa de computacion - Google Patents

Metodo de implantacion de turbo codificador en paralelo y un producto de programa de computacion

Info

Publication number
AR025674A1
AR025674A1 ARP000104837A ARP000104837A AR025674A1 AR 025674 A1 AR025674 A1 AR 025674A1 AR P000104837 A ARP000104837 A AR P000104837A AR P000104837 A ARP000104837 A AR P000104837A AR 025674 A1 AR025674 A1 AR 025674A1
Authority
AR
Argentina
Prior art keywords
parallel
encoder
turbo
samples
turbo block
Prior art date
Application number
ARP000104837A
Other languages
English (en)
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of AR025674A1 publication Critical patent/AR025674A1/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Método de implementacion de turbo codificador en paralelo y un producto de programa de computacion para poder lograr un bloque turbo codificador que poseauna velocidad de procesamiento incrementada, se propone llevar a cabo una paralelizacion degrad o n. Como resultado cada bloque turbo codificador en paralelo,consta de una unidad de almacenaje (I0,..., I7), para almacenar n muestras (I(t-1),..., I(t-n)), de una senal de entrada I(t) al bloque turbo codificador enparalelo, y por lo menosuna uni dad de almacenaje (Q0,..., Q7) para almacenar n muestras, (Qj(t),..., Qj(t(n-1))) de al menos una senal de salida Qj(t)(j=1,..., M) del bloque turbo codificador en paralelo. Más aun, el bloque turbo codificador en paralelo consta de un bancode n uni dades de retardo (x,... XN),y se adapta al procedimiento en paralelo de n muestras de la senal de entrada I(t), de modo tal, de que por lo menos dos unidades de retardo (x,..., XN) delbanco, reciban en forma directa sub conjuntos de nmuestras (I(t-1 ),..., I(t-n)), de la senal de entrada I(t), y una senal de salida de por lo menos una unidadde retardo (x,..., XN) en el bloque turbo codificador en paralelo, se suministra a por lo menos dos unidades de retardo en el medio delcodificador.
ARP000104837A 1999-09-15 2000-09-14 Metodo de implantacion de turbo codificador en paralelo y un producto de programa de computacion AR025674A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP99117945A EP1085660A1 (en) 1999-09-15 1999-09-15 Parallel turbo coder implementation

Publications (1)

Publication Number Publication Date
AR025674A1 true AR025674A1 (es) 2002-12-11

Family

ID=8238967

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP000104837A AR025674A1 (es) 1999-09-15 2000-09-14 Metodo de implantacion de turbo codificador en paralelo y un producto de programa de computacion

Country Status (11)

Country Link
US (1) US6651209B1 (es)
EP (2) EP1085660A1 (es)
JP (1) JP4713039B2 (es)
KR (1) KR20020035595A (es)
CN (1) CN1196268C (es)
AR (1) AR025674A1 (es)
AT (1) ATE263454T1 (es)
AU (1) AU6842800A (es)
DE (1) DE60009531T2 (es)
TW (1) TW474068B (es)
WO (1) WO2001020787A1 (es)

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US7315579B2 (en) * 2001-02-28 2008-01-01 Broadcom Corporation Trellis coded modulation tails
US6980820B2 (en) 2001-08-20 2005-12-27 Qualcomm Inc. Method and system for signaling in broadcast communication system
US6731936B2 (en) 2001-08-20 2004-05-04 Qualcomm Incorporated Method and system for a handoff in a broadcast communication system
US6701482B2 (en) * 2001-09-20 2004-03-02 Qualcomm Incorporated Method and apparatus for coding bits of data in parallel
US6948109B2 (en) * 2001-10-24 2005-09-20 Vitesse Semiconductor Corporation Low-density parity check forward error correction
US6954885B2 (en) * 2001-12-14 2005-10-11 Qualcomm Incorporated Method and apparatus for coding bits of data in parallel
FR2853164A1 (fr) * 2003-03-31 2004-10-01 France Telecom Procede de codage correcteur d'erreur utilisant au moins deux fois un meme code elementaire, procede de codage, dispositifs de codage et de decodage correspondants
US7912485B2 (en) 2003-09-11 2011-03-22 Qualcomm Incorporated Method and system for signaling in broadcast communication system
US8570880B2 (en) 2004-08-05 2013-10-29 Qualcomm Incorporated Method and apparatus for receiving broadcast in a wireless multiple-access communications system
EP1880473A2 (en) * 2005-01-14 2008-01-23 Nxp B.V. Channel encoding with two tables containing two sub-systems of a z system
US8620900B2 (en) * 2009-02-09 2013-12-31 The Hong Kong Polytechnic University Method for using dual indices to support query expansion, relevance/non-relevance models, blind/relevance feedback and an intelligent search interface
US8583993B2 (en) * 2011-06-17 2013-11-12 Lsi Corporation Turbo parallel concatenated convolutional code implementation on multiple-issue processor cores
KR101286019B1 (ko) * 2012-01-20 2013-07-19 주식회사 이노와이어리스 터보 인코더 장치
EP2693673A1 (en) * 2012-08-01 2014-02-05 Alcatel Lucent Bit-interleaver for an optical line terminal
US9281846B2 (en) 2013-07-31 2016-03-08 Globalfoundries Inc Turbo encoding on a parallel processor
EP2899991A1 (en) * 2014-01-24 2015-07-29 Alcatel Lucent Space time switch and bit interleaver

Family Cites Families (10)

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Publication number Priority date Publication date Assignee Title
JPS61214623A (ja) * 1985-03-20 1986-09-24 Fujitsu Ltd 畳み込み符号化回路
JPH07253895A (ja) * 1994-03-14 1995-10-03 Sony Corp 複数ビット同時演算による高速除算器
FI100565B (fi) * 1996-01-12 1997-12-31 Nokia Mobile Phones Ltd Tiedonsiirtomenetelmä ja laitteisto signaalin koodaamiseksi
US6023783A (en) * 1996-05-15 2000-02-08 California Institute Of Technology Hybrid concatenated codes and iterative decoding
KR19990012821A (ko) * 1997-07-31 1999-02-25 홍성용 전자기파 흡수체 조성물과 이의 제조 방법, 전자기파 흡수용도료 조성물과 이의 제조 방법 및 이의 도포 방법
BR9906479B1 (pt) * 1998-06-05 2013-01-22 dispositivo de codificaÇço de canal, e, processo de codificaÇço de canal.
AU731794B2 (en) * 1998-08-20 2001-04-05 Samsung Electronics Co., Ltd. Device and method for inserting previously known bits in input stage of channel encoder
JP2000114986A (ja) * 1998-10-08 2000-04-21 Oki Electric Ind Co Ltd 符号化方法及び装置
US6366624B1 (en) * 1998-11-30 2002-04-02 Ericsson Inc. Systems and methods for receiving a modulated signal containing encoded and unencoded bits using multi-pass demodulation
US6304991B1 (en) * 1998-12-04 2001-10-16 Qualcomm Incorporated Turbo code interleaver using linear congruential sequence

Also Published As

Publication number Publication date
KR20020035595A (ko) 2002-05-11
CN1196268C (zh) 2005-04-06
ATE263454T1 (de) 2004-04-15
EP1221200B1 (en) 2004-03-31
JP2003509943A (ja) 2003-03-11
AU6842800A (en) 2001-04-17
TW474068B (en) 2002-01-21
DE60009531D1 (de) 2004-05-06
WO2001020787A1 (en) 2001-03-22
CN1390391A (zh) 2003-01-08
EP1221200A1 (en) 2002-07-10
DE60009531T2 (de) 2005-03-03
JP4713039B2 (ja) 2011-06-29
EP1085660A1 (en) 2001-03-21
US6651209B1 (en) 2003-11-18

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