TW474068B - Parallel turbo coder implementation - Google Patents
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- H—ELECTRICITY
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
- H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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Abstract
Description
474068474068
、發明說明( 發明領域 本發明係關於加速編碼器實施,以及特別是本發明係關 於加速編碼器實施之平行化。 發明背景 電信通訊系統之發射機基頻部分經常連同包含將傳輸位 元之般編碼咨與其他邵分。該編碼器增加合成資訊至具 有位元大小K之進入資料流。因此,位元數藉由因素1/r 增加’與編碼器速率r有關。目前,1/2及1/3之編碼器速 率爲共同使用,雖然其他速率亦爲可能。結果,對各塊κ 個未編碼位元而言,-該編碼器輸出一塊K/r個編碼位元。 在電信通訊系統之資料流接收側上,該原始資料流由接 收器之編碼資料塊重新計算,縱使某些位元在例如空氣介 面上傳輸期間變成訛誤。 最近,加速編碼器爲了電信通訊資料傳輸之錯誤控制目 的而已經採用。通常,加速編碼涉及到應用至少二組件碼 至傳輸之前之相同資訊順序不同插入版本。如相關技藝已 熟知加速編碼,例如1993年5月IEEE國際通訊會議,第 1064-1070 頁 Berrou 等人之’’Near Shannon Limit Error -DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the implementation of accelerated encoders, and in particular the present invention relates to the parallelization of the implementation of accelerated encoders. BACKGROUND OF THE INVENTION The baseband portion of a transmitter of a telecommunication communication system is often Encoding and other points. The encoder adds synthetic information to the incoming data stream with a bit size K. Therefore, the number of bits is increased by a factor of 1 / r 'and is related to the encoder rate r. Currently, 1/2 and 1/3 of the encoder rate is common, although other rates are also possible. As a result, for each block of κ uncoded bits, the encoder outputs a block of K / r coded bits. In telecommunications systems On the data stream receiving side, the original data stream is recalculated by the receiver's coded data blocks, even if some bits become corrupted during transmission over, for example, the air interface. Recently, the encoder has been accelerated for the purpose of error control of telecommunications data transmission It has already been adopted. Generally, accelerated coding involves applying at least two component codes to different inserted versions of the same information sequence before transmission. Known to accelerate encoding, for example, in May 1993 IEEE International Conference on Communications, pp. 1064-1070 Berrou and others of '' Near Shannon Limit Error -
Correcting Coder and Decoder : Turbo-Codes丨’以及_ 1997 年 12 月 IEEE 通訊雜誌第 94-102 頁 Sklar 之”A Primer on Turbo Code Concepts'丨,此處將不提供更進一步細節以及陳 述之參考資料在此處以提及的方式併八本文中。 加速編碼器之一例子在圖8中顯示。如圖8所示,該加 速编碼器包括結構相等之二加·速編碼器方塊TCB 1、TCB2 -4- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝 # 經濟部智慧財產局員工消費合作社印製 474068Correcting Coder and Decoder: Turbo-Codes 丨 'and _ December 1997, IEEE Communications Magazine, pages 94-102 of Sklar "A Primer on Turbo Code Concepts' 丨", further details and statements are not provided here. This article is mentioned here in the manner described in this article. An example of an accelerated encoder is shown in Fig. 8. As shown in Fig. 8, the accelerated encoder includes two equal-speed acceleration / speed encoder blocks TCB 1, TCB2- 4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) 装 # Printed by the Ministry of Economic Affairs Intellectual Property Bureau Employee Consumption Cooperative
五、發明說明(2 ) 經濟部智慧財產局員工消費合作社印製 。二加速編碼器方擒之;PI A 、 万现之不问馬其中之一方塊以未改變次序 接收輸入塊位元,炊而另_ ' Χάί … —万塊以插入次序接收輸入位元 。對各輸入位元而言,例钆,1认山,、 J如 3輛出位元分別在輸出0、1 以及2上產生。 於如圖8所示,該加速編碼器方% Τ(:βι包括在其輸入之 第XOR閘1〇〇以及在其輸出之第二x〇r問1〇2。之間 具有配置3個延遲單^ 1G4 i⑽以供個別輸人位元之延 $。類似地是,該加速編碼器方塊丁CB2包括在其輸入之 第一 XOR閘1 1〇以及在其輸出之第四x〇R閘1 12。之間 具有提供延遲個別續入位元之3個延遲單元114至118。 亦如圖8所示,該加速編碼器輸入信號直接供應至加速 編碼器方塊1而經由插入器12〇供應至第二加速編碼器方 塊TCB2。對輸出0而言,該輸入信號亦直接轉送而不用任 何修正。 操作性地,圖8顯示之該加速編碼器參數爲各加速編碼 為方塊延遲單元數以及此外輸入信號供應至不同XOR閘 100、102、110 以及 112。 圖8顯示之該加速編碼器直接實施依賴延遲單元以及輸 入及輸出暫存器(未在圖8顯示)之使用,如此加迷編碼以 按位元方式完成。此處,所有延遲單元以相同系統時鐘工 作’所以延遲單元輸出因此代表先前時鐘循環之輸入。 雖然以串列方式使用延遲單元之加速編碼器之直接實施 不需要許多暫存器及XOR閘,但是主要缺點爲加速編碼以 串列方式執行。此意義爲每系統時鐘循環只編碼一位元。 -5- 本紙張尺度適用中國^^準(cns)a4規格(210 x 297公 (請先閱讀背面之注意事項和填寫本頁) 1· :裝 474068V. Description of Invention (2) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The second acceleration encoder is Fang Jizhi; PI A, Wan Xianzhi regardless of which one of the blocks receives the input block bits in an unaltered order, and the other _ 'Χάί ... — 10,000 blocks receive the input bits in the insertion order. For each input bit, for example, 认 1, 认, and J, such as 3 output bits are generated on outputs 0, 1, and 2, respectively. As shown in FIG. 8, the acceleration encoder side% T (: βι includes the XOR gate 100 at its input and the second x〇r 102 at its output. There are 3 delays configured between them. Single ^ 1G4 i⑽ for the extension of individual input bits. Similarly, the acceleration encoder block CB2 includes the first XOR gate 1 1 0 at its input and the fourth x 〇R gate 1 at its output. 12. There are three delay units 114 to 118 providing individual continuation bits between the delays. As also shown in FIG. 8, the input signal of the acceleration encoder is directly supplied to the acceleration encoder block 1 and is supplied to The second acceleration encoder block TCB2. For output 0, the input signal is also directly transmitted without any modification. Operationally, the acceleration encoder parameters shown in FIG. 8 are each acceleration encoding as the number of block delay units and other inputs. The signals are supplied to different XOR gates 100, 102, 110, and 112. The acceleration encoder shown in Figure 8 directly implements the use of the delay unit and the input and output registers (not shown in Figure 8). Bit-wise completion. Here, all The delay unit works with the same system clock 'so the output of the delay unit therefore represents the input of the previous clock cycle. Although the direct implementation of the acceleration encoder using the delay unit in series does not require many registers and XOR gates, the main disadvantage is acceleration The encoding is performed in tandem. This means that only one bit is encoded per system clock cycle. -5- This paper size applies to China ^^ standard (cns) a4 specifications (210 x 297 male (please read the precautions on the back and the (Fill in this page) 1 ·: Packing 474068
”亥系統時鐘頻率 結論是’對需要高位元速率之案例而言 將增加爲非常高値。 列如1200通道將 且右、— 〜” 1笔秒時間週期 具有1〇〇位兀之語音通道相關時,需要 1 ’于、統時鐘频傘爲 120 Mhz。 丁理 X、午馬 此處,將非常難以實施相關加速編碼器, 或是F P G A技術。 例如使用 ASIC- 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 、雖然—解答將爲實施各通道之專屬加速編碼器,但是此 方式將需要輸入及輸出位元流之複雜處理,因爲不同通道 仍然必須平行編碼。此情形將引導非常複雜控制邏輯 正確時間供應正確輸入至正確加速編碼器。 u ,不同加 逮編碼器之輸出亦將必須以相同複雜方式加以處理。 發明總結 有4a杰上文,本發明之目的爲增加該加速編碼器方塊處 理速度。 - 匕 如本發明,此目的爲經由加速編碼器平行實現而達成。 迄今爲止,加速編碼器方塊結構起初爲使用之後形成該 加速編碼器方塊平行化基準之一般形式化説明加以説明。Λ 特別是,該加速編碼器方塊輸入樣本解譯爲η維平行輸 入向量元素,其中η爲平行化度數。 該加速編碼器方塊之一般形式化說明之後用以導出此平 行輸入向量至至少一輸出向量之映射。 更詳細地是,内部狀態變數替代處理應用至該一般形式 化説明之各内邵狀態變數,其中該内部狀態變數之表示爲 474068"The conclusion of the clock frequency of the Hai system is that it will increase to a very high level for cases that require a high bit rate. Examples such as 1200 channels will be right, — ~" 1 second time period with a 100-bit voice channel correlation It requires 1 'clock frequency to be 120 Mhz. Ding X, Wu Ma Here, it will be very difficult to implement related acceleration encoders or F P G A technology. For example, using ASIC-Printed by the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives, although—the answer will be to implement a dedicated acceleration encoder for each channel, but this method will require complex processing of the input and output bit streams, as different channels must still be parallel coding. This situation will lead to very complex control logic supplying the correct input to the correct acceleration encoder at the right time. u, the output of different capture encoders will also have to be processed in the same complex way. Summary of the Invention As mentioned above, the purpose of the present invention is to increase the processing speed of the accelerated encoder block. -Dagger According to the present invention, this object is achieved in parallel via an accelerated encoder. So far, the accelerated encoder block structure was initially described as a generalized formal description of the accelerated encoder block parallelization benchmark after use. Λ In particular, the accelerated encoder block input samples are interpreted as n-dimensional parallel input vector elements, where η is the degree of parallelization. The generalized description of the accelerated encoder block is then used to derive the mapping of this parallel input vector to at least one output vector. In more detail, the internal state variable substitution process is applied to each internal state variable of the general formal description, where the internal state variable is represented as 474068
五、發明說明(4 ) 經濟部智慧財產局員工消費合作社印製 二::素掃描’該元素之後經由利用該内部狀態 〗決疋〈時間索引替代表示而實行後向時間索引轉 換加以替代。這些替代步驟爲重複直到各内部狀態變數之 表不只與依據平行化度數延遲之加速編碼器輸入向量元素 以及内邵狀態變數値相關爲止。 、此外3替代處理同樣爲各平行輸出向量之各元素加以 實行。再次,各輸出向量之各向量元素表示爲具有最大時 間索引(内邵狀態變數掃描以及之後該向量元素表示之後 向時間索引轉換爲遞迴地決定直到該向量元素表示只與依 據平行化度數延遲冬内部狀態變數値相關爲止。 所以,如本發明建議平行化該加速編碼器方塊,所以只 有一平行化加速編碼器方塊爲需要而取代多數串列加速編 碼器以達成增加之處理速度。此情形引導複數個加速編碼 器方塊不需要複雜輸入及輸出控制之決定性優點。 例如,、對⑸位元平行加速編碼器方塊而言,”上文提到例 子之形成之系統時間頻率位於3〇 MHz之範圍,所以可以 容易地使用FPGA或是ASIC技術加以實現。所以,該平行 化加速編碼器方塊以及由此導出之加速編碼器依據平行化 度數達成串列加速編碼器之上之增加速度,所以預先定義 之規範使用FPGA或是ASIC技術基準實施可以符/合。因: ,該平行化加速編碼器方塊可以形成在基頻部分具有低處 理延遲之複雜通訊系統之基準而沒有同時不同通道之複^ 處理。 夂亦 此外,當與串列加速編碼器比較時,該平行化加速編碼 ----I----丨丨丨裝·-------訂--I------*^ιρ· (請先閱讀背面之注意事項再填寫本頁) 7- 474068 第89117076號專利申請案 中文說明書修正頁(90年9月) A7 B7V. Description of the invention (4) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 :: The element is scanned and the element is replaced by the backward time index by using the internal state. These alternative steps are repeated until the table of each internal state variable is not only related to the acceleration encoder input vector elements and the internal state variable 値 which are delayed according to the degree of parallelization. In addition, 3 replacement processing is also performed for each element of each parallel output vector. Again, each vector element of each output vector is represented as having the largest time index (the scan of the internal Shao state variable and then the vector element representation is then converted to the time index to be determined recursively until the vector element representation is only delayed by the degree of parallelization according to the degree of parallelization The internal state variables are not related. Therefore, as the present invention proposes to parallelize the acceleration encoder block, only one parallel acceleration encoder block is needed instead of most serial acceleration encoders to achieve increased processing speed. This situation guides The decisive advantage of the complex acceleration encoder blocks that do not require complex input and output control. For example, for a unit-bit parallel acceleration encoder block, "the system time frequency formed by the example mentioned above is in the range of 30 MHz Therefore, it can be easily implemented using FPGA or ASIC technology. Therefore, the parallel acceleration encoder block and the derived acceleration encoder achieve the increase speed over the serial acceleration encoder according to the degree of parallelization, so it is defined in advance The specifications can be implemented using FPGA or ASIC technology benchmarks. Because: The parallel acceleration encoder block can form the basis of a complex communication system with a low processing delay in the fundamental frequency section without the complex processing of different channels at the same time. 夂 Also, when accelerating encoding with serial When comparing the encoders, the parallel acceleration encoding ---- I ---- 丨 丨 丨 installed ------- order --I ------ * ^ ιρ · (Please read the Note: Please fill in this page again) 7- 474068 No. 89117076 Patent Application Chinese Specification Revision Page (September 1990) A7 B7
五 、發明説明(5 ) 器方塊以及相關加速編碼器只需要邏輯閘以及暫存器之最 小額外過剩物。 此外,當加速編碼器前後之處理方塊亦支援平行處理方 式時,完整編碼器方塊與具有串列加速編碼器以及一些額 外轉換器之編碼器方塊比較整體需要較少邏輯(平行至串 列,反之亦然)。 裝Fifth, the invention description (5) The encoder block and the related acceleration encoder only need the minimum additional surplus of the logic gate and the register. In addition, when the processing blocks before and after the accelerated encoder also support parallel processing, the complete encoder block requires less logic overall (parallel to serial, and vice versa) than an encoder block with a serial accelerated encoder and some additional converters. And so on). Hold
如本發明另一具體實施例,亦提供一電腦可讀取儲存媒 體,包括軟體碼部分以供當在電腦上執行時,執行如發明 性平行化方法之步驟。較佳地是,該軟體碼部分為VHDL 類型。 所以,本發明允許以設計至不同硬體技術如ASIC或是 FPOA之映射相關之減少發展循環數及增加之彈性分別達 成平行加速編碼器設計快速發展及修正之基準。 圖式之簡單說明 在下文中,本發明較佳具體實施例將參考附圖而加以說 明,其中:According to another specific embodiment of the present invention, a computer-readable storage medium is also provided, including software code portions for performing the steps of the inventive parallelization method when executed on a computer. Preferably, the software code portion is a VHDL type. Therefore, the present invention allows to reduce the number of development cycles and increase the flexibility by mapping to different hardware technologies such as ASIC or FPOA to reach the benchmark for rapid development and modification of parallel accelerated encoder design, respectively. Brief description of the drawings In the following, preferred embodiments of the present invention will be described with reference to the drawings, in which:
線 圖1顯示具有一個輸出之加速編碼器方塊電路圖; 圖2顯示具有複數個輸出之加速編碼器方塊電路圖; 圖3顯示資料輸入時間順序流至平行輸入向量之映射以 及平行輸出向量至資料輸出時間順序流之映射; 圖4顯7JT特定加速編碼益方塊串列貫施之電路圖, 圖5顯示圖4顯示之加速編碼器方塊二位元平行實施之 電路圖; 圖6顯示圖4顯示之加速編碼器方塊四位元平行實施之 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 474068 A7 B7 五、發明說明(6 電路圖; -----------裳·丨1 (請先閱讀背面之注意事項再填寫本頁} 圖7A顯示圖4顯示之加速編碼器方塊八位元平行實施 之輸入部分之電路圖; 只她 圖7B顯示圖4顯示之加速編碼器方塊平行實施之輸 分之電路圖;以及 圖8顯示包括插入器以及加速編碼方塊1及 之加速編碼器概要圖。 圖式之詳細說明 在下、中本舍明較佳具體貫施例將參考圖1至圖7加 以説明。 " 特別是,起初如圖1及圖2所示之加速編碼器方塊正式 説明將既定爲如本發明之平行化方法之説明基準。 》 之後,將參考圖3説明資料輸入之時間順序流如何可以 映射至平行輸入向量以在平行化加速編碼器方塊中處理以 及此平行化加速編碼器方塊平行輸出向量如何可以再次映 射至資料輸出之時間順序流。 此處利用如本發明之平行化方法之加速編碼器方塊平行 貫施之後續不同例子將參考圖4至圖7既定。 經濟部智慧財產局員工消費合作社印製 1 · 具有串列實施、一般説明之加速編碼器方樓: 圖1顯示使用串列實施之加速編碼器方塊電路圖。 如圖1所示,該加速編碼器方塊包括Ν個延遲單元,X1 Χ2,···,ΧΝ,例如正反器。延遲單元X丨,χ2, ··· ^輸出信號 將分別視爲Xl⑴,Χ2⑴,…,Χν⑴,其中t表示整數時間索 引。在第一延遲單元Χι輸入上提供輸入x〇R閘12以及在 -9 - 本紙張尺度適用巾關家標準(CNS)A4規格(210 X 297公爱) 474068 A7 五、發明說明(7 ) 最後延遲單元X—出上提供輸出x〇r間… 亦如圖1所示,經由輸入延遲單元16供應之輸入信號I(tFigure 1 shows a block circuit diagram of an accelerated encoder with one output; Figure 2 shows a block circuit diagram of an accelerated encoder with multiple outputs; Figure 3 shows the mapping of data input time sequence to parallel input vectors and parallel output vector to data output time Sequence flow mapping; Figure 4 shows the circuit diagram of 7JT specific accelerated coding block implementation in series, Figure 5 shows the circuit diagram of the two-bit parallel implementation of the accelerated encoder block shown in Figure 4; Figure 6 shows the accelerated encoder shown in Figure 4 Square four-bit implementation in parallel -8- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 474068 A7 B7 V. Description of the invention (6 Circuit diagram; ----------- Shang · 丨 1 (Please read the precautions on the back before filling this page} Figure 7A shows the circuit diagram of the input part of the 8-bit parallel implementation of the accelerated encoder block shown in Figure 4; only Figure 7B shows the accelerated encoder shown in Figure 4 A block diagram of the input and output circuits implemented in parallel with the blocks; and Fig. 8 shows a schematic diagram of the accelerated encoder including the inserter and the accelerated coding block 1 and the block diagram. The preferred embodiments will be described with reference to Figs. 1 to 7. In particular, the formal description of the acceleration encoder block shown initially in Figs. 1 and 2 will be formalized as a description of the parallelization method of the present invention. After the benchmark, we will explain how the time-sequence stream of data input can be mapped to the parallel input vector for processing in the parallel acceleration encoder block with reference to FIG. 3 and how the parallel output vector of this parallel acceleration encoder block can be mapped to the data again. The output is a time-sequential stream. The following different examples of parallel implementation of the accelerated encoder block using the parallelization method of the present invention will be given with reference to Figures 4 to 7. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 1 · Has Accelerated encoder square building implemented in series and general description: Figure 1 shows the block circuit diagram of the accelerated encoder using serial implementation. As shown in Figure 1, the accelerated encoder block includes N delay units, X1 X2, ... , XN, such as flip-flops. The delay units X 丨, χ2, ··· ^ The output signals will be regarded as Xl⑴, χ2⑴, ..., χν⑴, respectively, where t represents Integer time index. Input x〇R gate 12 is provided on the input of the first delay unit X and -9-this paper size is applicable to the family standard (CNS) A4 specification (210 X 297 public love) 474068 A7 V. Description of the invention (7) The last delay unit X—the output is provided between x0r ... As shown in FIG. 1, the input signal I (t
以及輸出XOR閘14輪士狀铖丰认, V _ 輸出仏唬、,Λ由輸出延遲單元1 8轉送< 不如圖1所示,輸出信號⑴ 、击技抑 2⑴,···,〜⑴可以經由 、接㈣,a2, ·..,〜供應至輸入⑽閘12。亦 元輸入信號可以經由連接器ρ〇,, 遲早 職閘Μ。此外,延遲單元出經由至輸出 輸出XOR閘14。 °。h供應至 藉由正式指定値〇或是丨至各連接器αι, 此外扣足至各連接Ρ β〇,β!,…,βΝ,可能如下式—日Ν X及 個延遲單元之任何串列加速編碼器方塊實施:月具有hAnd the output XOR gate is 14 rounds, and the V_ output is frightened, and Λ is forwarded by the output delay unit 18 < not shown in Figure 1, the output signal ⑴, the hitting suppression 2⑴, ..., ~ ⑴ It can be supplied to the input gate 12 via a connection, a2, · .., ~. The input signal can also be input via the connector ρ〇, sooner or later. In addition, the delay unit outputs to the output XOR gate 14. °. h is supplied to 连接 〇 or 丨 to each connector αι by formal designation, and it is deducted to each connection P β〇, β!, ..., βΝ, which may be as follows—day N X and any series of delay units Speed up encoder block implementation: month has h
Xl (t)=:工(t-1)㊉ arXjL (t-1) © α2·Χ2 (t-l)㊉· ·染 •切 aN,(t、i)、 ai ε {〇, 1} (1·χ1) X2(t) = χχ(t-1) (1·X2) 111!11111 t !1_ (請先閱讀背面之注意事項再填寫本頁} # 經濟部智慧財產局員工消費合作社印製 = XN-l(t-l) (1·XN) 10 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 47406s A7 B7Xl (t) = : 工 (t-1) ㊉ arXjL (t-1) © α2 · χ2 (tl) ㊉ ··· Dye aN, (t, i), ai ε {〇, 1} (1 · χ1) X2 (t) = χχ (t-1) (1 · X2) 111! 11111 t! 1_ (Please read the notes on the back before filling out this page) # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy = XN -l (tl) (1 · XN) 10 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 47406s A7 B7
五、發明說明(8 ) 匕)=0〇.[工(匕-1)㊉arxi(卜工) ㊉ a2.X2 (卜1) ㊉· ··㊉ aN-xN(t:-i)]㊉ βγχ! (t-l)㊉ β2·χ2 (t-1)㊉· · ·㊉ =β〇·工(t-1)㊉ βο.α^α-Ι)㊉ βΐ·χ1(ί:-1)㊉ P〇,xN(t-l)㊉ PM.XNk-1) β〇·工(t-1)㊉ Χ]_(ί:-1)·[β〇·(Χι ㊉ βι]㊉ (t -1) · [Pq’CCn ㊉ Pn] ε {〇, 1} 绥濟部智慧財產局員工消費合作社印製 L---1--------*«r--- (請先閱讀背面之注意事項再填寫本頁) d.Q) 如圖2所示,具有單一輸出之加速編碼器方塊上文既定 之一般説明可以歸納爲使用串列實施以及具有複數輸出之 加速編碼器方塊。 如圖1以及亦如圖2顯示延·遲單元Xi,X2···,χΝ輸出信 -11 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4^4068 A7 經濟部智慧財產局員工消費合作社印製 、發明說明 號將再次視爲Xl⑴,x2 (t),···,xN⑴。各延遲單元Χι,X2,···, XN輸出信號X|(t),&⑴,…,χΝ⑴已經在圖i顯示經由連接 器α!,α2,···,αΝ供應至輸入XOR閘12。亦且,輸入資料流 經由延遲單元16供應至輸入x〇r閘12。 圖2顯示之事列加速編碼器方塊與先前討論之加速編碼 器方塊不同點在於提供複數個輸出Ql (t),...,QM(t)。如圖 2所示,各輸出提供相關輸出x〇R閘14_丨,…,14_M。在各 輸出XOR閘14-1,…,14-M之輸出上,具有連接之相關輸 出延遲單元18-1,...,18-M。 亦如圖2顯示’延遲單元X丨,x2...,ΧΝ之各輸入可以經 由連接器βΜ,β丨,丨,β丨2, ·..,Ρΐ Ν•丨供應至第—輸出閘"· i ;:及更進一步經由連接器β2,“2,Ι,β2,2,…,k等供應 =二出閘14-2等。此外’最後延遲單 供應至第一輸出閘14],經由連接 f至矛-輸出閑14·2等。最後’各輸出XOR間之二出产 號延遲以導A加速編碼时塊輸幻巧h⑴,8 圖2顯示之加速编碼器之正式說明^’ Qm 於各輪Ψ η “、 ^ 、 ”先則4論之不同在 、'卩1 (),…,QM⑴之相關表示歸納爲: (t) = Pjo·工(t-i)㊉ ㊉ pjl;| ㊉ — !11111^^ t — 11111 e 1111! *1^1^. {請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (8) Dagger) = 0. [Gong (Dagger-1) (arxi (Buddy) ㊉ a2.X2 (Bu1) ㊉ ··· ㊉ aN-xN (t: -i)] ㊉ βγχ ! (tl) ㊉ β2 · χ2 (t-1) ㊉ ··· ㊉ = β〇 · 工 (t-1) ㊉ βο.α ^ α-Ι) ㊉ βΐ · χ1 (ί: -1) ㊉ P〇 , XN (tl) ㊉ PM.XNk-1) β〇 · 工 (t-1) ㊉ Χ] _ (ί: -1) · [β〇 · (Χι ㊉ βι) ㊉ (t -1) · [Pq 'CCn ㊉ Pn] ε {〇, 1} Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Suiji L --- 1 -------- * «r --- (Please read the precautions on the back before (Fill in this page) dQ) As shown in Figure 2, the accelerated encoder block with a single output can be summarized as an accelerated encoder block with serial implementation and a complex output. Figure 1 and Figure 2 show the delay and delay units Xi, X2 ..., χΝ output letter-11 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4 ^ 4068 A7 Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative prints and invents the description number again as Xl⑴, x2 (t), ..., xN⑴. Each delay unit X1, X2, ..., XN output signals X | (t), & ⑴, ..., χΝ⑴ have shown in FIG. I that they are supplied to the input XOR gate via the connectors α !, α2, ..., αN 12. Also, the input data stream is supplied to the input x〇r gate 12 via the delay unit 16. The difference between the accelerated encoder block shown in Fig. 2 and the previously discussed accelerated encoder block is that a plurality of outputs Ql (t), ..., QM (t) are provided. As shown in Fig. 2, each output provides related outputs x〇R gates 14_ 丨, ..., 14_M. On the outputs of the respective output XOR gates 14-1, ..., 14-M, there are associated output delay units 18-1, ..., 18-M. It is also shown in Fig. 2 that the inputs of the delay units X 丨, x2 ..., XΝ can be supplied to the first output gate via the connectors βΜ, β 丨, 丨, β 丨 2, · .., PΐN • 丨; · I;: and further supply via connectors β2, "2, I, β2, 2, ..., k, etc. = two exit gates 14-2, etc. In addition 'the last delay order is supplied to the first output gate 14], By connecting f to the spear-output idle 14.2, etc. Finally, 'the output number of each output XOR is delayed to lead A to speed up the encoding of the block when the encoding is delayed, 8 Formal description of the accelerated encoder shown in Figure 2 ^' The differences between Qm in each round Ψ η ", ^,", the first four theories, '卩 1 (), ..., QM⑴'s related expressions are summarized as: (t) = Pjo · 工 (ti) ㊉ ㊉ pjl; | ㊉ —! 11111 ^^ t — 11111 e 1111! * 1 ^ 1 ^. {Please read the notes on the back before filling this page)
474068 A7 B7 五、發明說明(扣 pij ε {〇, 1} j ε [!' · · · , Μ], (l.Q) 串列實施之加速編碼器方塊上述之正式表于 是複數輸出將作用爲如本發明之平行化方法之説明二固或. 然而’在如本發明之平行化方法將在下文説明之:半。 初串列資料輸入流至平行輸入向量之映射以及平行::起 里回至串列資料輸申流之映射將參考圖3加以説明。向 2· 使用度數n平行實施之加速編碼器方塊: 在左上側,圖3顯示如串列資料輸入流之時間順序。麵 似地是,圖3在右上側部分顯示如串列輸出流之時間順= 〇 如圖3所示,平行輸出向量ι〇, η,Ιη-1可以由一串列資 料輸出値I (t-l)5 I (t-2),…,I (t-n)如下式導出: I (t-l)= 10 (p_l) I (t-2)= II (p-1) ··裝--------訂--------- rtt先閱讀背面之注意事項再填寫本頁,> # 經濟部智慧財產局員工消費合作社印製 (t-n) = In-1 (p-1) 假設圖3顯示之由串列資料輸入流導出之平行輸入向量 -13- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068474068 A7 B7 V. Description of the invention (deduction pij ε {〇, 1} j ε [! '· · · · Μ], (lQ) Accelerated encoder block implemented in series The above formal table will then be used as a complex output The description of the parallelization method of the present invention is two-way. However, the parallelization method of the present invention will be described below: half. The mapping of the initial serial data input stream to the parallel input vector and the parallel :: back to back The mapping of the serial data input stream will be explained with reference to Fig. 3. To the acceleration encoder block implemented in parallel using degree n: On the upper left side, Fig. 3 shows the time sequence of the serial data input stream. Figure 3 shows the time sequence of the serial output stream in the upper right part = 〇 As shown in Figure 3, the parallel output vector ι〇, η, Ιη-1 can be output from a series of data 値 I (tl) 5 I ( t-2), ..., I (tn) is derived as follows: I (tl) = 10 (p_l) I (t-2) = II (p-1) ··· equipment -------- order- -------- rtt first read the notes on the back before filling in this page, ># Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (tn) = In-1 (p-1) By string Export of parallel input vector data input stream -13- This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) 474 068
知於下文説明之加速編碼 平行輸出向量⑽…‘卜^處理’其中之一到達 如圖3所示’此平行輸 串列資料輸出流_,...,咖(1^:了〜下式映射回至Known as one of the accelerated encoding parallel output vectors 下文 ... 'Bu ^ processing' one of them arrives as shown in Figure 3 'This parallel input serial data output stream _, ..., coffee (1 ^: 了 ~ the following formula Maps back to
Qj(t) Qj(t-1)Qj (t) Qj (t-1)
Qj°(p)QjUp)Qj ° (p) QjUp)
Qj(t-(n-l)) = Qjn-i(-p) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 2 ·1 平行化之一般描繪 如本發明,纟串列域及平行域中具有使用之不同時間標 产話説’串列時間域之'组η個串列資料輸入相當 ^依據平行時間域Ρ之-時鐘循環平行處理之平行輸入向 "5* 〇 結論是,形成之平行系統時鐘爲慢於串列系統時鐘η倍 ,假設相同量資料將處理。所以,該串列時間式仏1)可以 由平行時間式(ρ-1)取代以及一系列η串列時間輸入重新寫 爲單一平行輸入向量,早於(ρ-1)之一平行時鐘循環。類似 地是,該事列輸出重新寫爲現行平行循環(ρ)之平行輸出 量。 使用如圖1及圖2之加速編.碼器方塊之一般説明以及 _ 丘匕 -14 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -裝---------訂---------. 474068 A7 五、發明說明(12 1 員 費 外:串列資料輸入流至平行輸入向量之映射以及平 向量至串列輸出資料流之反向映射,依據本發明之方 賴具有η個串列資料輸人項目之平行輸人向量之供應= 行化加速編碼器方塊以及各包括“固輸出資料項目^ 輸出向量之計算。 、輸出向量之η個元素與内部延遲單元只在早期之串列加 速編碼器方塊實施之η個系統時鐘與内部延遲單元 Χν <値有關-只相當於平行化加速編碼器方塊之一循環-以 及此外與平行輸入向量综合之這些η個循環期間 入資料項目有關。 掏 如將由下文所示’在本發明之下之方式依賴代表平行輸 出向量之輸出元素以及與平行加速編碼器方塊之内部延遲 单=輸^直以及先前平行循環之平行輸入向量有關之次一 平仃循ί衣·^平行加速編碼器方塊《内部延遲單元輸出値 等式決定。 如該串列表示(參考等式(1.Q)),在時間t之串列實施 加速編碼器方塊各輸出値由時間卜丨之延遲單元χΐ,· 之輸出値以及時間N1之輸入資料項目計算。 藉由以早期串列實施之系統時鐘循環之値取代内部延遲 ,元所有輸出値以及經由遞迴方式重複這些取代步驟直到 有早先η個串列系統時鐘猶環之輸出値留下爲止,可 具有在η個争列循環或是等效於一個平行循環上之輸出 果平行計算之導出等式。 換句居口見’這些等式將平行化加速編碼器方塊之基準 閱 之 之Qj (t- (nl)) = Qjn-i (-p) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 · 1 The general depiction of parallelism is as in the present invention纟 The serial time domain and the parallel time domain have different time scales. It says that the group of n serial data inputs of the 'serial time domain' is equivalent to the parallel input direction according to the parallel time domain P-clock cycle parallel processing. " 5 * 〇 The conclusion is that the parallel system clock formed is η times slower than the serial system clock, assuming that the same amount of data will be processed. Therefore, the serial time formula 仏 1) can be replaced by the parallel time formula (ρ-1) and a series of η series time inputs can be rewritten as a single parallel input vector, which is earlier than one parallel clock cycle of (ρ-1). Similarly, the output of this sequence is rewritten as the parallel output of the current parallel cycle (ρ). Use the accelerated coding as shown in Figure 1 and Figure 2. General description of the encoder block and _ Qiao -14 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)-installed ------ --- Order ---------. 474068 A7 V. Description of the invention (12 1 Staff fee: Mapping of serial data input stream to parallel input vector and reverse of flat vector to serial output data stream Mapping, according to the present invention, depends on the supply of parallel input vectors with η serial data input items = row acceleration encoder blocks and calculations that each include a "solid output data item ^ output vector." Η of the output vector Elements and the internal delay unit are only implemented in the early serial acceleration encoder blocks. The n system clocks are related to the internal delay unit χν < 値-equivalent to only one cycle of the parallel acceleration encoder block-and in addition to parallel input Vector integration is related to the data entry items during these n cycles. As will be shown below, the way under the present invention relies on the output elements representing the parallel output vector and the internal delay sheet with the parallel acceleration encoder block = input It is related to the parallel input vector of the previous parallel loop, and the next one is equal. The parallel acceleration encoder block "internal delay unit output" is determined by the equation. As shown in the series (refer to equation (1.Q)), in The implementation of accelerating encoder blocks at time t is calculated by the delay unit χΐ at the time bu, the output 値, and the input data items at time N1. The internal clock cycle of the system implemented in the earlier series replaces the internal Delay, repeat all output steps, and repeat these replacement steps recursively until there are previous n serial system clock output loops left, which can have n queue cycles or equivalent to a parallel cycle The output results of the parallel calculation of the derived equations. In other words, see 'These equations will parallelize the benchmark of the accelerated encoder block.
Xr 以 結 Μ (_____ · 15 _ 本紙張尺度適財關家標靴NS)A4規格⑽ 474068Xr ends with Μ (_____ · 15 _ this paper size is suitable for financial and family standard boots NS) A4 specifications ⑽ 474068
成爲代表一個平行時鐘循 2·2第-内部狀態之後二n個串列時鐘循環。 (請先閱讀背面之注意事項再填寫本頁) # ^ μ 、_ 曼向時間索引代替: 在準備上又提到之遞迴 押一 、$姦處理時,可以使用第一延遲 早70 Χ丨之輸出表示(比較等式(1.χι)) X1 (匕) =I (t-l) _ ㊉ cti.Xi (匕-ι)㊉Became two n serial clock cycles after representing a parallel clock cycle 2nd-2nd internal state. (Please read the notes on the back before filling in this page) # ^ μ 、 _ Manxiang time index instead: When mentioned in the preparation and returning the charge, the first delay can be used as early as 70 Χ 丨The output representation (comparative equation (1.χι)) X1 (dagger) = I (tl) _ ㊉ cti.Xi (dagger-ι) ㊉
Ct2 *X2 (t - 1)㊉· ·.㊉ aN*xN (t -1) 亦在下文視爲第--内部狀態以如下式表示串列時鐘循環 t-1,···,t-(n-l)之此内部狀雜··Ct2 * X2 (t-1) ㊉ ·· .㊉ aN * xN (t -1) is also regarded as the first--the internal state is represented by the serial clock cycle t-1, ..., t- ( nl) of this internal miscellaneous ...
經濟部智慧財產局員工消費合作社印製 xi(t:-(n-i)) = i(t:-n)㊉ ai.Xi(t_n)㊉ α2·χ2 (匕-n)㊉· ·.㊉ aN*xN (t ~π) (2·父1·η-l) -16- _ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 474068 A7 五、發明說明(14 ) ,3 其他内邵狀態之後向時間索引 #7丨代替(1 = 2 Χτχ 此外,其他延遲單元X, γ 、 ,···,Ν): 2’···’ Χν〈輸出表示(參考等式 (1·χ2),…,(1·χΝ))Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs xi (t :-( ni)) = i (t: -n) ㊉ ai.Xi (t_n) ㊉ α2 · χ2 (dagger-n) ㊉ ·· .㊉ aN * xN (t ~ π) (2 · Father1 · η-l) -16- _ This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) 474068 A7 V. Description of the invention (14), 3 The other internal states are then replaced by time index # 7 丨 (1 = 2 χτχ In addition, other delay units X, γ,, ..., N): 2 '··' 'χν <output representation (refer to equation (1 · Χ2), ..., (1 · χΝ))
Xi⑴Xi⑴
Xi -1 (t-1 ) 亦在下文視爲其他内部狀態可以如 t-υη-υ之這些内部狀態:式表,時鐘循環.Xi -1 (t-1) is also considered hereinafter as other internal states such as t-υη-υ these internal states: formula table, clock cycle.
Xi (t-l) xi-l (t — 2) (2-Xi·1)Xi (t-l) xi-l (t — 2) (2-Xi · 1)
Xj[(t-(n-l)) = xi-i(t-n) (2. 經濟部智慧財產局員工消費合作社印製 2.4 輸出向量元素之後向時間索引代替: 此外,該加速編碼器方塊之至少一輸出表示(比較等式(1.Q)) Qj (t) = β」0·工(t-l)㊉ — … x;L (t-l) · [Pjo.ajL ㊉ pjj ㊉ XN (卜1) · [h 〇·αΝ ㊉ PjN;] (2.Q.0) ^ ^--------^--------- (請先閱讀背面之注意事項再填寫本頁) _ -17- ‘紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 474068 A7 B7 五、發明說明(15) 可以如下式用以表示串列時鐘循環t-Ι,…,t-(n-l)之此輸 出: 請 先 閱 讀 背 面 之 注 意 事Xj [(t- (nl)) = xi-i (tn) (2. The Intellectual Property Bureau of the Ministry of Economic Affairs ’Employee Consumer Cooperatives printed 2.4 output vector elements and replaced them with time indexes: In addition, at least one output of the accelerated encoder block Representation (comparison equation (1.Q)) Qj (t) = β ″ 0 · 工 (tl) ㊉ —… x; L (tl) · [Pjo.ajL ㊉ pjj ㊉ XN (Bu 1) · [h 〇 · ΑΝ ㊉ PjN;] (2.Q.0) ^ ^ -------- ^ --------- (Please read the notes on the back before filling this page) _ -17- 'The paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 474068 A7 B7 V. Description of the invention (15) The following formula can be used to represent the serial clock cycle t-1, ..., t- (nl) This output: Please read the notes on the back first
Qj (t-i) = Pj〇.I (t-2)㊉ ㊉以工]㊉ xN(t-2) · [β」〇.αΝ ㊉ β」Ν] (2.Q.1)Qj (t-i) = Pj〇.I (t-2) ㊉ ㊉ 以 工] ㊉ xN (t-2) · [β ″ 〇.αΝ ㊉ β ″ N] (2.Q.1)
Qj (t-(η-1)) β」〇·工(t-n)㊉Qj (t- (η-1)) β ″ 〇 工 (t-n) ㊉
Xi(t-n).[Pj〇.cti ㊉ β」ι]㊉ 經濟部智慧財產局員工消費合作社印製 XN (t-η) · [β」〇·(% ㊉ pjN] (2.Q.n-l) -18 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(16 ) 2*5經由遞迴後向時間索引轉換步驟之平行化: 2.5.1目的 已經如上文描繪,如本發明之平行化處理之下之目的爲 表示各平行輸出向量之元素-圖2顯示之每輸出丨,…, 個元素-爲一串列n個_列資料輸入流以及一平行循環内部 狀態之函數-等效於η個串列循環-在現行平行循環之前:Xi (tn). [Pj〇.cti ㊉ β ″ ι] ㊉ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy XN (t-η) · [β "〇 · (% ㊉ pjN) (2.Qn-l) -18 The size of this paper applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 Printed by the Consumer Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (16) 2 * 5 The parallelization of the index conversion step: 2.5.1 The purpose has been described as above. The purpose under the parallelization process of the present invention is to represent the elements of each parallel output vector-each output shown in Fig. 2, ..., elements-is A series of n_column data input streams and a function of the internal state of a parallel loop-equivalent to n serial loops-before the current parallel loop:
Qj(t-i) = ..., I(t-n); x^t-n).....XN(t-n)] f〇r i ε [0, ···,n-1] j ε [1,…,M]Qj (ti) = ..., I (tn); x ^ tn) ..... XN (tn)] f〇ri ε [0, ·· ,, n-1] j ε [1, ..., M]
Qji(P) = f[I〇(p-l),…,In-l(p-i); …,ΧΝ(ρ-1)]· (2.Qi) 2.5.2遞迴時間索引轉換步驟 首先’爲達成此目標所有内部狀態均平行化。對所有内 邵狀態Xi (t),…,χΝ⑴而言,起初將在此内部狀態表示中使 用之取大時間索引依據一串列運作説明加以設定成t· 1。 之後所有内部狀態之表示爲考量以及各狀態爲遞迴掃描 以藉由表示使用上文列出之等式(2)之一之此現行最大時 間索引之前之時間索引相關之相同内部狀態之方程式取代 與現行最大時間索引有關之内部狀態變數。 所以,該考量之内部狀態之表示以由現行最大時間索引 至現行最大時間索引之前之時.間索引形成之轉換方式加以 -19 - 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) •I —丨丨—!111 ·—丨丨丨—丨—訂-丨— I- (請先閱讀背面之注意事項再填寫本頁) 474068 A7Qji (P) = f [I〇 (pl), ..., In-1 (pi); ..., XN (ρ-1)] · (2.Qi) 2.5.2 Recursive time index conversion step is first All internal states of this target are parallelized. For all internal states Xi (t),…, χΝ ,, the large time index used in this internal state representation is initially set to t · 1 according to a series of operating instructions. All subsequent internal states are expressed as a consideration and each state is a recursive scan to be replaced by an equation representing the same internal state related to the time index before this current maximum time index using one of the equations (2) listed above Internal state variables related to the current maximum time index. Therefore, the internal state of the consideration is expressed by the conversion method from the current maximum time index to the time before the current maximum time index. -19-This paper standard applies the Chinese National Standard (CNS) A4 specification (21〇x). 297 mm) • I — 丨 丨 —! 111 · — 丨 丨 丨 — 丨 —Order- 丨-I- (Please read the notes on the back before filling this page) 474068 A7
先 閱 讀 背 面 之 注 意 事 項 再I 填 寫 本 頁 裝 4 474068 A7 B7 五、發明說明(18 ) while ( tmax > t-n ) (請先閱讀背面之注意事項再填寫本頁) { scan representation of internal state X]^(t) for internal states with maximum time index tmax; · for ( all internal states with maximum time index ) { execute backward time index transition from tmax to tmax-l through state variable substitution using .eq. (2) above; } cancel double terms in representation of internal state xj^ (t); tmax = tmax-l; } } /* parallelization of output variables */ 經濟部智慧財產局員工消費合作社印製 for ( j=l; j<=M; j++ ) { for ( i = 0; i<=n-2; i + + ) { /* consider output vector element Qj(t-i) */ -21 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 474068 A7 B7 五、發明說明(19 ) tmax = t-i-l; while ( tmax > t-n ){ scan representation of Qj(t-i) for internal states with maximum time index; for ( all internal states with maximum time index ){ execute backward time index transition from tmax to t max' 1 through state variable substitution using eq. (2) above; cancel double terms in representation of Qj (t-i); 一 max -max" (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 } /* end procedure */ 爲解釋上文一般説明之平行化方式之應用,在下文中, 此平行化處理將參考特定例子加以詳細解釋。 如下文將顯示,各平行化加速編碼器方塊包括儲存單元 ,例如第一群組正反器10,…,17以儲存輸入信號I (t)之η 個樣本I (t-1),…,I (t-n)以供應至平行化加速編碼器方塊 -22- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(20 ) 以及至少一儲存單元,例如第二群組正反器Q 〇,…,Q 7以 儲存平行化加速編碼器方塊至少一輸出信號Qj (t),j二1, ···,Μ 之 η 個樣本 Qj (t),···,Qj (t>(n-l))。 此外’加速編碼态裝置包括n個延遲單元(x丨,…,XN)之 延遲單元庫以及調適爲輸入信號I (t)之η個樣本之平行處 理’如此3延遲早元庫(Χι,…,χΝ)之至少二延遲單元直接 接收該輸入信號I⑴之η個樣本(Ι (Ν1), ,I (t-n))之子集 合以及該加速編碼器裝置之至少一延遲單元(Χι,…,乂“輸 出信號供應至該加速編碼器裝置之至少二延遲單元。 圖4顯示特定串g加速編碼器方塊電路圖,而可以使用 於圖8顯示之加速編碼器。 此處’必須注意輸入延遲單元1 6及輸出延遲單元1 8本 身不疋串列貫施之案例必要條件,但是在平行化案例中變 成必要以收集如圖3所示之輸入向量及輸出向量之元素。 圖4顯示之串列加速編碼器方塊可以藉由使用如上文介 紹之等式(1)之正式說明以N=3,M = i,α=[αι,^,叫 =[0, 1,、1] ’ β = [β丨,β2, β3, ρ4] = π,h 〇, i]加以簡短説明 。在下又中,將解釋此串列加速编碼器方塊如何可以平行 化馬η = 2, 4及8位元平行加速編碼器方塊。 仞子 Ν — 3,1,α二[0, 1, 1],β = [1,1, 0, 之2位元平行加速編碼器 由等式U)開始,我們獲得 (請先閱讀背面之注意事項再填寫本頁) R-裝 ·. #.Read the precautions on the back before I fill in this page 4 474068 A7 B7 V. Description of the invention (18) while (tmax > tn) (Please read the precautions on the back before filling in this page) {scan representation of internal state X ] ^ (t) for internal states with maximum time index tmax; · for (all internal states with maximum time index) {execute backward time index transition from tmax to tmax-l through state variable substitution using .eq. (2) above; } cancel double terms in representation of internal state xj ^ (t); tmax = tmax-l;}} / * parallelization of output variables * / printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs for (j = l; j < = M; j ++) {for (i = 0; i < = n-2; i + +) {/ * consider output vector element Qj (ti) * / -21-This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 474068 A7 B7 V. Description of the invention (19) tmax = til; while (tmax > tn) {scan representation of Qj (ti) for internal states with maximum time index; for (all int ernal states with maximum time index) {execute backward time index transition from tmax to t max '1 through state variable substitution using eq. (2) above; cancel double terms in representation of Qj (ti); one max -max " (please (Please read the notes on the back before filling out this page) (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs) / * end procedure * / To explain the application of the parallelization method generally described above, in the following, this parallelization process will be referred to Specific examples are explained in detail. As will be shown below, each parallelized acceleration encoder block includes a storage unit, such as a first group of flip-flops 10, ..., 17 to store n samples I (t-1) of the input signal I (t), ..., I (tn) is supplied to the parallel acceleration encoder block-22- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 474068 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Explanation (20) and at least one storage unit, such as a second group of flip-flops Q 0,..., Q 7 to store at least one output signal Qj (t), j 2 1, ... Η samples of M Qj (t), ..., Qj (t > (nl)). In addition, the "accelerated coding state device includes a delay cell library of n delay cells (x 丨, ..., XN) and parallel processing of n samples adapted to the input signal I (t)", such as a 3 delay early cell library (Xι, ... , ΧΝ) at least two delay units directly receive a subset of n samples (I (N1),, I (tn)) of the input signal I⑴ and at least one delay unit (Xι, ..., 乂 "of the acceleration encoder device The output signal is supplied to at least two delay units of the acceleration encoder device. Fig. 4 shows a block circuit diagram of a specific string g acceleration encoder, which can be used in the acceleration encoder shown in Fig. 8. Here 'we must pay attention to the input delay unit 16 and The output delay unit 18 itself does not have the necessary conditions of the serial execution case, but in the parallelization case it becomes necessary to collect the elements of the input vector and the output vector as shown in Figure 3. The serial acceleration encoder shown in Figure 4 Blocks can be formalized using equation (1) as described above with N = 3, M = i, α = [αι, ^, called = [0, 1 ,, 1] 'β = [β 丨, β2, β3, ρ4] = π, h 〇, i] In the next section, we will explain how this serial acceleration encoder block can parallelize η = 2, 4 and 8-bit parallel acceleration encoder blocks. 仞 子 Ν — 3,1, α 二 [0, 1, 1], β = [1,1, 0, The 2-bit parallel acceleration encoder starts with equation U), we get (Please read the precautions on the back before filling this page) R- 装 ·. #.
297公釐) 474068 A7 B7 五、發明說明(21 )297 mm) 474068 A7 B7 V. Description of the invention (21)
Xl(t) = I(t-l)㊉ x2(t-l)㊉ x3(t-l) (請先閱讀背面之注意事項再填寫本頁) X2(t) = X!(t-1) X3 (t) = x2 (t - 1) Q(t) = 1(匕-1)㊉ ㊉ x2(t-i) 如圖4顯示之加速編碼器方塊之説明。下列在二串列時間-循環之後向時間索引轉換爲必要: x:L(t:) = I(t-l)㊉ X2(t-1)㊉々(卜1) <=> Xl(t) = I(t-l)㊉ Xi(t-2)㊉ X2(t-2) 鑑於平行電路: => χι (ρ) = ΙΟ (p-1)㊉ X! (p-1)㊉ X2 (P-工) x2(t) = xx(t-1) < => x2(t) = 1(卜2)㊉ ^2(1-2)㊉ x3(t_2) 鑑於平行電路: => x2 (P)=工1 (ρ-l)㊉ X2 (P-1)㊉ x3 (P-1) 經濟部智慧財產局員工消費合作社印製 X3 (t) = X2 (t -1) < => X3(t) = (t-2 ) 鑑於平行電路: -24- 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) 474068 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(22) => X3(p) = Xi(p-1) Q(t) = Θ xi(t-l)㊉ X2(t-1) < => Q(t) = I(t-l)㊉[1(卜2)㊉ X2(t-2)㊉ x3(t-2)]㊉ X;L(t:-2)鑑於平行電路: => QO (p) = 10 (p-1)㊉ II (p-1)㊉ Xi (p-1)㊉ X2 (P-1)㊉.¾ (P-· 1) Q(t-l) = I(t-2)㊉ Xi(t:-2)㊉ χ2(^2)鑑於平行電路: _ => Ql(p) = Il(p-l)㊉ x^p-l)㊉々(P·*1〉圖5顯示此平行化處理之結果,亦即圖4顯示之加速編 碼器方塊之二位元實施之電路圖。3.2 例子:Ν=3,Μ=1,α=[0,1,1],β=[1,1,0,1] 之4位元平行加速編碼器 由等式(1)開始,我們獲得 X^t) = I(t-l)㊉ ㊉ X3(t-1) x2(t) = Xl(t-1) X3(t) = x2(t-1) Q(t) = I(t-1)㊉ Xl(t:-1)㊉ X2(匕-1) -25- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------r------^裝—— (請先閱讀背面之注意事項再填寫本頁) . 474068 A7 B7 五、發明說明(23) 如圖4顯示之加速編碼器方塊之説明。下列在四串列時間 循環之後向時間索引轉換爲必要: (請先閱讀背面之注意事項再填寫本頁) xyt) = I(t-l)㊉ x2(t-l)㊉ X3(t-1) < => Xl(t) = I(t-l)㊉ Χι(ί:-2)㊉ x2(t-2) < => xdt) = I(t-l)㊉工(t-3)㊉ x2(t-3)㊉ x3(t-3)㊉ Xl(t-3) < => xl(t) = I(t-l)㊉ I(t-3)㊉ χ;ι_(Ι:-4)㊉ X2(t-4)㊉ I(t-4)㊉ X2(t-4)㊉ x3(t-4) 鑑於平行電路: => Xl (P) =10(p-1)㊉工2(p-1) ®Ι3(ρ-1)Θχι(ρ-1)®Χ3(ρ- 1) x2⑻ =Ki(t-l) < => X2⑻ =工(t-2〉㊉ x2(t-2) ㊉ X3(t-2) < => x2 (t) =工(t-2)㊉ Χχ(t-3) ㊉ X2(匕 _ 3) · < => x2 (t) =工(t-2)㊉[I(t-4) ㊉ X2(t_4)㊉ x3(t-4)]㊉ 4) 鑑於平行電路: _ _ 經濟部智慧財產局員工消費合作社印製 => x2 (P)=工1 (P-1)㊉ 13 (p-1)㊉ Xl (p-i)㊉ X2 (p-D ㊉ χ3 (p_ 1) X3 (t) = X2 (t -1) -26- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 ___B7__ 五、發明說明(24 ) <=> X3(t) = Xi(t-2) (請先閱讀背面之注意事項再填寫本頁) < => x3(t)=[工(t-3)㊉ 乂2(匕-3)㊉ x3(t-3)] < => x3(t) = I(t-3)㊉ Xi(t-4)㊉ Qk-4) 鑑於平行電路: => X3 (P)=工2 (P-1)㊉ xi (P**1)㊉ x2 (P-1) r Q(t) = I(t-l)㊉ Χ]_(ί:-1)㊉:^2(1^1) < => Q(t) = I(t-l)㊉[I(t-2)㊉ x2(t_2)㊉ x3(t-2)]㊉ X]_(t:-2) < = :> Q(t) = I(t:-1)㊉ _I(t-2)、㊉ ㊉ x2(t-3)㊉ [工(t-3)㊉ X2(t-3)㊉ x3(t-3)] < => Q(t) = I(t-l)㊉ I(t-2)㊉ I(t-3)㊉ [工(t-4)㊉ X2(t-4) ® X3(t-4)]㊉ x2(匕-4) 鑑於平行電路: => QO (p)=工〇 (p-1)㊉工1 (p-1)㊉工2 (p-1)㊉工3 (p-1)㊉ X3 (p-1) 經濟部智慧財產局員工消費合作社印製 Q(t-l)=工(t-2)㊉ χ! (t-2)㊉ X2 (t-2) — < => Q(t-l) = I(t-2) Θ [工(t-3)㊉ Χ2(^3)㊉ 乂3(卜3)]㊉Xl (t) = I (tl) ㊉ x2 (tl) ㊉ x3 (tl) (Please read the notes on the back before filling this page) X2 (t) = X! (T-1) X3 (t) = x2 (t-1) Q (t) = 1 (dagger-1) ㊉ ㊉ x2 (ti) The description of the accelerated encoder block shown in Figure 4. The following is necessary to convert to a time index after a two-string time-loop: x: L (t :) = I (tl) ㊉ X2 (t-1) ㊉々 (Bu1) < = > Xl (t) = I (tl) ㊉ Xi (t-2) ㊉ X2 (t-2) Given the parallel circuit: = > χι (ρ) = ΙΟ (p-1) ㊉ X! (P-1) ㊉ X2 (P- Work) x2 (t) = xx (t-1) < = > x2 (t) = 1 (Bu 2) ㊉ ^ 2 (1-2) ㊉ x3 (t_2) Given the parallel circuit: = > x2 ( P) = Industrial 1 (ρ-1) ㊉ X2 (P-1) ㊉ x3 (P-1) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy X3 (t) = X2 (t -1) < = > X3 (t) = (t-2) Given the parallel circuit: -24- This paper size applies the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) 474068 A7 B7 Explanation of the invention (22) = > X3 (p) = Xi (p-1) Q (t) = Θ xi (tl) ㊉ X2 (t-1) < = > Q (t) = I (tl ) ㊉ [1 (卜 2) ㊉ X2 (t-2) ㊉ x3 (t-2)] ㊉ X; L (t: -2) Given the parallel circuit: = > QO (p) = 10 (p-1 ) ㊉ II (p-1) ㊉ Xi (p-1) ㊉ X2 (P-1) ㊉. ¾ (P- · 1) Q (tl) = I (t-2) ㊉ Xi (t: -2)平行 χ2 (^ 2) Given the parallel circuit: _ = > Ql (p) = Il (pl) ㊉ x ^ pl) ㊉々 (P · * 1 Figure 5 shows the result of this parallelization process, which is the circuit diagram of the two-bit implementation of the accelerated encoder block shown in Figure 4. 3.2 Example: N = 3, M = 1, α = [0, 1, 1], β = [1,1,0,1] 4-bit parallel acceleration encoder starts from equation (1), we get X ^ t) = I (tl) ㊉ ㊉ X3 (t-1) x2 (t) = Xl (t-1) X3 (t) = x2 (t-1) Q (t) = I (t-1) ㊉ Xl (t: -1) ㊉ X2 (dagger-1) -25- This paper size applies China National Standard (CNS) A4 specification (210 X 297 mm) ------ r ------ ^ installation-(Please read the precautions on the back before filling this page). 474068 A7 B7 5 2. Description of the invention (23) The description of the acceleration encoder block shown in FIG. 4. The following is necessary to convert to the time index after four series of time loops: (Please read the notes on the back before filling this page) xyt) = I (tl) ㊉ x2 (tl) ㊉ X3 (t-1) < = > Xl (t) = I (tl) ㊉ Χι (ί: -2) ㊉ x2 (t-2) < = > xdt) = I (tl) ㊉ 工 (t-3) ㊉ x2 (t- 3) ㊉ x3 (t-3) ㊉ Xl (t-3) < = > xl (t) = I (tl) ㊉ I (t-3) ㊉ χ; ι_ (Ι: -4) ㊉ X2 ( t-4) ㊉ I (t-4) ㊉ X2 (t-4) ㊉ x3 (t-4) Given the parallel circuit: = > Xl (P) = 10 (p-1) ㊉ 工 2 (p-1 ) ®Ι3 (ρ-1) Θχι (ρ-1) ®χ3 (ρ-1) x2⑻ = Ki (tl) < = > X2⑻ = 工 (t-2〉 ㊉ x2 (t-2) ㊉ X3 ( t-2) < = > x2 (t) = worker (t-2) ㊉χ (t-3) ㊉ X2 (2_ 3) · < = > x2 (t) = worker (t-2 ) ㊉ [I (t-4) ㊉ X2 (t_4) ㊉ x3 (t-4)] ㊉ 4) Given the parallel circuit: _ _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs = > x2 (P) = 工1 (P-1) ㊉ 13 (p-1) ㊉ Xl (pi) ㊉ X2 (pD ㊉ χ3 (p_ 1) X3 (t) = X2 (t -1) -26- CNS) A4 specification (210 X 297 mm) 474068 A7 ___B7__ 5. Description of the invention (24) < = > X3 (t) = Xi ( t-2) (Please read the notes on the back before filling this page) < = > x3 (t) = [工 (t-3) -3 乂 2 (dagger-3) ㊉ x3 (t-3)] < = > x3 (t) = I (t-3) ㊉ Xi (t-4) ㊉ Qk-4) Given the parallel circuit: = > X3 (P) = I 2 (P-1) ㊉ xi ( P ** 1) ㊉ x2 (P-1) r Q (t) = I (tl) ㊉ Χ] _ (ί: -1) ㊉: ^ 2 (1 ^ 1) < = > Q (t) = I (tl) ㊉ [I (t-2) ㊉ x2 (t_2) ㊉ x3 (t-2)] ㊉ X] _ (t: -2) < =: > Q (t) = I (t : -1) ㊉ _I (t-2), ㊉ ㊉ x2 (t-3) ㊉ [工 (t-3) ㊉ X2 (t-3) ㊉ x3 (t-3)] < = > Q ( t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ [工 (t-4) ㊉ X2 (t-4) ® X3 (t-4)] ㊉ x2 (匕 -4 ) Given the parallel circuit: = > QO (p) = worker 0 (p-1) worker 1 (p-1) worker 2 (p-1) worker 3 (p-1) ㊉ X3 (p-1 ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Q (tl) = 工 (t-2) ㊉ χ! (T-2) ㊉ X2 (t-2) — < = > Q (tl) = I ( t-2) Θ [工 (t-3) ㊉ Χ2 (^ 3) ㊉ 乂 3 (卜 3)] ㊉
Xl (t-3) <二> Q(t-l) = I(t-2)㊉ I(t-3)㊉ X]_(t-4)㊉ X2(t-4)㊉ [工(t-4)㊉ X2(t-4) ·㊉ X3(t-4)] -27- 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) 474068 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明(25)鑑於平行電路:=> Q1 (P) = II (ρ-1)㊉工2 (p-ι)㊉工3 (P-1)㊉ Xi (p-ι)㊉ x3 (p- 1) Q(t-2)=工(匕-3)㊉ X]_(t:-3)㊉ x2(t:-3) < => Q(t-2) = I(t-3)㊉[I(t-4)㊉ x2(t:-4)㊉ x3(t-4)]㊉ Xl (t-4)鑑於平行電路: => Q2 (P)=工2 (ρ-1) Φ 工3 (p-1)㊉ q (p-1)㊉ χ2 (p-ι)㊉ χ3 (p-1) » Q(t-3) = I(t-4)㊉ Xi(t-4)㊉ X2(t-4)鑑於平行電路: => Q3 (p)=工3 (p-1)㊉ 乂工(p-1)㊉ χ2 (p-1)圖6顯示此平行化處理之結果,亦即圖4顯示 < 加速编 碼方塊之四位元實施之電路圖。3.3 例子:N = 3,M = 1,α = [0,1,1],β = [1,1,0,1]之8位元平行加速編碼器 由等式(1)開始,我們獲得 -28- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 B7 五、發明說明(26)Xl (t-3) < two > Q (tl) = I (t-2) ㊉ I (t-3) ㊉ X] _ (t-4) ㊉ X2 (t-4) ㊉ [工 (t -4) ㊉ X2 (t-4) · ㊉ X3 (t-4)] -27- This paper size applies to China National Standard (CNS) A4 (210 χ 297 mm) 474068 Α7 Β7 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a consumer cooperative V. Description of the invention (25) Given the parallel circuit: = > Q1 (P) = II (ρ-1) ㊉ 工 2 (p-ι) ㊉ 工 3 (P-1) ㊉ Xi (p- ι) ㊉ x3 (p- 1) Q (t-2) = 工 (agger-3) ㊉ X] _ (t: -3) ㊉ x2 (t: -3) < = > Q (t-2 ) = I (t-3) ㊉ [I (t-4) ㊉ x2 (t: -4) ㊉ x3 (t-4)] ㊉ Xl (t-4) Given the parallel circuit: = > Q2 (P) = 工 2 (ρ-1) Φ 工 3 (p-1) ㊉ q (p-1) ㊉ χ2 (p-ι) ㊉ χ3 (p-1) »Q (t-3) = I (t-4 ) ㊉ Xi (t-4) ㊉ X2 (t-4) Given the parallel circuit: = > Q3 (p) = 工 3 (p-1) ㊉ ㊉ 工 (p-1) ㊉ χ2 (p-1) 6 shows the result of this parallelization process, that is, FIG. 4 shows a circuit diagram of the four-bit implementation of the accelerated coding block. 3.3 Example: N = 3, M = 1, α = [0,1,1], β = [1,1,0,1] The 8-bit parallel acceleration encoder starts from equation (1), we obtain -28- (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (26)
Xl(t) = I(t-l)㊉ x2(t-1)㊉ ^3( = .1) (請先閱讀背面之注意事項再填寫本頁) X2(t) = Χχ(t-1) X3(t) = x2(t-1) Q(t) = I(t-l)㊉ x^t-l)㊉ 乂2(亡-工) 如圖4顯示之加速編碼器方塊之説明。下列在八串列時間_ 循環之後向時間索引轉換爲必要:Xl (t) = I (tl) ㊉ x2 (t-1) ㊉ ^ 3 (= .1) (Please read the precautions on the back before filling this page) X2 (t) = χχ (t-1) X3 ( t) = x2 (t-1) Q (t) = I (tl) ㊉ x ^ tl) ㊉ 乂 2 (dead-work) The description of the acceleration encoder block shown in Figure 4. The following is converted to a time index after the eight-string time_ loop is necessary:
Xl(t) = I(t-l)㊉ X2(t-1)㊉ X3(t__1) < => Xl(t) = 1(匕-1)㊉ X2_(t:-2)㊉ X2(t-2) < => Xl(t) = I(t_l)㊉[工(t-3) Θ X2(t-3)㊉ x3(t-3)]㊉ xl(匕-3) <=> Xl(t) = I(t-l)㊉ I(t-3)㊉ Xi(t-4)㊉ X2(t-4)㊉ [I(t-4)㊉ X2(t·4)㊉ x3(t-4)] <=> X工(t) = I(t-l)㊉ I(t-3)㊉ 1(匕-4)㊉ [I(t-5)㊉ x2(t-5)㊉ x3(t-5)]㊉ x2(t:-5) < => X]_(t) = I(t-l)㊉ I(t-3)㊉ I(t-4)㊉ I(t-5)㊉ X2(t_6) .xUt) = I(t-l)㊉ I(t-3)㊉ I(t-4)㊉ I(t-5)㊉ 乂工(1:-7) 經濟部智慧財產局員工消費合作社印製 < => Xl(t) = I(t-l)㊉ I(t-3)㊉ I(t-4)㊉ I(t-5)㊉ [工(t-8)㊉ X2(t-8)㊉ X3(t-8)] -29- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 B7 五、發明說明(27) 鑑於平行電路: (請先閱讀背面之注意事項再填寫本頁) => Χι (ρ)=工0 (p-1)㊉工2 (p-1)㊉工3 (p-1)㊉ 14 (p-1)㊉ I7(p-1)㊉ χ2(ρ-1) Φ X3(P-1) X2(t) = χχ(t-1) < => x2(t) = [;E(t-2)㊉ x2(t-2)㊉ x3(t-2)] < => X2(t)=工(匕-2)㊉ X]_(t-3)㊉ X2(t-3) < => X2(t) = I(t-2)㊉[工(t - 4)㊉ X2(t「4)㊉ x3(t-4)]㊉Xl (t) = I (tl) ㊉ X2 (t-1) ㊉ X3 (t__1) < = > Xl (t) = 1 (dagger-1) ㊉ X2_ (t: -2) ㊉ X2 (t- 2) < = > Xl (t) = I (t_l) ㊉ [工 (t-3) Θ X2 (t-3) ㊉ x3 (t-3)] ㊉ xl (匕 -3) < = > Xl (t) = I (tl) ㊉ I (t-3) ㊉ Xi (t-4) ㊉ X2 (t-4) ㊉ (I (t-4) ㊉ X2 (t · 4) ㊉ x3 (t -4)] < = > X (t) = I (tl) ㊉ I (t-3) ㊉ 1 (dagger-4) ㊉ [I (t-5) ㊉ x2 (t-5) ㊉ x3 (t-5)] ㊉ x2 (t: -5) < = > X) _ (t) = I (tl) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5 ) ㊉ X2 (t_6) .xUt) = I (tl) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ ㊉ 工 (1: -7) Staff of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Consumer Cooperatives < = > Xl (t) = I (tl) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ [工 (t-8) ㊉ X2 ( t-8) ㊉ X3 (t-8)] -29- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (27) Given the parallel circuit: (Please (Read the precautions on the back before filling this page) => χι (ρ) = 工 0 (p-1) ㊉ 工 2 (p-1) ㊉ 工 3 (p-1) ㊉ 14 (p-1) ㊉ I7 (p-1) ㊉ χ2 (ρ-1) Φ X3 (P-1) X2 (t) = χχ (t-1) < = > x2 (t) = [; E (t-2) ㊉ x2 (t-2) ㊉ x3 (t-2)] < = > X2 (t) = 工 (agger-2) ㊉ X] _ (t-3) ㊉ X2 (t-3) < = > X2 (t) = I (t-2) ㊉ [工(T-4) ㊉ X2 (t 「4) ㊉ x3 (t-4)] ㊉
Xl (t-4) · < => X2(t)=工(卜2)㊉ 1(卜4)㊉ Xi(t-5)㊉ X2(t-5)㊉ [I(t-5)㊉ x2(t-5)㊉ x3(t-5)] < => x2(t) = I(t-2)㊉ I(t-4)㊉ I(t:-5)㊉ [工(匕-6) Θχ2( = -6)㊉ x3(t-6)]㊉ 乂2(匕-6) < => x2(t) = I(t-2)㊉ I(t-4)㊉ I(t-5)㊉ 1(仁-6)㊉ χ2(^7) < => x2(t) = I(t:-2)㊉ I(t-4)㊉ I(t-5)㊉ I(t:-6)㊉ xyt-S) 鑑於平行電路: 經濟部智慧財產局員工消費合作社印製 => X2 (P)=工1 (p-1)㊉工3 (p-1)㊉工4 (p-1)㊉ 15 (p-1)㊉ Xi (p-1) X3(t) = x2(t-1) < => x3 (t) = (t-2) -30- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 B7 五、發明說明(28) < => x3(t) = [;[(t:-3)㊉ X2(t-3)㊉ x3(t-3)] (請先閱讀背面之注意事項再填寫本頁) < => Χ3(1)=工(t-3)㊉ X]_(t:-4)㊉ X2(t_4) < => X3(t) = ㊉[I(t-5)㊉ X2(t-5)㊉ X3(匕縛5)]㊉ xl(匕- 5) < = :> X3(t) = I(t-3)㊉ I(t-5)㊉ Xi(t-6)㊉ X2(t-6)㊉ [工(t-6)㊉ x2(t-6)㊉ x3(t-6)] < => x3(t:) = I(t-3)㊉ I(t-5)㊉ I(t-6)㊉ [I(t-7)㊉ x2(匕_7)㊉ 乂3(匕-7)]㊉ x2(t-7) < => x3(t) = I(t-3)㊉工(t-5)㊉工(t-6)㊉工(匕-7)㊉ x2(t-8) 鑑於平行電路·· => X3 (P)=工2 (p-1)㊉工4 (p-1)㊉ 15 (p-1)㊉工6 (p-1)㊉ x2 (p-1) Q(t) = I(t-l)㊉ xUt-l)㊉;^2(=-工) < => Q(t) = I(t-l)㊉[I(t-2)㊉ x2(t:-2)㊉ x3(t-2)]㊉ -2) < => Q(t) = I(t-l)㊉ I(t-2)㊉ X]L(t:-3)㊉ x2((t-3)㊉· 經濟部智慧財產局員工消費合作社印製 [工(t-3)㊉ X2(t - 3)㊉ x3(t-3)] -- < => Q(t) = 1(匕-1)㊉ I(t-2)㊉ I(t-3)㊉ [工(t-4)㊉ X2((t-4)㊉ x3(t-4)]㊉ x2((t-4) < => Q(t) = I(t-l)㊉ I(t-2)㊉工(t-3)由 1(匕-4)㊉ x2((t-5) < => Q(t) = I(t-l)㊉ I(t-2)㊉ I(t-3)㊉ I(t-4)㊉ xUt-S) -31 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 B7 五、發明說明(29) < => Q(t) = I(t-l)㊉ I(t-2)㊉ I(t-3)㊉ I(t-4)㊉ [工(t-7)㊉ x2(t-7)㊉ X3(t-7)] < = >· Q(t) = I(t-l)㊉ I(t-2)㊉ I(t-3)㊉ I(t-4)㊉ I(t-7)㊉ x丄(t-8)㊉ X2(t-8) 鑑於平行電路: => QO(p) = IO(p-l)㊉工 1(ρ-1)㊉ I2(p-1)㊉ I3(p-1)㊉ I6(p-1)㊉ χ工(p-1)㊉ χ2(Ρ_1) Q(t-l) = I(t-2)㊉ xytO ㊉ X2(t-2) < => Q(t-l) = I(t-2)㊉[I(t-3)㊉ x2(t-3)㊉ x3(t-3)]㊉ X]_ (t - 3 ) < => ’Q(t-l) = I(t-2)㊉ I(t-3)㊉ ^(¢:-4)㊉ x2((t-4)㊉ [工(t-4)㊉ x2(t:-4)㊉ x3(t-4)] < => Q(t-l) = I(t-2)㊉ I(t-3)㊉ 1(卜4)㊉· [I(t:-5)㊉ X2(t-5)㊉ X3(t-5)]㊉ X2(t-5) 經濟部智慧財產局員工消費合作社印製 ------------裝--- (請先閱讀背面之注意事項再填寫本頁) < => Q(t:-1) = I(t-2)㊉ I(t-3)㊉ I(t-4)㊉ I(t-5)㊉ x2(t-6) < => Q(t-l) = I(t-2)㊉工(匕-3)㊉ I(t-4)㊉ I(t-5)㊉ < => Q(t-1) = I(t-2)㊉ I(t-3)㊉ I(t-4)㊉ I(t-5)㊉ [工(t-8)㊉ x2(t-8)㊉ x3(t-8)] -32- 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) 474068 A7 B7 五、發明說明(3Q) 鑑於平行電路: (請先閱讀背面之注意事項翔填寫本頁) => Ql(p) = Il(p-l)㊉工 2(p-l)㊉工 3(p-l)㊉工 4(p-l)㊉ I7(p-1)㊉ χ2(ρ-ΐ)㊉ χ3(ρ_ι) Q(t-2) = I(t-3)㊉:^(1:-3)㊉:^2(亡-3) < => Q(卜2) =: I(t-3)㊉[I(t-4)㊉ x2(t-4)㊉ x3(t-4)]㊉ Χχ(t-4) < => Q(t:-2) = I(t-3)㊉ 1(匕-4)㊉ xyt-S)㊉ xsk-5)㊉ [工(t-5) _ ㊉ X2(t-5)㊉ x:3(t-5)] < => Q(t-2)=工(卜3)㊉工(t-4)㊉工(t-5)㊉ [工(t-6)㊉ X2(t-6)㊉ X3(t-6)]㊉ x2(t-6) < => Q(t-2) = I(t-3)㊉ I(t-4)㊉ I(t-5)㊉ I(t-6)㊉ x2(匕-7) <=> Q(t-2〉 = I(t-3)㊉ I(t-4)㊉ I(t-5)㊉ I(t-6)㊉ Xi(t-8) 鑑於平行電路: => Q2 (p)=工2 (ρ-l)㊉工3 (ρ-l)㊉工4 (ρ-l)㊉工5 (ρ-l)㊉ 乂工(p-1) 經濟部智慧財產局員工消費合作社印製 Q(t-3)=工(t-4)㊉ Xi(t-4)㊉ X2(t-4) < => Q(t_3) = I(t-4)㊉[I(t-5)㊉ x2(ft-5)㊉ x3(t-5)]㊉Xl (t-4) · < = > X2 (t) = Gong (Bu 2) ㊉ 1 (Bu 4) ㊉ Xi (t-5) ㊉ X2 (t-5) ㊉ [I (t-5) ㊉ x2 (t-5) ㊉ x3 (t-5)] < = > x2 (t) = I (t-2) ㊉ I (t-4) ㊉ I (t: -5) ㊉ [工 ( D-6) Θχ2 (= -6) ㊉ x3 (t-6)] ㊉ 乂 2 (D-6) < = > x2 (t) = I (t-2) ㊉ I (t-4) ㊉ I (t-5) ㊉ 1 (仁 -6) ㊉ χ2 (^ 7) < = > x2 (t) = I (t: -2) ㊉ I (t-4) ㊉ I (t-5) ㊉ I (t: -6) ㊉ xyt-S) Given the parallel circuit: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs = > X2 (P) = Industrial 1 (p-1) Industrial 3 (p-1) ㊉ 工 4 (p-1) ㊉ 15 (p-1) ㊉ Xi (p-1) X3 (t) = x2 (t-1) < = > x3 (t) = (t-2) -30 -This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (28) < = > x3 (t) = [; [(t: -3) ㊉ X2 (t-3) ㊉ x3 (t-3)] (Please read the precautions on the back before filling this page) < = > χ3 (1) = 工 (t-3) ㊉ X] _ (t: -4) ㊉ X2 (t_4) < = > X3 (t) = ㊉ (I (t-5) ㊉ X2 (t-5) ㊉ X3 (dagger-5)] ㊉ xl (dagger-5) < =: > X3 (t) = I (t-3) ㊉ I (t-5) ㊉ Xi (t-6) ㊉ X2 (t-6) ㊉ [工 (t-6) ㊉ x2 (t-6 ) ㊉ x3 (t-6)] < = > x3 (t :) = I (t-3) ㊉ I (t-5) ㊉ I (t-6) ㊉ (I (t-7) ㊉ x2 (dagger_7) ㊉ 乂 3 (dagger-7)] ㊉ x2 ( t-7) < = > x3 (t) = I (t-3) workers (t-5) workers (t-6) workers (dagger-7) ㊉ x2 (t-8) Circuit · == X3 (P) = Work 2 (p-1) Work 4 (p-1) ㊉ 15 (p-1) Work 6 (p-1) ㊉ x 2 (p-1) Q ( t) = I (tl) ㊉ xUt-l) ㊉; ^ 2 (=-工) < = > Q (t) = I (tl) ㊉ [I (t-2) ㊉ x2 (t: -2 ) ㊉ x3 (t-2)] ㊉ -2) < = > Q (t) = I (tl) ㊉ I (t-2) ㊉ X) L (t: -3) ㊉ x2 ((t- 3) ㊉ · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [工 (t-3) ㊉ X2 (t-3) ㊉ x3 (t-3)]-< = > Q (t) = 1 ( D-1) ㊉ I (t-2) ㊉ I (t-3) ㊉ [工 (t-4) ㊉ X2 ((t-4) ㊉ x3 (t-4)] ㊉ x2 ((t-4) < = > Q (t) = I (tl) ㊉ I (t-2) ㊉ (t-3) from 1 (dagger-4) ㊉ x2 ((t-5) < = > Q ( t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ I (t-4) ㊉ xUt-S) -31-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (29) < = > Q (t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ I (t-4)工 [工 (t-7) ㊉ x2 (t-7) ㊉ X3 (t-7)] < = > · Q (t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-7) ㊉ x 丄 (t-8) ㊉ X2 (t-8) Given the parallel circuit: = > QO (p) = IO (pl) ㊉ 工 1 (ρ-1) ㊉ I2 (p-1) ㊉ I3 (p-1) ㊉ I6 (p-1) ㊉ χ (p-1) ㊉ χ2 (P_1) Q (tl) = I (t-2) ㊉ xytO ㊉ X2 (t-2) < = > Q (tl) = I (t-2) ㊉ (I (t-3) ㊉ x2 (t-3 ) ㊉ x3 (t-3)] ㊉ X] _ (t-3) < = > 'Q (tl) = I (t-2) ㊉ I (t-3) ㊉ ^ (¢: -4) ㊉ x2 ((t-4) ㊉ [工 (t-4) ㊉ x2 (t : -4) ㊉ x3 (t-4)] < = > Q (tl) = I (t-2) ㊉ I (t-3) ㊉ 1 (Bu 4) ㊉ [I (t: -5) ㊉ X2 (t-5) ㊉ X3 (t-5)] ㊉ X2 (t-5) Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative ------------ install --- (Please read the notes on the back before filling this page) < = > Q (t: -1) = I (t-2 ) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ x2 (t-6) < = > Q (tl) = I (t-2) 3) ㊉ I (t-4) ㊉ I (t-5) ㊉ < = > Q (t-1) = I (t-2) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ [工 (t-8) ㊉ x2 (t-8) ㊉ x3 (t-8)] -32- This paper size is applicable to China National Standard (CNS) A4 (210 x 297 mm) 474068 A7 B7 V. Description of the Invention (3Q) Given the parallel circuit: (Please read first Read the notes on the back and fill in this page) => Ql (p) = Il (pl) pl 工 2 (pl) ㊉ 工 3 (pl) ㊉ 工 4 (pl) ㊉ I7 (p-1) ㊉ χ2 ( ρ-ΐ) ㊉ χ3 (ρ_ι) Q (t-2) = I (t-3) ㊉: ^ (1: -3) ㊉: ^ 2 (die-3) < = > Q (Bu 2) =: I (t-3) ㊉ [I (t-4) ㊉ x2 (t-4) ㊉ x3 (t-4)] ㊉ χχ (t-4) < = > Q (t: -2) = I (t-3) ㊉ 1 (匕 -4) ㊉ xyt-S) ㊉ xsk-5) ㊉ [工 (t-5) _ ㊉ X2 (t-5) ㊉ x: 3 (t-5)] < = > Q (t-2) = Gong (Bu 3) Gong (t-4) Gong (t-5) ㊉ [Gong (t-6) ㊉ X2 (t-6) ㊉ X3 (t -6)] ㊉ x2 (t-6) < = > Q (t-2) = I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ I (t-6) 2 x2 (dagger-7) < = > Q (t-2> = I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ I (t-6) ㊉ Xi (t -8) Given the parallel circuit: = > Q2 (p) = worker 2 (ρ-l) worker 3 (ρ-l) worker 4 (ρ-l) worker 5 (ρ-l) worker ( p-1) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Q (t-3) = Industrial (t-4) ㊉ Xi (t-4) ㊉ X2 (t-4) < = > Q (t_3) = I (t-4) ㊉ [I (t-5) ㊉ x2 (ft-5) ㊉ x3 (t-5)] ㊉
Xl (t-5) -33- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 B7 五、發明說明(31) < => Q(t-3) = I(t-4)㊉ I(t-5)㊉ Xi(t:-6) Θ x2(t_6)㊉ [工(t - 6)㊉ X2 (亡-6 )㊉ X3 (亡弓)] < => Q(t-3) = I(t-4)㊉ I(t-5)㊉ I(t-6)㊉ [工(t-7) Θ X2(t-7)㊉ ㊉ x2(t_7) < => Q(卜3) = I(t-4) Θ I(t-5)㊉工(卜6)㊉工(t-7)㊉ X2(t-8) 鑑於平行電路: => Q3 (p)=工3 (p-1)㊉工4 (p-1)㊉工5 (p-1)㊉ 16 (p-1)㊉ x2 (P-1) Q(t-4) = :E(t-5)㊉ xyt-S)㊉ x2(t-5) < => Q(t-4) = I(t:-5)㊉[I(t-6)㊉ Χ2(^6)㊉ χ3(^6)]㊉ Χχ (t-6) < => Q(t-4) = I(t-5)㊉ I(t-6)㊉ xyt-?)㊉ x2(t-7)㊉ [工(t-7)㊉ x2 (t-7)㊉ x3 (t-7)] < => Q(t-4) =I(t-5)㊉ I(t-6)㊉ I(t-7)㊉ [工(t-8)㊉ Χ2(υ)㊉ x3(t-8)]㊉ X2(t-8) -34- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------------- (請先閱讀背面之注意事項再填寫本頁) 訂: 經濟部智慧財產局員工消費合作社印製 474068 A7 B7 五、發明說明(32) 鑑於平行電路: (請先閱讀背面之注意事項再填寫本頁) => Q4 (p)=工4 (p-1)㊉工5 (p-1)㊉工6 (p-1)㊉工7 (p-1)㊉ X3 (P-1) Q(t-5) = I(t-6)㊉ Χι_(ί:-6)㊉:<2(亡一6) < => Q(t-5) = I(t-6)㊉[工(t-7)㊉ χ2(^7)㊉ x3(t_7)]㊉Xl (t-5) -33- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (31) < = > Q (t-3) = I (t-4) ㊉ I (t-5) ㊉ Xi (t: -6) Θ x2 (t_6) ㊉ [工 (t-6) ㊉ X2 (亡 -6) ㊉ X3 (亡 弓)] < = > Q (t-3) = I (t-4) ㊉ I (t-5) ㊉ I (t-6) ㊉ [工 (t-7) Θ X2 (t-7) ㊉ ㊉ x2 (t_7 ) < = > Q (Bu 3) = I (t-4) Θ I (t-5) ㊉ 工 (卜 6) ㊉ 工 (t-7) ㊉ X2 (t-8) Given the parallel circuit: = > Q3 (p) = Worker 3 (p-1) Worker 4 (p-1) Worker 5 (p-1) ㊉ 16 (p-1) ㊉ x2 (P-1) Q (t-4) =: E (t-5) ㊉ xyt-S) ㊉ x2 (t-5) < = > Q (t-4) = I (t: -5) ㊉ [I (t-6) ㊉ χ2 ( ^ 6) ㊉ χ3 (^ 6)] ㊉ χχ (t-6) < = > Q (t-4) = I (t-5) ㊉ I (t-6) ㊉ xyt-?) ㊉ x2 ( t-7) ㊉ [工 (t-7) ㊉ x2 (t-7) ㊉ x3 (t-7)] < = > Q (t-4) = I (t-5) ㊉ I (t- 6) ㊉ I (t-7) ㊉ [工 (t-8) ㊉ Χ2 (υ) ㊉ x3 (t-8)] ㊉ X2 (t-8) -34- The paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------------- (Please read the notes on the back before filling out this page) Order: Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Sakusha Co., Ltd. 474068 A7 B7 V. Description of the invention (32) In view of parallel circuits: (Please read the notes on the back before filling out this page) = > Q4 (p) = 工 4 (p-1) ㊉ 工 5 ( p-1) ㊉ 工 6 (p-1) ㊉ 工 7 (p-1) ㊉ X3 (P-1) Q (t-5) = I (t-6) ㊉ Χι_ (ί: -6) ㊉: < 2 (死 一 6) < = > Q (t-5) = I (t-6) ㊉ [工 (t-7) ㊉ χ2 (^ 7) ㊉ x3 (t_7)] ㊉
Xl (t-7) < => Q(t-5) = I(t-6)㊉工(t-7)㊉ ^(68) Θ X2(t_8)㊉ [工(t-8)㊉ X2(t-8)㊉ χ3(^8)] 鑑於平行電路: => Q5(p) = I5(p-1)㊉工6(p-l)㊉工7(p-l)㊉ xi(P-l)㊉ X3(P_ 1) . Q(t-6) = I;(t:-7)㊉ Xi(t-7)㊉ X2(t-7) <=> Q(t-6) = I(t-7)㊉[I(t-8)㊉ X2(t-8) Θ x3(t-8)]㊉ Χχ (t-8) 鑑於平行電路: 經濟部智慧財產局員工消費合作社印製 => Q6 (p)=工6 (p-1)㊉工7 (p-1)㊉ x;l (p-1)㊉ x2 (P·*1〉㊉ x3 (P-1) Q(t-7) = I(t-8)㊉ xyt-S)㊉ x2(t-8) -35- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(33 ) 鑑於平行電路: => Q7 (p)=工7 (ρ-l)㊉ Χ]_ (p-1)㊉ χ2 (p-工) •圖7Α及7Β顯示此平行化處理之牡果 心、、"果,吓即圖4顯示之 加速編碼方塊之八位元實施之電路圖。 4. VHDL ^ 上文以步驟接步驟方式説明之遞迴平行化可以邏輯综合 工具使用以比較不同設計替代方案。不限於任何此種特別 系統,此處參考非常鬲速硬體說明語言VHDL爲使用邏輯 综合工具之邏輯電跨設計之典型例子。 加速編碼器方塊平行化結果實施方式之vhdl碼優點爲 設計可以很短時間實現而不用局限於特定技術,例如 或是FPGA。 因此,實際技術不經由加速編碼器方塊平行化結果加以 規範,但是可以設定爲將由編碼後續之邏輯综合工具處理 之參數,因此與不同設計選擇比較爲容易改變。 、 在下文中’ VHDL碼爲圖5,6以及7顯示之2,4以及8 位元平行化加速編碼器方塊列出。由於V η d L碼語今在相 關技藝爲熟知以及關於上文解釋之平行化結果爲不言而喻 ,所以此處將不給予其他細節解釋。 LIBRARY ieee; USE ieee.std—logic一1164.ALL; ------I---— 裝·---I---訂---I----- (請先閱讀背面之注意事項再填寫本頁) -36 474068 A7 B7 五、發明說明(34 USE ieee . std_logic__arith. ALL; ENTITY en一turb〇_c〇der—rt:l IS • PORT ( -- General: reset:—p clk32m input: 一 8 input_4 input_2 input__l :工N STD一L·CλGIC; : 工N STD_L〇GIC; -- Clock (rising edge triggered) IN std一logic一vector(7 DOWNTO 0); IN std_logic_vector(3 DOWNTO 0); IN std一logic一vector(1 DOWNTO 0); IN std_logic; turboCoding 2 bit parallel output_8 output_4 〇utput_2 output 1 END en turbo coder rtl; OUT std一logic—vector(7 DOWNTO 0); 〇UT std一logic—vector(3 DOWNTO 0); OUT std_logic_vector(1 DOWNTO 0); OUT std—logic (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Xl (t-7) < = > Q (t-5) = I (t-6) ㊉ 工 (t-7) ㊉ ^ (68) Θ X2 (t_8) ㊉ [工 (t-8) ㊉ X2 (t-8) ㊉ χ3 (^ 8)] Given the parallel circuit: = > Q5 (p) = I5 (p-1) ㊉ 工 6 (pl) ㊉ 工 7 (pl) ㊉ xi (Pl) ㊉ X3 (P_ 1). Q (t-6) = I; (t: -7) ㊉ Xi (t-7) ㊉ X2 (t-7) < = > Q (t-6) = I (t- 7) ㊉ [I (t-8) ㊉ X2 (t-8) Θ x3 (t-8)] ㊉ χχ (t-8) Given the parallel circuit: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs = > Q6 (p) = 6 (p-1) and 7 (p-1) ㊉ x; l (p-1) ㊉ x2 (P · * 1> ㊉ x3 (P-1) Q (t-7) = I (t-8) ㊉ xyt-S) ㊉ x2 (t-8) -35- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 474068 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy System A7 V. Description of the invention (33) Given the parallel circuit: = > Q7 (p) = 工 7 (ρ-l) ㊉ Χ] _ (p-1) ㊉ χ2 (p- 工) • Figures 7A and 7B show This parallelization process results in a circuit diagram of the eight-bit implementation of the accelerated coding block shown in FIG. 4. 4. VHDL ^ The recursive parallelism explained above step by step can be used as a logical synthesis tool to compare different design alternatives. Without being limited to any such special system, the very fast hardware description language VHDL is referenced here as a typical example of logic span design using logic synthesis tools. The advantage of the implementation of the accelerated encoder block parallelization implementation of the vhdl code is that the design can be implemented in a short time without being limited to a specific technology, such as FPGA. Therefore, the actual technology is not standardized by accelerating the parallelization of the encoder block, but it can be set to a parameter that will be processed by the logical synthesis tool following the encoding, so it is easy to change compared with different design choices. In the following, the VHDL codes are listed in the 2, 4 and 8-bit parallel acceleration encoder blocks shown in Figures 5, 6 and 7. Since the V η d L codeword is well known in related arts today and the parallelization results explained above are self-evident, no further details will be given here. LIBRARY ieee; USE ieee.std—logic 一 1164.ALL; ------ I ----- Install · --- I --- Order --- I ----- (Please read the Please fill in this page again for attention) -36 474068 A7 B7 V. Invention Description (34 USE ieee. Std_logic__arith. ALL; ENTITY en_turb〇_c〇der—rt: l IS • PORT (-General: reset :—p clk32m input: one 8 input_4 input_2 input__l: industrial N STD_L · CλGIC;: industrial N STD_L〇GIC;-Clock (rising edge triggered) IN std_logic_vector (7 DOWNTO 0); IN std_logic_vector (3 DOWNTO 0 ); IN std_logic_vector (1 DOWNTO 0); IN std_logic; turboCoding 2 bit parallel output_8 output_4 〇utput_2 output 1 END en turbo coder rtl; OUT std_logic_vector (7 DOWNTO 0); 〇UT std_logic —Vector (3 DOWNTO 0); OUT std_logic_vector (1 DOWNTO 0); OUT std—logic (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs
ARCHITECTUilE rtl OF en turbo coder rtl IS SIGNAL si一xl SIGNAL· si一x2 SIGNAL si一x3 SIGNAL sl_i SIGNAL· si o std一logic; std一logic; std_logic; std—logic; std一logic; -37- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 474068 A7 B7 五、發明說明(35) SIGNAL s2_ jkI std一 _logic; SIGNAL· s2_ 一 x2 std_ _l〇gic ; SIGNAL s2_ 一 std 一 .logic/ SIGNAL· s2_ 一 i std 一 JLogic一vector* (1 DOWNTO 〇); SIGNAL· s2_ 一 o std一 logic一vector(1 DOWNTO 〇); SIGNAL s4_ 一 xl std_ ^logic ; SIGNAL s4_ _x2 std一 logic; SIGNAL s4_ __x3 std_ 一logic; SIGNAL s4_ 一 i std_ logic—vector(3 DOWNTO 〇); SIGNAL· s4· 一 o std_ logic一vector(3 DOWNTO 〇); SIGNAL· s8 一 xl std_ ^logiq; SIGNAL s8 __x2 std_ logic ; SIGNAL s8 一x3 std_ 一iogic; SIGNAL· s8 一 i std_ logic一vector* (7 DOWNTO 〇); SIGNAL s8 —〇 std_ logic—vector(7 DOWNTO 〇); BEGIN tc : 1 : PROCESS (clk32m, reset_ p) -- seriell building of (請先閱讀背面之注意事項再填寫本頁) 裝 訂·· 經濟部智慧財產局員工消費合作社印製ARCHITECTUilE rtl OF en turbo coder rtl IS SIGNAL si_xl SIGNAL · si_x2 SIGNAL si_x3 SIGNAL sl_i SIGNAL · si o std_logic; std_logic; std_logic; std_logic; std_logic; -37- paper Standards apply to China National Standard (CNS) A4 specifications (210 X 297 mm) 474068 A7 B7 V. Description of invention (35) SIGNAL s2_ jkI std__logic; SIGNAL · s2_ one x2 std_ _l0gic; SIGNAL s2_ one std one .logic / SIGNAL · s2_ a i std a JLogic a vector * (1 DOWNTO 〇); SIGNAL · s2_ a o std a logic a vector (1 DOWNTO 〇); SIGNAL s4_ a xl std_ ^ logic; SIGNAL s4_ _x2 std a logic SIGNAL s4_ __x3 std_ a logic; SIGNAL s4_ a i std_ logic—vector (3 DOWNTO 〇); SIGNAL · s4 · a o std_ logic a vector (3 DOWNTO 〇); SIGNAL · s8 a xl std_ ^ logiq; SIGNAL s8 _8 std_ logic; SIGNAL s8-x3 std_-iogic; SIGNAL · s8-i std_ logic-vector * (7 DOWNTO 〇); SIGNAL s8 —〇std_ logic — vector (7 DOWNTO 〇); BEGIN tc: 1: PROCE SS (clk32m, reset_ p)-seriell building of (Please read the notes on the back before filling out this page) Binding ·· Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
turbo coder block TCBturbo coder block TCB
BEGIN IF reset—p = 11' THEN si xl <= '0'; -38- 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 經濟部智慧財產局員工消費合作社印製 474068 A7 _B7 五、發明說明(36 ) sl__ 一 x2 < = 1 0 ' / si _x3 < = '0 '; si一 _i < = '0 ,; si一 _〇 < = '0 '; ELSIF clk^m'EVENT AND clk32m = ' 1 1 THEN si一i <= input一1; si—xl <= sl__i XOR sl_x2 XOR sl___x3; si一x2 <= sl—xl; s1—x3 < = sl—x2; sl_〇 <=sl__i XOR sl_x2 XOR sl_xl; END IF; END PROCESS tc_l; output__l <= sl_o; tc一2: PROCESS (clk32m/ reset_p) -- 2bit parallel building of turbo coder blockBEGIN IF reset—p = 11 'THEN si xl < =' 0 '; -38- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474068 A7 _B7 V. Description of the invention (36) sl__ a x2 < = 1 0 '/ si _x3 < =' 0 '; si a_i < =' 0,; si a_〇 < = '0' ; ELSIF clk ^ m'EVENT AND clk32m = '1 1 THEN si-i < = input-1 1; si-xl < = sl__i XOR sl_x2 XOR sl___x3; si-x2 < = sl-xl; s1-x3 < = sl—x2; sl_〇 < = sl__i XOR sl_x2 XOR sl_xl; END IF; END PROCESS tc_l; output__l < = sl_o; tc-1 2: PROCESS (clk32m / reset_p)-2bit parallel building of turbo coder block
BEGIN IF reset_p = '1' THEN s2—xl <= '0'; 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ----------I— — — — — — II ^ ·11111111 . (請先閱讀背面之注意事項再填寫本頁) 474068 A7 _______B7 _ 五、發明說明(37) s2—x2 < = 'Ο '; s2」c3 <= 1 Ο 1 ; s2一i <= (OTHERS => ·0·); s2一〇 <= (OTHERS => '0');BEGIN IF reset_p = '1' THEN s2—xl < = '0'; This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---------- I-- — — — — — II ^ · 11111111. (Please read the notes on the back before filling this page) 474068 A7 _______B7 _ V. Description of the invention (37) s2—x2 < = 'Ο'; s2 ″ c3 < = 1 Ο 1 ; s2—i < = (OTHERS = > · 0 ·); s2—0 < = (OTHERS = >'0');
ELSIF clk32m'EVENT AND clk32m = '1' THEN s2—i <= input—2; s2一xl <= s2—i(0) X〇R s2一xl X〇R s2一x2; s2_x2 <= s2_i(1) XOR s2一x2 X〇R s2一x3; s2_x3 <= s2一xl; s2—o(0) <= s2Ji (0) X〇R · s2一i(l) X〇R s2一xl X〇R s2一x2 X〇R s2_jk3; s2一o(l) <= s2一i(l) X〇R s2一xl X〇R s2—x2; END IF; END PROCESS tc_2; output—2 <= s2_o; tc___4 : PROCESS (clk32m/ reset_p) -- 4bit parallel building of turbo coder block 9ELSIF clk32m'EVENT AND clk32m = '1' THEN s2—i < = input—2; s2—xl < = s2—i (0) X〇R s2—xl X〇R s2—x2; s2_x2 < = s2_i (1) XOR s2-x2 X〇R s2-x3; s2_x3 < = s2-xl; s2-o (0) < = s2Ji (0) X〇R · s2-i (l) X〇R s2 -Xl X〇R s2-x2 X〇R s2_jk3; s2-o (l) < = s2-i (l) X〇R s2-xl X〇R s2—x2; END IF; END PROCESS tc_2; output— 2 < = s2_o; tc___4: PROCESS (clk32m / reset_p)-4bit parallel building of turbo coder block 9
BEGINBEGIN
IF reset一p =言1, THEN -40 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 請 先 閱 讀 背 面 之 注 意 h 經濟部智慧財產局員工消費合作社印製 474068 A7 B7 五、發明說明(38) s4_ _xl <='0 1 / s4_ _x2 <=1 0 ' / s4_ _x3 <='0 ' / s4_ _i <=(ΟΊ 'HERS => 1 〇') / s4_ _〇 <=(OTHERS => 1 〇丨) / ELSIF clk32m 'EVENT AND clk32m ='1 'THEN s4_ _i <=input_4, r s4_ _xl <=s4 i(〇) X〇R s4 一 _i(2) XOR s4__i(3) X〇R s4 一 _xl XOR s4_x3; s4_ x2 <=s4二i (1) X〇R s4 一 _i(3) XOR s4__xl X〇R S4 一 _x2 XOR s4_x3; s4_ _x3 <=s4 i(2) X〇R s4 一 _xl XOR s4_x2; s4_ _〇(0) <=s4 一 i(〇) X〇R s4 一 .i(l) XOR s4_i(2) X〇R s4_ i(3) XOR S4_x3; s4_ _〇(l) <=s4 一 i(l) X〇R s4 一 .i (2> XOR s4_i(3) X〇R s4_ _xl XOR s4_x3; s4_ _〇(2) <=s4 一 i(2) X〇R s4 一 _i(3) XOR s4__xl X〇R s4_ _x2 X〇Rs4—x3; s4 一〇(3) <=S4_ 一丄⑶ X〇R s4_ _xl XOR s4_x2; — — — — — —---裝·!ί 丨!訂-----I-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 END IF; END PROCESS tc_4; output—4 <= s4__o ; 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 474068 A7 B7 五、發明說明(39) tc一8: PROCESS (clk32m, reset—p) -- 8bit parallel building of turbo coder blockIF reset a p = say 1, THEN -40-This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) Please read the note on the back h Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474068 A7 B7 V. Description of the invention (38) s4_ _xl < = '0 1 / s4_ _x2 < = 1 0' / s4_ _x3 < = '0' / s4_ _i < = (ΟΊ 'HERS = > 1 〇' ) / s4_ _〇 < = (OTHERS = > 1 〇 丨) / ELSIF clk32m 'EVENT AND clk32m =' 1 'THEN s4_ _i < = input_4, r s4_ _xl < = s4 i (〇) X〇R s4 one_i (2) XOR s4__i (3) X〇R s4 one_xl XOR s4_x3; s4_ x2 < = s4 two i (1) X〇R s4 one_i (3) XOR s4__xl X〇R S4 one _x2 XOR s4_x3; s4_ _x3 < = s4 i (2) X〇R s4 a_xl XOR s4_x2; s4_ _〇 (0) < = s4 a i (〇) X〇R s4 a.i (l) XOR s4_i (2) X〇R s4_ i (3) XOR S4_x3; s4_ _〇 (l) < = s4 -i (l) X〇R s4 a.i (2 > XOR s4_i (3) X〇R s4_ _xl XOR s4_x3; s4_ _〇 (2) < = s4 -i (2) X〇R s4 -_i (3) XOR s4__xl X〇R s4_ _x2 X〇Rs4-x3; s4 one〇 (3) < = S4_一 丄 ⑶ X〇R s4_ _xl XOR s4_x2; — — — — — — ——— 装 ·! Ί 丨! Order ----- I-- (Please read the notes on the back before filling this page) Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Consumption Cooperative END IF; END PROCESS tc_4; output—4 < = s4__o; This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Printed 474068 A7 B7 V. Description of the invention (39) tc-8: PROCESS (clk32m, reset—p)-8bit parallel building of turbo coder block
BEGINBEGIN
IF reset—p = '11 THEN S8- 一 xl <='0'; s8· _x2 <='0'; s8_ —x3 <=,01; s8_ 一i <=(OTHERS => 101); s8_ <=(OTHERS => ,01); ELSIF clk32m'EVENT AND clk32m = ' 1 1 THEN s8_i <= input_8; s8一xl <= s8_i(0) XOR s8__i(2) X〇R s8_i(3) X〇R s8_i(4) XOR s8__i(7) XOR s8_x2 XOR s8_x3; s8—x2 <= s8_i(1) XOR s8_i(3) XOR s8_i(4) XOR s8_i(5)*XOR s8_xl; s8—x3 <= s8_i(2) XOR s8_i(4) XOR s8_i(5) XOR s8_i(6) XOR s8__x2; _ s8_o(0) <= s8_i(0) XOR s8__i(l) XOR s8_i(2) XOR s8_i(3) XOR s8_i(6) XOR s8 xl XOR s8 x2; -42- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) — I — I 丨 — — — — — 丨^^ · !丨 — ! —訂. (請先閱讀背面之注意事項再填寫本頁) 474068 A7 B7 五、發明說明(40) s8 〇(1) s8_o(2) s8_o(3) s8_〇 (4) s8—〇(5) s8一。(6) s8 〇(7) s8—i(l) X〇R s8_ X〇R s8-XOR s8_ s8—i(2) XOR s8_ X〇R s8_ s8—i(3) XOR s8_ XOR s8 广 s8—i(4) XOR s8· XOR s8_ s8—i(5) XOR s8 XOR s.8 s8—i(6) XOR s8 XOR s8 s8 i (7) XOR s8 _i (2) XOR s8_i(3) _i (4) XOR s8—i (7) x2 X〇R s8—x3; _i (3) XOR s8__i(4) _i(5) XOR s8_xl; _i(4) XOR s8—i(5) _i(6) XOR s8_x2; _i (5) XOR s8—i(6) _i(7) XOR s8一x3; __i (6) XOR s8_i (7) __xl XOR s8__x3; _i(7) XOR s8一xl _x2 XOR s8_x3; xl XOR s8 x2; ------------裝--- (請先閱讀背面之注意事項再填寫本頁) . END IF; END PROCESS tc__8 ; output___8 <= s8_〇; END rtl; 5. 加速編碼器實現 雖然本發明相關背景技藝已經參考圖8,但是此圖8將 與本發明有關,將在下文顯示。 如目前爲止説明之本發明,.已經參考具有Μ個輸出之加 -43- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) #- 經濟部智慧財產局員工消費合作社印製 8 6 ο 4 A7 B7 玉 經濟部智慧財產局員工消費合作社印製 發明說明(41 ) 速編碼斋方塊之平行化。然而,必彡g '、敌到如本發明,穿替 加速編碼器之結構需要平行化加迷編碼器方塊啓動二次, 如圖8所示(其中二方塊假設Μ = 1)。 -加速編碼器方塊與正常輸入資料流有關以導出圖"g 示之0_T i以及另一加速編碼器方塊與插入之輸入资 料流有關以導出OUTPUT 2。由於輸入資料流亦直接轉送 至OUTPUT 0,所以加速编碼器之三輸出每平行時鐘循環 具有3n個位元之寬度,其中n爲平行化度數。 1 44 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)IF reset—p = '11 THEN S8- one xl < = '0'; s8 · _x2 < = '0'; s8_ —x3 < =, 01; s8_ one i < = (OTHERS = > 101 ); s8_ < = (OTHERS = >,01); ELSIF clk32m'EVENT AND clk32m = '1 1 THEN s8_i < = input_8; s8-xl < = s8_i (0) XOR s8__i (2) X〇R s8_i (3) X〇R s8_i (4) XOR s8__i (7) XOR s8_x2 XOR s8_x3; s8—x2 < = s8_i (1) XOR s8_i (3) XOR s8_i (4) XOR s8_i (5) * l s8—x3 < = s8_i (2) XOR s8_i (4) XOR s8_i (5) XOR s8_i (6) XOR s8__x2; _ s8_o (0) < = s8_i (0) XOR s8__i (l) XOR s8_ XOR s8_i (3) XOR s8_i (6) XOR s8 xl XOR s8 x2; -42- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) — I — I 丨 — — — — — 丨^^ ·! 丨 —! —Order. (Please read the notes on the back before filling this page) 474068 A7 B7 V. Description of the invention (40) s8 〇 (1) s8_o (2) s8_o (3) s8_〇 ( 4) s8-0 (5) s8-1. (6) s8 〇 (7) s8—i (l) X〇R s8_ X〇R s8-XOR s8_ s8—i (2) XOR s8_ X〇R s8_ s8—i (3) XOR s8_ XOR s8 wide s8— i (4) XOR s8 · XOR s8_ s8—i (5) XOR s8 XOR s.8 s8—i (6) XOR s8 XOR s8 s8 i (7) XOR s8 _i (2) XOR s8_i (3) _i (4 ) XOR s8—i (7) x2 X〇R s8—x3; _i (3) XOR s8__i (4) _i (5) XOR s8_xl; _i (4) XOR s8—i (5) _i (6) XOR s8_x2; _i (5) XOR s8—i (6) _i (7) XOR s8_x3; __i (6) XOR s8_i (7) __xl XOR s8__x3; _i (7) XOR s8_xl _x2 XOR s8_x3; xl XOR s8 ------------ Install --- (Please read the precautions on the back before filling this page). END IF; END PROCESS tc__8; output___8 < = s8_〇; END rtl; 5. Accelerated encoder implementation Although the background art related to the present invention has been referred to FIG. 8, this FIG. 8 will be related to the present invention and will be shown below. As for the present invention explained so far, the reference has been added with M outputs -43- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) #-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System 8 6 ο 4 A7 B7 Jade Economy Ministry Intellectual Property Bureau employee consumer cooperatives printed invention description (41) Parallelization of fast-coded fasting box. However, as the present invention must meet the requirements of the present invention, the structure of the accelerated acceleration encoder needs to be parallelized and the encoder block is activated twice, as shown in FIG. 8 (where two blocks assume M = 1). -The accelerated encoder block is related to the normal input data stream to derive 0_T i shown in the figure " g and another accelerated encoder block is related to the inserted input data stream to derive OUTPUT 2. Since the input data stream is also directly transferred to OUTPUT 0, the third output of the accelerated encoder has a width of 3n bits per parallel clock cycle, where n is the degree of parallelization. 1 44 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
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EP99117945A EP1085660A1 (en) | 1999-09-15 | 1999-09-15 | Parallel turbo coder implementation |
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EP (2) | EP1085660A1 (en) |
JP (1) | JP4713039B2 (en) |
KR (1) | KR20020035595A (en) |
CN (1) | CN1196268C (en) |
AR (1) | AR025674A1 (en) |
AT (1) | ATE263454T1 (en) |
AU (1) | AU6842800A (en) |
DE (1) | DE60009531T2 (en) |
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US7315579B2 (en) * | 2001-02-28 | 2008-01-01 | Broadcom Corporation | Trellis coded modulation tails |
US6980820B2 (en) | 2001-08-20 | 2005-12-27 | Qualcomm Inc. | Method and system for signaling in broadcast communication system |
US6731936B2 (en) | 2001-08-20 | 2004-05-04 | Qualcomm Incorporated | Method and system for a handoff in a broadcast communication system |
US6701482B2 (en) * | 2001-09-20 | 2004-03-02 | Qualcomm Incorporated | Method and apparatus for coding bits of data in parallel |
US6948109B2 (en) * | 2001-10-24 | 2005-09-20 | Vitesse Semiconductor Corporation | Low-density parity check forward error correction |
US6954885B2 (en) * | 2001-12-14 | 2005-10-11 | Qualcomm Incorporated | Method and apparatus for coding bits of data in parallel |
FR2853164A1 (en) * | 2003-03-31 | 2004-10-01 | France Telecom | Error correcting encoding process for digital communication, involves defining code word such that two sections of elementary code are distinct even when order and/or role of vectors of vector label are modified |
US7912485B2 (en) | 2003-09-11 | 2011-03-22 | Qualcomm Incorporated | Method and system for signaling in broadcast communication system |
US8570880B2 (en) | 2004-08-05 | 2013-10-29 | Qualcomm Incorporated | Method and apparatus for receiving broadcast in a wireless multiple-access communications system |
EP1880473A2 (en) * | 2005-01-14 | 2008-01-23 | Nxp B.V. | Channel encoding with two tables containing two sub-systems of a z system |
US8620900B2 (en) * | 2009-02-09 | 2013-12-31 | The Hong Kong Polytechnic University | Method for using dual indices to support query expansion, relevance/non-relevance models, blind/relevance feedback and an intelligent search interface |
US8583993B2 (en) * | 2011-06-17 | 2013-11-12 | Lsi Corporation | Turbo parallel concatenated convolutional code implementation on multiple-issue processor cores |
KR101286019B1 (en) * | 2012-01-20 | 2013-07-19 | 주식회사 이노와이어리스 | Turbo encoder apparatus |
EP2693673A1 (en) * | 2012-08-01 | 2014-02-05 | Alcatel Lucent | Bit-interleaver for an optical line terminal |
US9281846B2 (en) | 2013-07-31 | 2016-03-08 | Globalfoundries Inc | Turbo encoding on a parallel processor |
EP2899991A1 (en) * | 2014-01-24 | 2015-07-29 | Alcatel Lucent | Space time switch and bit interleaver |
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JPS61214623A (en) * | 1985-03-20 | 1986-09-24 | Fujitsu Ltd | Convolution encoding circuit |
JPH07253895A (en) * | 1994-03-14 | 1995-10-03 | Sony Corp | High-speed subtracter by plural bit simultaneous arithmetic operation |
FI100565B (en) * | 1996-01-12 | 1997-12-31 | Nokia Mobile Phones Ltd | Communication method and apparatus for encoding a signal |
US6023783A (en) * | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
KR19990012821A (en) * | 1997-07-31 | 1999-02-25 | 홍성용 | Electromagnetic wave absorber composition and its manufacturing method, electromagnetic wave absorbing coating composition, its manufacturing method and its coating method |
BR9906479B1 (en) * | 1998-06-05 | 2013-01-22 | channel coding device, and, channel coding process. | |
AU731794B2 (en) * | 1998-08-20 | 2001-04-05 | Samsung Electronics Co., Ltd. | Device and method for inserting previously known bits in input stage of channel encoder |
JP2000114986A (en) * | 1998-10-08 | 2000-04-21 | Oki Electric Ind Co Ltd | Encoding method and device |
US6366624B1 (en) * | 1998-11-30 | 2002-04-02 | Ericsson Inc. | Systems and methods for receiving a modulated signal containing encoded and unencoded bits using multi-pass demodulation |
US6304991B1 (en) * | 1998-12-04 | 2001-10-16 | Qualcomm Incorporated | Turbo code interleaver using linear congruential sequence |
-
1999
- 1999-09-15 EP EP99117945A patent/EP1085660A1/en not_active Withdrawn
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2000
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- 2000-09-04 WO PCT/EP2000/008631 patent/WO2001020787A1/en not_active Application Discontinuation
- 2000-09-04 JP JP2001524245A patent/JP4713039B2/en not_active Expired - Lifetime
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JP2003509943A (en) | 2003-03-11 |
AU6842800A (en) | 2001-04-17 |
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WO2001020787A1 (en) | 2001-03-22 |
AR025674A1 (en) | 2002-12-11 |
CN1390391A (en) | 2003-01-08 |
EP1221200A1 (en) | 2002-07-10 |
DE60009531T2 (en) | 2005-03-03 |
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US6651209B1 (en) | 2003-11-18 |
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