TW474068B - Parallel turbo coder implementation - Google Patents

Abstract

In order to achieve a turbo coder block having an increased processing speed it is proposed to carry out a parallelization of degree n. As a result each parallelized turbo coder block comprises a storage unit (I0, ..., I7) to store n samples (I(t-1), ..., I(t-n)) of an input signal I(t) to the parallelized turbo coding block and at least one storage unit (Q0, ..., Q7) to store n samples (Qj(t), ..., Qj(t-(n-1)) of at least one output signal Qj(t) (j=1, ..., M) of the parallelized turbo coding block. Further, the parallelized turbo coder block comprises a bank of n delay units (X1, ..., XN) and is adapted to a parallel processing of n samples of the input signal I(t) such that at least two delay units (X1, ..., XN) of the bank directly receive subsets of the n samples (I(t-1), ..., I(t-n)) of the input signal I(t) and an output signal of at least one delay unit (X1, ..., XN) in the parallelized turbo coder block is supplied to at least two delay units in the parallelized turbo coder block.

Description

474068

DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the implementation of accelerated encoders, and in particular the present invention relates to the parallelization of the implementation of accelerated encoders. BACKGROUND OF THE INVENTION The baseband portion of a transmitter of a telecommunication communication system is often Encoding and other points. The encoder adds synthetic information to the incoming data stream with a bit size K. Therefore, the number of bits is increased by a factor of 1 / r 'and is related to the encoder rate r. Currently, 1/2 and 1/3 of the encoder rate is common, although other rates are also possible. As a result, for each block of κ uncoded bits, the encoder outputs a block of K / r coded bits. In telecommunications systems On the data stream receiving side, the original data stream is recalculated by the receiver's coded data blocks, even if some bits become corrupted during transmission over, for example, the air interface. Recently, the encoder has been accelerated for the purpose of error control of telecommunications data transmission It has already been adopted. Generally, accelerated coding involves applying at least two component codes to different inserted versions of the same information sequence before transmission. Known to accelerate encoding, for example, in May 1993 IEEE International Conference on Communications, pp. 1064-1070 Berrou and others of '' Near Shannon Limit Error -

Correcting Coder and Decoder: Turbo-Codes 丨 'and _ December 1997, IEEE Communications Magazine, pages 94-102 of Sklar "A Primer on Turbo Code Concepts' 丨", further details and statements are not provided here. This article is mentioned here in the manner described in this article. An example of an accelerated encoder is shown in Fig. 8. As shown in Fig. 8, the accelerated encoder includes two equal-speed acceleration / speed encoder blocks TCB 1, TCB2- 4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) 装 # Printed by the Ministry of Economic Affairs Intellectual Property Bureau Employee Consumption Cooperative

V. Description of Invention (2) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The second acceleration encoder is Fang Jizhi; PI A, Wan Xianzhi regardless of which one of the blocks receives the input block bits in an unaltered order, and the other _ 'Χάί ... — 10,000 blocks receive the input bits in the insertion order. For each input bit, for example, 认 1, 认, and J, such as 3 output bits are generated on outputs 0, 1, and 2, respectively. As shown in FIG. 8, the acceleration encoder side% T (: βι includes the XOR gate 100 at its input and the second x〇r 102 at its output. There are 3 delays configured between them. Single ^ 1G4 i⑽ for the extension of individual input bits. Similarly, the acceleration encoder block CB2 includes the first XOR gate 1 1 0 at its input and the fourth x 〇R gate 1 at its output. 12. There are three delay units 114 to 118 providing individual continuation bits between the delays. As also shown in FIG. 8, the input signal of the acceleration encoder is directly supplied to the acceleration encoder block 1 and is supplied to The second acceleration encoder block TCB2. For output 0, the input signal is also directly transmitted without any modification. Operationally, the acceleration encoder parameters shown in FIG. 8 are each acceleration encoding as the number of block delay units and other inputs. The signals are supplied to different XOR gates 100, 102, 110, and 112. The acceleration encoder shown in Figure 8 directly implements the use of the delay unit and the input and output registers (not shown in Figure 8). Bit-wise completion. Here, all The delay unit works with the same system clock 'so the output of the delay unit therefore represents the input of the previous clock cycle. Although the direct implementation of the acceleration encoder using the delay unit in series does not require many registers and XOR gates, the main disadvantage is acceleration The encoding is performed in tandem. This means that only one bit is encoded per system clock cycle. -5- This paper size applies to China ^^ standard (cns) a4 specifications (210 x 297 male (please read the precautions on the back and the (Fill in this page) 1 ·: Packing 474068

"The conclusion of the clock frequency of the Hai system is that it will increase to a very high level for cases that require a high bit rate. Examples such as 1200 channels will be right, — ~" 1 second time period with a 100-bit voice channel correlation It requires 1 'clock frequency to be 120 Mhz. Ding X, Wu Ma Here, it will be very difficult to implement related acceleration encoders or F P G A technology. For example, using ASIC-Printed by the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives, although—the answer will be to implement a dedicated acceleration encoder for each channel, but this method will require complex processing of the input and output bit streams, as different channels must still be parallel coding. This situation will lead to very complex control logic supplying the correct input to the correct acceleration encoder at the right time. u, the output of different capture encoders will also have to be processed in the same complex way. Summary of the Invention As mentioned above, the purpose of the present invention is to increase the processing speed of the accelerated encoder block. -Dagger According to the present invention, this object is achieved in parallel via an accelerated encoder. So far, the accelerated encoder block structure was initially described as a generalized formal description of the accelerated encoder block parallelization benchmark after use. Λ In particular, the accelerated encoder block input samples are interpreted as n-dimensional parallel input vector elements, where η is the degree of parallelization. The generalized description of the accelerated encoder block is then used to derive the mapping of this parallel input vector to at least one output vector. In more detail, the internal state variable substitution process is applied to each internal state variable of the general formal description, where the internal state variable is represented as 474068

V. Description of the invention (4) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 :: The element is scanned and the element is replaced by the backward time index by using the internal state. These alternative steps are repeated until the table of each internal state variable is not only related to the acceleration encoder input vector elements and the internal state variable 値 which are delayed according to the degree of parallelization. In addition, 3 replacement processing is also performed for each element of each parallel output vector. Again, each vector element of each output vector is represented as having the largest time index (the scan of the internal Shao state variable and then the vector element representation is then converted to the time index to be determined recursively until the vector element representation is only delayed by the degree of parallelization according to the degree of parallelization The internal state variables are not related. Therefore, as the present invention proposes to parallelize the acceleration encoder block, only one parallel acceleration encoder block is needed instead of most serial acceleration encoders to achieve increased processing speed. This situation guides The decisive advantage of the complex acceleration encoder blocks that do not require complex input and output control. For example, for a unit-bit parallel acceleration encoder block, "the system time frequency formed by the example mentioned above is in the range of 30 MHz Therefore, it can be easily implemented using FPGA or ASIC technology. Therefore, the parallel acceleration encoder block and the derived acceleration encoder achieve the increase speed over the serial acceleration encoder according to the degree of parallelization, so it is defined in advance The specifications can be implemented using FPGA or ASIC technology benchmarks. Because: The parallel acceleration encoder block can form the basis of a complex communication system with a low processing delay in the fundamental frequency section without the complex processing of different channels at the same time. 夂 Also, when accelerating encoding with serial When comparing the encoders, the parallel acceleration encoding ---- I ---- 丨 丨 丨 installed ------- order --I ------ * ^ ιρ · (Please read the Note: Please fill in this page again) 7- 474068 No. 89117076 Patent Application Chinese Specification Revision Page (September 1990) A7 B7

Fifth, the invention description (5) The encoder block and the related acceleration encoder only need the minimum additional surplus of the logic gate and the register. In addition, when the processing blocks before and after the accelerated encoder also support parallel processing, the complete encoder block requires less logic overall (parallel to serial, and vice versa) than an encoder block with a serial accelerated encoder and some additional converters. And so on). Hold

According to another specific embodiment of the present invention, a computer-readable storage medium is also provided, including software code portions for performing the steps of the inventive parallelization method when executed on a computer. Preferably, the software code portion is a VHDL type. Therefore, the present invention allows to reduce the number of development cycles and increase the flexibility by mapping to different hardware technologies such as ASIC or FPOA to reach the benchmark for rapid development and modification of parallel accelerated encoder design, respectively. Brief description of the drawings In the following, preferred embodiments of the present invention will be described with reference to the drawings, in which:

Figure 1 shows a block circuit diagram of an accelerated encoder with one output; Figure 2 shows a block circuit diagram of an accelerated encoder with multiple outputs; Figure 3 shows the mapping of data input time sequence to parallel input vectors and parallel output vector to data output time Sequence flow mapping; Figure 4 shows the circuit diagram of 7JT specific accelerated coding block implementation in series, Figure 5 shows the circuit diagram of the two-bit parallel implementation of the accelerated encoder block shown in Figure 4; Figure 6 shows the accelerated encoder shown in Figure 4 Square four-bit implementation in parallel -8- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 474068 A7 B7 V. Description of the invention (6 Circuit diagram; ----------- Shang · 丨 1 (Please read the precautions on the back before filling this page} Figure 7A shows the circuit diagram of the input part of the 8-bit parallel implementation of the accelerated encoder block shown in Figure 4; only Figure 7B shows the accelerated encoder shown in Figure 4 A block diagram of the input and output circuits implemented in parallel with the blocks; and Fig. 8 shows a schematic diagram of the accelerated encoder including the inserter and the accelerated coding block 1 and the block diagram. The preferred embodiments will be described with reference to Figs. 1 to 7. In particular, the formal description of the acceleration encoder block shown initially in Figs. 1 and 2 will be formalized as a description of the parallelization method of the present invention. After the benchmark, we will explain how the time-sequence stream of data input can be mapped to the parallel input vector for processing in the parallel acceleration encoder block with reference to FIG. 3 and how the parallel output vector of this parallel acceleration encoder block can be mapped to the data again. The output is a time-sequential stream. The following different examples of parallel implementation of the accelerated encoder block using the parallelization method of the present invention will be given with reference to Figures 4 to 7. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 1 · Has Accelerated encoder square building implemented in series and general description: Figure 1 shows the block circuit diagram of the accelerated encoder using serial implementation. As shown in Figure 1, the accelerated encoder block includes N delay units, X1 X2, ... , XN, such as flip-flops. The delay units X 丨, χ2, ··· ^ The output signals will be regarded as Xl⑴, χ2⑴, ..., χν⑴, respectively, where t represents Integer time index. Input x〇R gate 12 is provided on the input of the first delay unit X and -9-this paper size is applicable to the family standard (CNS) A4 specification (210 X 297 public love) 474068 A7 V. Description of the invention (7) The last delay unit X—the output is provided between x0r ... As shown in FIG. 1, the input signal I (t

And the output XOR gate is 14 rounds, and the V_ output is frightened, and Λ is forwarded by the output delay unit 18 < not shown in Figure 1, the output signal ⑴, the hitting suppression 2⑴, ..., ~ ⑴ It can be supplied to the input gate 12 via a connection, a2, · .., ~. The input signal can also be input via the connector ρ〇, sooner or later. In addition, the delay unit outputs to the output XOR gate 14. °. h is supplied to 连接 〇 or 丨 to each connector αι by formal designation, and it is deducted to each connection P β〇, β!, ..., βΝ, which may be as follows—day N X and any series of delay units Speed up encoder block implementation: month has h

Xl (t) = ： 工 (t-1) ㊉ arXjL (t-1) © α2 · χ2 (tl) ㊉ ··· Dye aN, (t, i), ai ε {〇, 1} (1 · χ1) X2 (t) = χχ (t-1) (1 · X2) 111! 11111 t! 1_ (Please read the notes on the back before filling out this page) # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy = XN -l (tl) (1 · XN) 10 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 47406s A7 B7

V. Description of the invention (8) Dagger) = 0. [Gong (Dagger-1) (arxi (Buddy) ㊉ a2.X2 (Bu1) ㊉ ··· ㊉ aN-xN (t: -i)] ㊉ βγχ ! (tl) ㊉ β2 · χ2 (t-1) ㊉ ··· ㊉ = β〇 · 工 (t-1) ㊉ βο.α ^ α-Ι) ㊉ βΐ · χ1 (ί: -1) ㊉ P〇 , XN (tl) ㊉ PM.XNk-1) β〇 · 工 (t-1) ㊉ Χ] _ (ί: -1) · [β〇 · (Χι ㊉ βι) ㊉ (t -1) · [Pq 'CCn ㊉ Pn] ε {〇, 1} Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Suiji L --- 1 -------- * «r --- (Please read the precautions on the back before (Fill in this page) dQ) As shown in Figure 2, the accelerated encoder block with a single output can be summarized as an accelerated encoder block with serial implementation and a complex output. Figure 1 and Figure 2 show the delay and delay units Xi, X2 ..., χΝ output letter-11 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4 ^ 4068 A7 Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative prints and invents the description number again as Xl⑴, x2 (t), ..., xN⑴. Each delay unit X1, X2, ..., XN output signals X | (t), & ⑴, ..., χΝ⑴ have shown in FIG. I that they are supplied to the input XOR gate via the connectors α !, α2, ..., αN 12. Also, the input data stream is supplied to the input x〇r gate 12 via the delay unit 16. The difference between the accelerated encoder block shown in Fig. 2 and the previously discussed accelerated encoder block is that a plurality of outputs Ql (t), ..., QM (t) are provided. As shown in Fig. 2, each output provides related outputs x〇R gates 14_ 丨, ..., 14_M. On the outputs of the respective output XOR gates 14-1, ..., 14-M, there are associated output delay units 18-1, ..., 18-M. It is also shown in Fig. 2 that the inputs of the delay units X 丨, x2 ..., XΝ can be supplied to the first output gate via the connectors βΜ, β 丨, 丨, β 丨 2, · .., PΐN • 丨; · I;: and further supply via connectors β2, "2, I, β2, 2, ..., k, etc. = two exit gates 14-2, etc. In addition 'the last delay order is supplied to the first output gate 14], By connecting f to the spear-output idle 14.2, etc. Finally, 'the output number of each output XOR is delayed to lead A to speed up the encoding of the block when the encoding is delayed, 8 Formal description of the accelerated encoder shown in Figure 2 ^' The differences between Qm in each round Ψ η ", ^,", the first four theories, '卩 1 (), ..., QM⑴'s related expressions are summarized as: (t) = Pjo · 工 （ti) ㊉ ㊉ pjl; | ㊉ —! 11111 ^^ t — 11111 e 1111! * 1 ^ 1 ^. {Please read the notes on the back before filling this page)

474068 A7 B7 V. Description of the invention (deduction pij ε {〇, 1} j ε [! '· · · · Μ], (lQ) Accelerated encoder block implemented in series The above formal table will then be used as a complex output The description of the parallelization method of the present invention is two-way. However, the parallelization method of the present invention will be described below: half. The mapping of the initial serial data input stream to the parallel input vector and the parallel :: back to back The mapping of the serial data input stream will be explained with reference to Fig. 3. To the acceleration encoder block implemented in parallel using degree n: On the upper left side, Fig. 3 shows the time sequence of the serial data input stream. Figure 3 shows the time sequence of the serial output stream in the upper right part = 〇 As shown in Figure 3, the parallel output vector ι〇, η, Ιη-1 can be output from a series of data 値 I (tl) 5 I ( t-2), ..., I (tn) is derived as follows: I (tl) = 10 (p_l) I (t-2) = II (p-1) ··· equipment -------- order- -------- rtt first read the notes on the back before filling in this page, ># Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (tn) = In-1 (p-1) By string Export of parallel input vector data input stream -13- This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) 474 068

Known as one of the accelerated encoding parallel output vectors 下文 ... 'Bu ^ processing' one of them arrives as shown in Figure 3 'This parallel input serial data output stream _, ..., coffee (1 ^: 了 ~ the following formula Maps back to

Qj (t) Qj (t-1)

Qj ° (p) QjUp)

Qj (t- (nl)) = Qjn-i (-p) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 · 1 The general depiction of parallelism is as in the present invention纟 The serial time domain and the parallel time domain have different time scales. It says that the group of n serial data inputs of the 'serial time domain' is equivalent to the parallel input direction according to the parallel time domain P-clock cycle parallel processing. " 5 * 〇 The conclusion is that the parallel system clock formed is η times slower than the serial system clock, assuming that the same amount of data will be processed. Therefore, the serial time formula 仏 1) can be replaced by the parallel time formula (ρ-1) and a series of η series time inputs can be rewritten as a single parallel input vector, which is earlier than one parallel clock cycle of (ρ-1). Similarly, the output of this sequence is rewritten as the parallel output of the current parallel cycle (ρ). Use the accelerated coding as shown in Figure 1 and Figure 2. General description of the encoder block and _ Qiao -14 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)-installed ------ --- Order ---------. 474068 A7 V. Description of the invention (12 1 Staff fee: Mapping of serial data input stream to parallel input vector and reverse of flat vector to serial output data stream Mapping, according to the present invention, depends on the supply of parallel input vectors with η serial data input items = row acceleration encoder blocks and calculations that each include a "solid output data item ^ output vector." Η of the output vector Elements and the internal delay unit are only implemented in the early serial acceleration encoder blocks. The n system clocks are related to the internal delay unit χν < 値-equivalent to only one cycle of the parallel acceleration encoder block-and in addition to parallel input Vector integration is related to the data entry items during these n cycles. As will be shown below, the way under the present invention relies on the output elements representing the parallel output vector and the internal delay sheet with the parallel acceleration encoder block = input It is related to the parallel input vector of the previous parallel loop, and the next one is equal. The parallel acceleration encoder block "internal delay unit output" is determined by the equation. As shown in the series (refer to equation (1.Q)), in The implementation of accelerating encoder blocks at time t is calculated by the delay unit χΐ at the time bu, the output 値, and the input data items at time N1. The internal clock cycle of the system implemented in the earlier series replaces the internal Delay, repeat all output steps, and repeat these replacement steps recursively until there are previous n serial system clock output loops left, which can have n queue cycles or equivalent to a parallel cycle The output results of the parallel calculation of the derived equations. In other words, see 'These equations will parallelize the benchmark of the accelerated encoder block.

Xr ends with Μ (_____ · 15 _ this paper size is suitable for financial and family standard boots NS) A4 specifications ⑽ 474068

Became two n serial clock cycles after representing a parallel clock cycle 2nd-2nd internal state. (Please read the notes on the back before filling in this page) # ^ μ 、 _ Manxiang time index instead: When mentioned in the preparation and returning the charge, the first delay can be used as early as 70 Χ 丨The output representation (comparative equation (1.χι)) X1 (dagger) = I (tl) _ ㊉ cti.Xi (dagger-ι) ㊉

Ct2 * X2 (t-1) ㊉ ·· .㊉ aN * xN (t -1) is also regarded as the first--the internal state is represented by the serial clock cycle t-1, ..., t- ( nl) of this internal miscellaneous ...

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs xi (t :-( ni)) = i (t: -n) ㊉ ai.Xi (t_n) ㊉ α2 · χ2 (dagger-n) ㊉ ·· .㊉ aN * xN (t ~ π) (2 · Father1 · η-l) -16- _ This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) 474068 A7 V. Description of the invention (14), 3 The other internal states are then replaced by time index # 7 丨 (1 = 2 χτχ In addition, other delay units X, γ,, ..., N): 2 '··' 'χν <output representation (refer to equation (1 · Χ2), ..., (1 · χΝ))

Xi⑴

Xi -1 (t-1) is also considered hereinafter as other internal states such as t-υη-υ these internal states: formula table, clock cycle.

Xi (t-l) xi-l (t — 2) (2-Xi · 1)

Xj [(t- (nl)) = xi-i (tn) (2. The Intellectual Property Bureau of the Ministry of Economic Affairs ’Employee Consumer Cooperatives printed 2.4 output vector elements and replaced them with time indexes: In addition, at least one output of the accelerated encoder block Representation (comparison equation (1.Q)) Qj (t) = β ″ 0 · 工 (tl) ㊉ —… x; L (tl) · [Pjo.ajL ㊉ pjj ㊉ XN (Bu 1) · [h 〇 · ΑΝ ㊉ PjN;] (2.Q.0) ^ ^ -------- ^ --------- (Please read the notes on the back before filling this page) _ -17- 'The paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 474068 A7 B7 V. Description of the invention (15) The following formula can be used to represent the serial clock cycle t-1, ..., t- (nl) This output: Please read the notes on the back first

Qj (t-i) = Pj〇.I (t-2) ㊉ ㊉ 以 工] ㊉ xN (t-2) · [β ″ 〇.αΝ ㊉ β ″ N] (2.Q.1)

Qj (t- (η-1)) β ″ 〇 工 (t-n) ㊉

Xi (tn). [Pj〇.cti ㊉ β ″ ι] ㊉ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy XN (t-η) · [β "〇 · (% ㊉ pjN) (2.Qn-l) -18 The size of this paper applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 Printed by the Consumer Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (16) 2 * 5 The parallelization of the index conversion step: 2.5.1 The purpose has been described as above. The purpose under the parallelization process of the present invention is to represent the elements of each parallel output vector-each output shown in Fig. 2, ..., elements-is A series of n_column data input streams and a function of the internal state of a parallel loop-equivalent to n serial loops-before the current parallel loop:

Qj (ti) = ..., I (tn); x ^ tn) ..... XN (tn)] f〇ri ε [0, ·· ,, n-1] j ε [1, ..., M]

Qji (P) = f [I〇 (pl), ..., In-1 (pi); ..., XN (ρ-1)] · (2.Qi) 2.5.2 Recursive time index conversion step is first All internal states of this target are parallelized. For all internal states Xi (t),…, χΝ ，, the large time index used in this internal state representation is initially set to t · 1 according to a series of operating instructions. All subsequent internal states are expressed as a consideration and each state is a recursive scan to be replaced by an equation representing the same internal state related to the time index before this current maximum time index using one of the equations (2) listed above Internal state variables related to the current maximum time index. Therefore, the internal state of the consideration is expressed by the conversion method from the current maximum time index to the time before the current maximum time index. -19-This paper standard applies the Chinese National Standard (CNS) A4 specification (21〇x). 297 mm) • I — 丨 丨 —! 111 · — 丨 丨 丨 — 丨 —Order- 丨-I- (Please read the notes on the back before filling this page) 474068 A7

Read the precautions on the back before I fill in this page 4 474068 A7 B7 V. Description of the invention (18) while (tmax &gt; tn) (Please read the precautions on the back before filling in this page) {scan representation of internal state X ] ^ (t) for internal states with maximum time index tmax; · for (all internal states with maximum time index) {execute backward time index transition from tmax to tmax-l through state variable substitution using .eq. (2) above; } cancel double terms in representation of internal state xj ^ (t); tmax = tmax-l;}} / * parallelization of output variables * / printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs for (j = l; j &lt; = M; j ++) {for (i = 0; i &lt; = n-2; i + +) {/ * consider output vector element Qj (ti) * / -21-This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 474068 A7 B7 V. Description of the invention (19) tmax = til; while (tmax &gt; tn) {scan representation of Qj (ti) for internal states with maximum time index; for (all int ernal states with maximum time index) {execute backward time index transition from tmax to t max '1 through state variable substitution using eq. (2) above; cancel double terms in representation of Qj (ti); one max -max &quot; (please (Please read the notes on the back before filling out this page) (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs) / * end procedure * / To explain the application of the parallelization method generally described above, in the following, this parallelization process will be referred to Specific examples are explained in detail. As will be shown below, each parallelized acceleration encoder block includes a storage unit, such as a first group of flip-flops 10, ..., 17 to store n samples I (t-1) of the input signal I (t), ..., I (tn) is supplied to the parallel acceleration encoder block-22- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 474068 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Explanation (20) and at least one storage unit, such as a second group of flip-flops Q 0,..., Q 7 to store at least one output signal Qj (t), j 2 1, ... Η samples of M Qj (t), ..., Qj (t &gt; (nl)). In addition, the "accelerated coding state device includes a delay cell library of n delay cells (x 丨, ..., XN) and parallel processing of n samples adapted to the input signal I (t)", such as a 3 delay early cell library (Xι, ... , ΧΝ) at least two delay units directly receive a subset of n samples (I (N1),, I (tn)) of the input signal I⑴ and at least one delay unit (Xι, ..., 乂 "of the acceleration encoder device The output signal is supplied to at least two delay units of the acceleration encoder device. Fig. 4 shows a block circuit diagram of a specific string g acceleration encoder, which can be used in the acceleration encoder shown in Fig. 8. Here 'we must pay attention to the input delay unit 16 and The output delay unit 18 itself does not have the necessary conditions of the serial execution case, but in the parallelization case it becomes necessary to collect the elements of the input vector and the output vector as shown in Figure 3. The serial acceleration encoder shown in Figure 4 Blocks can be formalized using equation (1) as described above with N = 3, M = i, α = [αι, ^, called = [0, 1 ,, 1] 'β = [β 丨, β2, β3, ρ4] = π, h 〇, i] In the next section, we will explain how this serial acceleration encoder block can parallelize η = 2, 4 and 8-bit parallel acceleration encoder blocks. 仞 子 Ν — 3,1, α 二 [0, 1, 1], β = [1,1, 0, The 2-bit parallel acceleration encoder starts with equation U), we get (Please read the precautions on the back before filling this page) R- 装 ·. #.

297 mm) 474068 A7 B7 V. Description of the invention (21)

Xl (t) = I (tl) ㊉ x2 (tl) ㊉ x3 (tl) (Please read the notes on the back before filling this page) X2 (t) = X! (T-1) X3 (t) = x2 (t-1) Q (t) = 1 (dagger-1) ㊉ ㊉ x2 (ti) The description of the accelerated encoder block shown in Figure 4. The following is necessary to convert to a time index after a two-string time-loop: x: L (t :) = I (tl) ㊉ X2 (t-1) ㊉々 (Bu1) &lt; = &gt; Xl (t) = I (tl) ㊉ Xi (t-2) ㊉ X2 (t-2) Given the parallel circuit: = &gt; χι (ρ) = ΙΟ (p-1) ㊉ X! (P-1) ㊉ X2 (P- Work) x2 (t) = xx (t-1) &lt; = &gt; x2 (t) = 1 (Bu 2) ㊉ ^ 2 (1-2) ㊉ x3 (t_2) Given the parallel circuit: = &gt; x2 ( P) = Industrial 1 (ρ-1) ㊉ X2 (P-1) ㊉ x3 (P-1) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy X3 (t) = X2 (t -1) &lt; = &gt; X3 (t) = (t-2) Given the parallel circuit: -24- This paper size applies the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) 474068 A7 B7 Explanation of the invention (22) = &gt; X3 (p) = Xi (p-1) Q (t) = Θ xi (tl) ㊉ X2 (t-1) &lt; = &gt; Q (t) = I (tl ) ㊉ [1 (卜 2) ㊉ X2 (t-2) ㊉ x3 (t-2)] ㊉ X; L (t: -2) Given the parallel circuit: = &gt; QO (p) = 10 (p-1 ) ㊉ II (p-1) ㊉ Xi (p-1) ㊉ X2 (P-1) ㊉. ¾ (P- · 1) Q (tl) = I (t-2) ㊉ Xi (t: -2)平行 χ2 (^ 2) Given the parallel circuit: _ = &gt; Ql (p) = Il (pl) ㊉ x ^ pl) ㊉々 (P · * 1 Figure 5 shows the result of this parallelization process, which is the circuit diagram of the two-bit implementation of the accelerated encoder block shown in Figure 4. 3.2 Example: N = 3, M = 1, α = [0, 1, 1], β = [1,1,0,1] 4-bit parallel acceleration encoder starts from equation (1), we get X ^ t) = I (tl) ㊉ ㊉ X3 (t-1) x2 (t) = Xl (t-1) X3 (t) = x2 (t-1) Q (t) = I (t-1) ㊉ Xl (t: -1) ㊉ X2 (dagger-1) -25- This paper size applies China National Standard (CNS) A4 specification (210 X 297 mm) ------ r ------ ^ installation-(Please read the precautions on the back before filling this page). 474068 A7 B7 5 2. Description of the invention (23) The description of the acceleration encoder block shown in FIG. 4. The following is necessary to convert to the time index after four series of time loops: (Please read the notes on the back before filling this page) xyt) = I (tl) ㊉ x2 (tl) ㊉ X3 (t-1) &lt; = &gt; Xl (t) = I (tl) ㊉ Χι (ί: -2) ㊉ x2 (t-2) &lt; = &gt; xdt) = I (tl) ㊉ 工 (t-3) ㊉ x2 (t- 3) ㊉ x3 (t-3) ㊉ Xl (t-3) &lt; = &gt; xl (t) = I (tl) ㊉ I (t-3) ㊉ χ; ι_ (Ι: -4) ㊉ X2 ( t-4) ㊉ I (t-4) ㊉ X2 (t-4) ㊉ x3 (t-4) Given the parallel circuit: = &gt; Xl (P) = 10 (p-1) ㊉ 工 2 (p-1 ) ®Ι3 (ρ-1) Θχι (ρ-1) ®χ3 (ρ-1) x2⑻ = Ki (tl) &lt; = &gt; X2⑻ = 工 （t-2〉 ㊉ x2 (t-2) ㊉ X3 ( t-2) &lt; = &gt; x2 (t) = worker (t-2) ㊉χ (t-3) ㊉ X2 (2_ 3) · &lt; = &gt; x2 (t) = worker (t-2 ) ㊉ [I (t-4) ㊉ X2 (t_4) ㊉ x3 (t-4)] ㊉ 4) Given the parallel circuit: _ _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs = &gt; x2 (P) = 工1 (P-1) ㊉ 13 (p-1) ㊉ Xl (pi) ㊉ X2 (pD ㊉ χ3 (p_ 1) X3 (t) = X2 (t -1) -26- CNS) A4 specification (210 X 297 mm) 474068 A7 ___B7__ 5. Description of the invention (24) &lt; = &gt; X3 (t) = Xi ( t-2) (Please read the notes on the back before filling this page) &lt; = &gt; x3 (t) = [工 （t-3) -3 乂 2 (dagger-3) ㊉ x3 (t-3)] &lt; = &gt; x3 (t) = I (t-3) ㊉ Xi (t-4) ㊉ Qk-4) Given the parallel circuit: = &gt; X3 (P) = I 2 (P-1) ㊉ xi ( P ** 1) ㊉ x2 (P-1) r Q (t) = I (tl) ㊉ Χ] _ (ί: -1) ㊉: ^ 2 (1 ^ 1) &lt; = &gt; Q (t) = I (tl) ㊉ [I (t-2) ㊉ x2 (t_2) ㊉ x3 (t-2)] ㊉ X] _ (t: -2) &lt; =: &gt; Q (t) = I (t : -1) ㊉ _I (t-2), ㊉ ㊉ x2 (t-3) ㊉ [工 （t-3) ㊉ X2 (t-3) ㊉ x3 (t-3)] &lt; = &gt; Q ( t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ [工 （t-4) ㊉ X2 (t-4) ® X3 (t-4)] ㊉ x2 (匕 -4 ) Given the parallel circuit: = &gt; QO (p) = worker 0 (p-1) worker 1 (p-1) worker 2 (p-1) worker 3 (p-1) ㊉ X3 (p-1 ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Q (tl) = 工 (t-2) ㊉ χ! (T-2) ㊉ X2 (t-2) — &lt; = &gt; Q (tl) = I ( t-2) Θ [工 (t-3) ㊉ Χ2 (^ 3) ㊉ 乂 3 (卜 3)] ㊉

Xl (t-3) &lt; two &gt; Q (tl) = I (t-2) ㊉ I (t-3) ㊉ X] _ (t-4) ㊉ X2 (t-4) ㊉ [工 （t -4) ㊉ X2 (t-4) · ㊉ X3 (t-4)] -27- This paper size applies to China National Standard (CNS) A4 (210 χ 297 mm) 474068 Α7 Β7 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a consumer cooperative V. Description of the invention (25) Given the parallel circuit: = &gt; Q1 (P) = II (ρ-1) ㊉ 工 2 (p-ι) ㊉ 工 3 (P-1) ㊉ Xi (p- ι) ㊉ x3 (p- 1) Q (t-2) = 工 （agger-3) ㊉ X] _ (t: -3) ㊉ x2 (t: -3) &lt; = &gt; Q (t-2 ) = I (t-3) ㊉ [I (t-4) ㊉ x2 (t: -4) ㊉ x3 (t-4)] ㊉ Xl (t-4) Given the parallel circuit: = &gt; Q2 (P) = 工 2 (ρ-1) Φ 工 3 (p-1) ㊉ q (p-1) ㊉ χ2 (p-ι) ㊉ χ3 (p-1) »Q (t-3) = I (t-4 ) ㊉ Xi (t-4) ㊉ X2 (t-4) Given the parallel circuit: = &gt; Q3 (p) = 工 3 (p-1) ㊉ ㊉ 工 (p-1) ㊉ χ2 (p-1) 6 shows the result of this parallelization process, that is, FIG. 4 shows a circuit diagram of the four-bit implementation of the accelerated coding block. 3.3 Example: N = 3, M = 1, α = [0,1,1], β = [1,1,0,1] The 8-bit parallel acceleration encoder starts from equation (1), we obtain -28- (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (26)

Xl (t) = I (tl) ㊉ x2 (t-1) ㊉ ^ 3 (= .1) (Please read the precautions on the back before filling this page) X2 (t) = χχ (t-1) X3 ( t) = x2 (t-1) Q (t) = I (tl) ㊉ x ^ tl) ㊉ 乂 2 (dead-work) The description of the acceleration encoder block shown in Figure 4. The following is converted to a time index after the eight-string time_ loop is necessary:

Xl (t) = I (tl) ㊉ X2 (t-1) ㊉ X3 (t__1) &lt; = &gt; Xl (t) = 1 (dagger-1) ㊉ X2_ (t: -2) ㊉ X2 (t- 2) &lt; = &gt; Xl (t) = I (t_l) ㊉ [工 (t-3) Θ X2 (t-3) ㊉ x3 (t-3)] ㊉ xl (匕 -3) &lt; = &gt; Xl (t) = I (tl) ㊉ I (t-3) ㊉ Xi (t-4) ㊉ X2 (t-4) ㊉ (I (t-4) ㊉ X2 (t · 4) ㊉ x3 (t -4)] &lt; = &gt; X (t) = I (tl) ㊉ I (t-3) ㊉ 1 (dagger-4) ㊉ [I (t-5) ㊉ x2 (t-5) ㊉ x3 (t-5)] ㊉ x2 (t: -5) &lt; = &gt; X) _ (t) = I (tl) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5 ) ㊉ X2 (t_6) .xUt) = I (tl) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ ㊉ 工 (1: -7) Staff of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Consumer Cooperatives &lt; = &gt; Xl (t) = I (tl) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ [工 (t-8) ㊉ X2 ( t-8) ㊉ X3 (t-8)] -29- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (27) Given the parallel circuit: (Please (Read the precautions on the back before filling this page) => χι (ρ) = 工 0 (p-1) ㊉ 工 2 (p-1) ㊉ 工 3 (p-1) ㊉ 14 (p-1) ㊉ I7 (p-1) ㊉ χ2 (ρ-1) Φ X3 (P-1) X2 (t) = χχ (t-1) &lt; = &gt; x2 (t) = [; E (t-2) ㊉ x2 (t-2) ㊉ x3 (t-2)] &lt; = &gt; X2 (t) = 工 （agger-2) ㊉ X] _ (t-3) ㊉ X2 (t-3) &lt; = &gt; X2 (t) = I (t-2) ㊉ [工(T-4) ㊉ X2 (t 「4) ㊉ x3 (t-4)] ㊉

Xl (t-4) · &lt; = &gt; X2 (t) = Gong (Bu 2) ㊉ 1 (Bu 4) ㊉ Xi (t-5) ㊉ X2 (t-5) ㊉ [I (t-5) ㊉ x2 (t-5) ㊉ x3 (t-5)] &lt; = &gt; x2 (t) = I (t-2) ㊉ I (t-4) ㊉ I (t: -5) ㊉ [工 （ D-6) Θχ2 (= -6) ㊉ x3 (t-6)] ㊉ 乂 2 (D-6) &lt; = &gt; x2 (t) = I (t-2) ㊉ I (t-4) ㊉ I (t-5) ㊉ 1 (仁 -6) ㊉ χ2 (^ 7) &lt; = &gt; x2 (t) = I (t: -2) ㊉ I (t-4) ㊉ I (t-5) ㊉ I (t: -6) ㊉ xyt-S) Given the parallel circuit: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs = &gt; X2 (P) = Industrial 1 (p-1) Industrial 3 (p-1) ㊉ 工 4 (p-1) ㊉ 15 (p-1) ㊉ Xi (p-1) X3 (t) = x2 (t-1) &lt; = &gt; x3 (t) = (t-2) -30 -This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (28) &lt; = &gt; x3 (t) = [; [(t: -3) ㊉ X2 (t-3) ㊉ x3 (t-3)] (Please read the precautions on the back before filling this page) &lt; = &gt; χ3 (1) = 工 （t-3) ㊉ X] _ (t: -4) ㊉ X2 (t_4) &lt; = &gt; X3 (t) = ㊉ (I (t-5) ㊉ X2 (t-5) ㊉ X3 (dagger-5)] ㊉ xl (dagger-5) &lt; =: &gt; X3 (t) = I (t-3) ㊉ I (t-5) ㊉ Xi (t-6) ㊉ X2 (t-6) ㊉ [工 （t-6) ㊉ x2 (t-6 ) ㊉ x3 (t-6)] &lt; = &gt; x3 (t :) = I (t-3) ㊉ I (t-5) ㊉ I (t-6) ㊉ (I (t-7) ㊉ x2 (dagger_7) ㊉ 乂 3 (dagger-7)] ㊉ x2 ( t-7) &lt; = &gt; x3 (t) = I (t-3) workers (t-5) workers (t-6) workers (dagger-7) ㊉ x2 (t-8) Circuit · == X3 (P) = Work 2 (p-1) Work 4 (p-1) ㊉ 15 (p-1) Work 6 (p-1) ㊉ x 2 (p-1) Q ( t) = I (tl) ㊉ xUt-l) ㊉; ^ 2 (=-工) &lt; = &gt; Q (t) = I (tl) ㊉ [I (t-2) ㊉ x2 (t: -2 ) ㊉ x3 (t-2)] ㊉ -2) &lt; = &gt; Q (t) = I (tl) ㊉ I (t-2) ㊉ X) L (t: -3) ㊉ x2 ((t- 3) ㊉ · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [工 （t-3) ㊉ X2 (t-3) ㊉ x3 (t-3)]-&lt; = &gt; Q (t) = 1 ( D-1) ㊉ I (t-2) ㊉ I (t-3) ㊉ [工 （t-4) ㊉ X2 ((t-4) ㊉ x3 (t-4)] ㊉ x2 ((t-4) &lt; = &gt; Q (t) = I (tl) ㊉ I (t-2) ㊉ (t-3) from 1 (dagger-4) ㊉ x2 ((t-5) &lt; = &gt; Q ( t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ I (t-4) ㊉ xUt-S) -31-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (29) &lt; = &gt; Q (t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ I (t-4)工 [工 （t-7) ㊉ x2 (t-7) ㊉ X3 (t-7)] &lt; = &gt; · Q (t) = I (tl) ㊉ I (t-2) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-7) ㊉ x 丄 (t-8) ㊉ X2 (t-8) Given the parallel circuit: = &gt; QO (p) = IO (pl) ㊉ 工 1 (ρ-1) ㊉ I2 (p-1) ㊉ I3 (p-1) ㊉ I6 (p-1) ㊉ χ (p-1) ㊉ χ2 (P_1) Q (tl) = I (t-2) ㊉ xytO ㊉ X2 (t-2) &lt; = &gt; Q (tl) = I (t-2) ㊉ (I (t-3) ㊉ x2 (t-3 ) ㊉ x3 (t-3)] ㊉ X] _ (t-3) &lt; = &gt; 'Q (tl) = I (t-2) ㊉ I (t-3) ㊉ ^ (¢: -4) ㊉ x2 ((t-4) ㊉ [工 （t-4) ㊉ x2 (t ： -4) ㊉ x3 (t-4)] &lt; = &gt; Q (tl) = I (t-2) ㊉ I (t-3) ㊉ 1 (Bu 4) ㊉ [I (t: -5) ㊉ X2 (t-5) ㊉ X3 (t-5)] ㊉ X2 (t-5) Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative ------------ install --- (Please read the notes on the back before filling this page) &lt; = &gt; Q (t: -1) = I (t-2 ) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ x2 (t-6) &lt; = &gt; Q (tl) = I (t-2) 3) ㊉ I (t-4) ㊉ I (t-5) ㊉ &lt; = &gt; Q (t-1) = I (t-2) ㊉ I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ [工 （t-8) ㊉ x2 (t-8) ㊉ x3 (t-8)] -32- This paper size is applicable to China National Standard (CNS) A4 (210 x 297 mm) 474068 A7 B7 V. Description of the Invention (3Q) Given the parallel circuit: (Please read first Read the notes on the back and fill in this page) => Ql (p) = Il (pl) pl 工 2 (pl) ㊉ 工 3 (pl) ㊉ 工 4 (pl) ㊉ I7 (p-1) ㊉ χ2 ( ρ-ΐ) ㊉ χ3 (ρ_ι) Q (t-2) = I (t-3) ㊉: ^ (1: -3) ㊉: ^ 2 (die-3) &lt; = &gt; Q (Bu 2) =: I (t-3) ㊉ [I (t-4) ㊉ x2 (t-4) ㊉ x3 (t-4)] ㊉ χχ (t-4) &lt; = &gt; Q (t: -2) = I (t-3) ㊉ 1 (匕 -4) ㊉ xyt-S) ㊉ xsk-5) ㊉ [工 （t-5) _ ㊉ X2 (t-5) ㊉ x: 3 (t-5)] &lt; = &gt; Q (t-2) = Gong (Bu 3) Gong (t-4) Gong (t-5) ㊉ [Gong (t-6) ㊉ X2 (t-6) ㊉ X3 (t -6)] ㊉ x2 (t-6) &lt; = &gt; Q (t-2) = I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ I (t-6) 2 x2 (dagger-7) &lt; = &gt; Q (t-2> = I (t-3) ㊉ I (t-4) ㊉ I (t-5) ㊉ I (t-6) ㊉ Xi (t -8) Given the parallel circuit: = &gt; Q2 (p) = worker 2 (ρ-l) worker 3 (ρ-l) worker 4 (ρ-l) worker 5 (ρ-l) worker ( p-1) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Q (t-3) = Industrial (t-4) ㊉ Xi (t-4) ㊉ X2 (t-4) &lt; = &gt; Q (t_3) = I (t-4) ㊉ [I (t-5) ㊉ x2 (ft-5) ㊉ x3 (t-5)] ㊉

Xl (t-5) -33- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 474068 A7 B7 V. Description of the invention (31) &lt; = &gt; Q (t-3) = I (t-4) ㊉ I (t-5) ㊉ Xi (t: -6) Θ x2 (t_6) ㊉ [工 (t-6) ㊉ X2 (亡 -6) ㊉ X3 (亡 弓)] &lt; = &gt; Q (t-3) = I (t-4) ㊉ I (t-5) ㊉ I (t-6) ㊉ [工 （t-7) Θ X2 (t-7) ㊉ ㊉ x2 (t_7 ) &lt; = &gt; Q (Bu 3) = I (t-4) Θ I (t-5) ㊉ 工 (卜 6) ㊉ 工 (t-7) ㊉ X2 (t-8) Given the parallel circuit: = &gt; Q3 (p) = Worker 3 (p-1) Worker 4 (p-1) Worker 5 (p-1) ㊉ 16 (p-1) ㊉ x2 (P-1) Q (t-4) =: E (t-5) ㊉ xyt-S) ㊉ x2 (t-5) &lt; = &gt; Q (t-4) = I (t: -5) ㊉ [I (t-6) ㊉ χ2 ( ^ 6) ㊉ χ3 (^ 6)] ㊉ χχ (t-6) &lt; = &gt; Q (t-4) = I (t-5) ㊉ I (t-6) ㊉ xyt-?) ㊉ x2 ( t-7) ㊉ [工 （t-7) ㊉ x2 (t-7) ㊉ x3 (t-7)] &lt; = &gt; Q (t-4) = I (t-5) ㊉ I (t- 6) ㊉ I (t-7) ㊉ [工 （t-8) ㊉ Χ2 (υ) ㊉ x3 (t-8)] ㊉ X2 (t-8) -34- The paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------------- (Please read the notes on the back before filling out this page) Order: Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Sakusha Co., Ltd. 474068 A7 B7 V. Description of the invention (32) In view of parallel circuits: (Please read the notes on the back before filling out this page) = &gt; Q4 (p) = 工 4 (p-1) ㊉ 工 5 ( p-1) ㊉ 工 6 (p-1) ㊉ 工 7 (p-1) ㊉ X3 (P-1) Q (t-5) = I (t-6) ㊉ Χι_ (ί: -6) ㊉: &lt; 2 (死 一 6) &lt; = &gt; Q (t-5) = I (t-6) ㊉ [工 (t-7) ㊉ χ2 (^ 7) ㊉ x3 (t_7)] ㊉

Xl (t-7) &lt; = &gt; Q (t-5) = I (t-6) ㊉ 工 (t-7) ㊉ ^ (68) Θ X2 (t_8) ㊉ [工 (t-8) ㊉ X2 (t-8) ㊉ χ3 (^ 8)] Given the parallel circuit: = &gt; Q5 (p) = I5 (p-1) ㊉ 工 6 (pl) ㊉ 工 7 (pl) ㊉ xi (Pl) ㊉ X3 (P_ 1). Q (t-6) = I; (t: -7) ㊉ Xi (t-7) ㊉ X2 (t-7) &lt; = &gt; Q (t-6) = I (t- 7) ㊉ [I (t-8) ㊉ X2 (t-8) Θ x3 (t-8)] ㊉ χχ (t-8) Given the parallel circuit: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs = &gt; Q6 (p) = 6 (p-1) and 7 (p-1) ㊉ x; l (p-1) ㊉ x2 (P · * 1> ㊉ x3 (P-1) Q (t-7) = I (t-8) ㊉ xyt-S) ㊉ x2 (t-8) -35- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 474068 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy System A7 V. Description of the invention (33) Given the parallel circuit: = &gt; Q7 (p) = 工 7 (ρ-l) ㊉ Χ] _ (p-1) ㊉ χ2 (p- 工) • Figures 7A and 7B show This parallelization process results in a circuit diagram of the eight-bit implementation of the accelerated coding block shown in FIG. 4. 4. VHDL ^ The recursive parallelism explained above step by step can be used as a logical synthesis tool to compare different design alternatives. Without being limited to any such special system, the very fast hardware description language VHDL is referenced here as a typical example of logic span design using logic synthesis tools. The advantage of the implementation of the accelerated encoder block parallelization implementation of the vhdl code is that the design can be implemented in a short time without being limited to a specific technology, such as FPGA. Therefore, the actual technology is not standardized by accelerating the parallelization of the encoder block, but it can be set to a parameter that will be processed by the logical synthesis tool following the encoding, so it is easy to change compared with different design choices. In the following, the VHDL codes are listed in the 2, 4 and 8-bit parallel acceleration encoder blocks shown in Figures 5, 6 and 7. Since the V η d L codeword is well known in related arts today and the parallelization results explained above are self-evident, no further details will be given here. LIBRARY ieee; USE ieee.std—logic 一 1164.ALL; ------ I ----- Install · --- I --- Order --- I ----- (Please read the Please fill in this page again for attention) -36 474068 A7 B7 V. Invention Description (34 USE ieee. Std_logic__arith. ALL; ENTITY en_turb〇_c〇der—rt: l IS • PORT (-General: reset :—p clk32m input: one 8 input_4 input_2 input__l: industrial N STD_L · CλGIC;: industrial N STD_L〇GIC;-Clock (rising edge triggered) IN std_logic_vector (7 DOWNTO 0); IN std_logic_vector (3 DOWNTO 0 ); IN std_logic_vector (1 DOWNTO 0); IN std_logic; turboCoding 2 bit parallel output_8 output_4 〇utput_2 output 1 END en turbo coder rtl; OUT std_logic_vector (7 DOWNTO 0); 〇UT std_logic —Vector (3 DOWNTO 0); OUT std_logic_vector (1 DOWNTO 0); OUT std—logic (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs

ARCHITECTUilE rtl OF en turbo coder rtl IS SIGNAL si_xl SIGNAL · si_x2 SIGNAL si_x3 SIGNAL sl_i SIGNAL · si o std_logic; std_logic; std_logic; std_logic; std_logic; -37- paper Standards apply to China National Standard (CNS) A4 specifications (210 X 297 mm) 474068 A7 B7 V. Description of invention (35) SIGNAL s2_ jkI std__logic; SIGNAL · s2_ one x2 std_ _l0gic; SIGNAL s2_ one std one .logic / SIGNAL · s2_ a i std a JLogic a vector * (1 DOWNTO 〇); SIGNAL · s2_ a o std a logic a vector (1 DOWNTO 〇); SIGNAL s4_ a xl std_ ^ logic; SIGNAL s4_ _x2 std a logic SIGNAL s4_ __x3 std_ a logic; SIGNAL s4_ a i std_ logic—vector (3 DOWNTO 〇); SIGNAL · s4 · a o std_ logic a vector (3 DOWNTO 〇); SIGNAL · s8 a xl std_ ^ logiq; SIGNAL s8 _8 std_ logic; SIGNAL s8-x3 std_-iogic; SIGNAL · s8-i std_ logic-vector * (7 DOWNTO 〇); SIGNAL s8 —〇std_ logic — vector (7 DOWNTO 〇); BEGIN tc: 1: PROCE SS (clk32m, reset_ p)-seriell building of (Please read the notes on the back before filling out this page) Binding ·· Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

turbo coder block TCB

BEGIN IF reset—p = 11 'THEN si xl &lt; =' 0 '; -38- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474068 A7 _B7 V. Description of the invention (36) sl__ a x2 &lt; = 1 0 '/ si _x3 &lt; =' 0 '; si a_i &lt; =' 0,; si a_〇 &lt; = '0' ; ELSIF clk ^ m'EVENT AND clk32m = '1 1 THEN si-i &lt; = input-1 1; si-xl &lt; = sl__i XOR sl_x2 XOR sl___x3; si-x2 &lt; = sl-xl; s1-x3 &lt; = sl—x2; sl_〇 &lt; = sl__i XOR sl_x2 XOR sl_xl; END IF; END PROCESS tc_l; output__l &lt; = sl_o; tc-1 2: PROCESS (clk32m / reset_p)-2bit parallel building of turbo coder block

BEGIN IF reset_p = '1' THEN s2—xl &lt; = '0'; This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---------- I-- — — — — — II ^ · 11111111. (Please read the notes on the back before filling this page) 474068 A7 _______B7 _ V. Description of the invention (37) s2—x2 &lt; = 'Ο'; s2 ″ c3 &lt; = 1 Ο 1 ； s2—i &lt; = (OTHERS = &gt; · 0 ·); s2—0 &lt; = (OTHERS = &gt;'0');

ELSIF clk32m'EVENT AND clk32m = '1' THEN s2—i &lt; = input—2; s2—xl &lt; = s2—i (0) X〇R s2—xl X〇R s2—x2; s2_x2 &lt; = s2_i (1) XOR s2-x2 X〇R s2-x3; s2_x3 &lt; = s2-xl; s2-o (0) &lt; = s2Ji (0) X〇R · s2-i (l) X〇R s2 -Xl X〇R s2-x2 X〇R s2_jk3; s2-o (l) &lt; = s2-i (l) X〇R s2-xl X〇R s2—x2; END IF; END PROCESS tc_2; output— 2 &lt; = s2_o; tc___4: PROCESS (clk32m / reset_p)-4bit parallel building of turbo coder block 9

BEGIN

IF reset a p = say 1, THEN -40-This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) Please read the note on the back h Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474068 A7 B7 V. Description of the invention (38) s4_ _xl &lt; = '0 1 / s4_ _x2 &lt; = 1 0' / s4_ _x3 &lt; = '0' / s4_ _i &lt; = (ΟΊ 'HERS = &gt; 1 〇' ) / s4_ _〇 &lt; = (OTHERS = &gt; 1 〇 丨) / ELSIF clk32m 'EVENT AND clk32m =' 1 'THEN s4_ _i &lt; = input_4, r s4_ _xl &lt; = s4 i (〇) X〇R s4 one_i (2) XOR s4__i (3) X〇R s4 one_xl XOR s4_x3; s4_ x2 &lt; = s4 two i (1) X〇R s4 one_i (3) XOR s4__xl X〇R S4 one _x2 XOR s4_x3; s4_ _x3 &lt; = s4 i (2) X〇R s4 a_xl XOR s4_x2; s4_ _〇 (0) &lt; = s4 a i (〇) X〇R s4 a.i (l) XOR s4_i (2) X〇R s4_ i (3) XOR S4_x3; s4_ _〇 (l) &lt; = s4 -i (l) X〇R s4 a.i (2 &gt; XOR s4_i (3) X〇R s4_ _xl XOR s4_x3; s4_ _〇 (2) &lt; = s4 -i (2) X〇R s4 -_i (3) XOR s4__xl X〇R s4_ _x2 X〇Rs4-x3; s4 one〇 (3) &lt; = S4_一 丄 ⑶ X〇R s4_ _xl XOR s4_x2; — — — — — — ——— 装 ·! Ί 丨! Order ----- I-- (Please read the notes on the back before filling this page) Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Consumption Cooperative END IF; END PROCESS tc_4; output—4 &lt; = s4__o; This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Printed 474068 A7 B7 V. Description of the invention (39) tc-8: PROCESS (clk32m, reset—p)-8bit parallel building of turbo coder block

BEGIN

IF reset—p = '11 THEN S8- one xl &lt; = '0'; s8 · _x2 &lt; = '0'; s8_ —x3 &lt; =, 01; s8_ one i &lt; = (OTHERS = &gt; 101 ); s8_ &lt; = (OTHERS = &gt;,01); ELSIF clk32m'EVENT AND clk32m = '1 1 THEN s8_i &lt; = input_8; s8-xl &lt; = s8_i (0) XOR s8__i (2) X〇R s8_i (3) X〇R s8_i (4) XOR s8__i (7) XOR s8_x2 XOR s8_x3; s8—x2 &lt; = s8_i (1) XOR s8_i (3) XOR s8_i (4) XOR s8_i (5) * l s8—x3 &lt; = s8_i (2) XOR s8_i (4) XOR s8_i (5) XOR s8_i (6) XOR s8__x2; _ s8_o (0) &lt; = s8_i (0) XOR s8__i (l) XOR s8_ XOR s8_i (3) XOR s8_i (6) XOR s8 xl XOR s8 x2; -42- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) — I — I 丨 — — — — — 丨^^ ·! 丨 —! —Order. (Please read the notes on the back before filling this page) 474068 A7 B7 V. Description of the invention (40) s8 〇 (1) s8_o (2) s8_o (3) s8_〇 ( 4) s8-0 (5) s8-1. (6) s8 〇 (7) s8—i (l) X〇R s8_ X〇R s8-XOR s8_ s8—i (2) XOR s8_ X〇R s8_ s8—i (3) XOR s8_ XOR s8 wide s8— i (4) XOR s8 · XOR s8_ s8—i (5) XOR s8 XOR s.8 s8—i (6) XOR s8 XOR s8 s8 i (7) XOR s8 _i (2) XOR s8_i (3) _i (4 ) XOR s8—i (7) x2 X〇R s8—x3; _i (3) XOR s8__i (4) _i (5) XOR s8_xl; _i (4) XOR s8—i (5) _i (6) XOR s8_x2; _i (5) XOR s8—i (6) _i (7) XOR s8_x3; __i (6) XOR s8_i (7) __xl XOR s8__x3; _i (7) XOR s8_xl _x2 XOR s8_x3; xl XOR s8 ------------ Install --- (Please read the precautions on the back before filling this page). END IF; END PROCESS tc__8; output___8 &lt; = s8_〇; END rtl; 5. Accelerated encoder implementation Although the background art related to the present invention has been referred to FIG. 8, this FIG. 8 will be related to the present invention and will be shown below. As for the present invention explained so far, the reference has been added with M outputs -43- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) #-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System 8 6 ο 4 A7 B7 Jade Economy Ministry Intellectual Property Bureau employee consumer cooperatives printed invention description (41) Parallelization of fast-coded fasting box. However, as the present invention must meet the requirements of the present invention, the structure of the accelerated acceleration encoder needs to be parallelized and the encoder block is activated twice, as shown in FIG. 8 (where two blocks assume M = 1). -The accelerated encoder block is related to the normal input data stream to derive 0_T i shown in the figure &quot; g and another accelerated encoder block is related to the inserted input data stream to derive OUTPUT 2. Since the input data stream is also directly transferred to OUTPUT 0, the third output of the accelerated encoder has a width of 3n bits per parallel clock cycle, where n is the degree of parallelization. 1 44 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

474068 .. Patent No. 89117〇76 Chinese Application for Amendment of Patent Scope (September 1990) VI. Implementation of Patented Parallel Acceleration Encoder Implementation Method The encoder block starts from the serial acceleration of the following formula (t ) Father 2 (dagger) • 1 (tl) © arx ± (t-1) © χχ (tl) 4 · Χ2 (^ 1) © ·· ㊉ ㊉ αΝ · ΧΝ (Νυ ai ε {〇, 1} xN ( t) = xN ^ i (t: .i) Qj (tl) = PjO.I (ti) ㊉ Xi (t, l). [pj0 ·% ㊉ β],] Θ Binding xN (t, l), [Pj〇.aN ㊉ β] · N] Pi j ε {0 ,, 1} j ε [1, ..., N] includes the following steps:) The first internal state is as follows Time index instead of processing: X1 (dagger-1) # I (t · 2) ㊉acx1 (t-2) Θ a2.X2 (t-2) © ··· θ aN * XN (t ： -2) 474068 VI.Scope of patent application 8 8 8 8 AB c D (2 .1) xl (t (Π4)) = ⑴㊉ αιχι (^ η) ㊉ α2 × 2 (Bu 11) ㊉ ·· ㊉ αΝ.χΝ ( -n) 1) (2, X Wang · η · where η is the degree of parallelization; ib) The time index of the remaining internal states (i = 2, ···, N) is replaced as follows: xi (dagger-1 ) Xi-i (C-2) equipment (2.Xi · l) order (2 · parent 丄 · η-1) Qj c) implement the time index of the output signal instead of processing l) = PjO.I (dagger, (I + l)) ㊉ -2- ε · · ·, n-ij (2.Qi) i ρ ζ Φ This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 4 ^ 4068 To derive the parallel output vector Qj (dagger) = Qj〇 (p) Qj (dagger-1) = QjKp) Qj (t- (ni)) = Qjn-i (p) j ε [l, ·· ,, M] ϊ d) Carry out each internal state Xk⑴ as follows: (k === time index instead of processing ..., which is called to set the maximum time index element of this internal state Xk⑴ to tmax === t- 1; d2) Scan the internal state representation with the maximum time index tmax ~ the internal state representation of ⑴; d3) use equation (2) to replace the step with the state variable xk (t) by using state variables instead of steps from tmax to tmax-1 to perform time-to-time index conversion ; And d4) when tmax &gt; tn, decrease the value of tmax by 1 and repeat steps d2) to d4); + e) implement each parallel output vector Qj (t) (j == 1, ^ Μ) as the following sub-steps Time index of Qj (ti) (i = 〇, ···, n-2) instead of processing ... 'el) Set the maximum time index element of the vector element Qj (ti) for consideration of the parallel output vector Qj⑴ as tmax = t Seven i; e2) Scan 474068 of vector element Qj (ti) with large time index Λ8 B8 C8 D8 Patent scope table »e3) Use equation (2) to pass Variable instead of the step of the vector element Qj (t-i) of the represented max by the 〖to Tmax 1 after the transfer is performed to a time index change; and e4) when tmax> t-n The tmax reduce the value of 1 and repeat steps d2) to d4). 2. A kind of parallel acceleration encoder block with parallelization degree n, including: a) device (10, ..., 17) for storing input signal I (t) n samples GO1), ..., I (tn)) To the parallel acceleration coding block; b) at least one device (Q0, ..., Q7) to store n samples of at least one output signal Qj⑴ (j = 1, ..., M) of the parallel acceleration coding block (Qj (t ), ···, Qj (t- (n-1)); and °) Accelerated encoder device, including a delay unit library of n delay units (Xi, ..., χN), and adapted to the input signal I (t) The η samples are processed in parallel, so that at least two delay units of the delay unit library (X!, ..., XΝ) directly receive the η samples (I (tl), ..., I (t_n) of the input signal I (t) )) And the at least one delay unit (X1, Xn) output signal of the acceleration encoder device are supplied to at least two delay units of the acceleration encoder device. 3. The parallel acceleration encoder block with the degree of parallelism η as claimed in item 2 of the scope of patent application, characterized in that the acceleration encoder device has a parallel acceleration encoder block described by the following formula: Structure that can be derived from the implementation method of the accelerated encoder -4- The paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) 474068 8 8 8 8 Α Β c D •, patent application scope &gt;: 1 (dagger ) = 1 (dagger, 1) ㊉ ai.xi (t: -l) ㊉ (^ 2. 乂 2 (dagger-1) ㊉ ··· ㊉ αΝ.χΜ (dagger-1) with 丄 ε {〇, 1 } χ2 (dagger) = χχ (tl) x ^ j (t) = xn-i (t-1) Qj (t) = Pj〇.I (dagger-1) ㊉ xi (t: -l). [Pj 〇-ai ㊉ pj] J θ x ^ (t: -l) * [pj 〇 · α ^ Θ Pj ^] Pji ε {0/1} j ε [1, ···, M] 4. If applying for a patent The parallel acceleration encoder block of the range 2 or 3 is characterized in that the degree of parallelization is 2, ^ N = 3, M = 1, a = [0, 1, 1], and β = [1, 1, 0, 1] and the structure of the acceleration encoder device is Q0 (p) = IO (pl) ㊉l (pl) ㊉ Xl (pl) ㊉ χ2 (Ρ- ”㊉ χ3 (Ρ · 1) Ql (p) = Ι1 (ρ-1) ㊉ X 丄 (ρ-1) Θχ2 (Ρ-1) '17 of which -5- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 474068 8 8 8 8 AB c D Patent application scope X1 (P) = I〇 (pl) ㊉ Xl (pl) ㊉ X2 (p-1), X2 (P) = Il (pl) ㊉ X2 (p-1) ㊉ X3 (P-1) 'and X3 (P) = Xl (P-1) 5. If the parallel acceleration encoder block of the patent application scope item 2 or 3 is characterized in that the degree of parallelization is 4, the N = 3, M = 1, α = [0, 1, 1], β = [1, 1, 0, 1] and the structure of the acceleration encoder device is Q〇 (p) = Ι0 (ρ-1) Θ Il (pl) ㊉ 工 2… 1) ㊉ Ι3 (ρ-1) Θ χ3 (Ρ-1) Ql (p) = Il (pl) ㊉ 工 2 (ρ-1) ㊉ Ι3 (ρ-1) ㊉ xyp -l) © X3 (P- 1) Q2 (p) = I2 (p-1) ㊉ I3 (p-1) ㊉ x: L (p, l) ㊉ X2 (P-1) ㊉ X3 (P. 1 ) Q3 (p) = I3 (p-1) Θ xyp-l) ㊉々 (P · 1), where X] L (p) = IO (pl) ㊉ I2 (p-1) θ I3 (p-1 ) ㊉ x; L (p-1) ㊉ X3 (p-1) 'x2 (p) = II (p-1) ㊉ 13 (p-1) ㊉ Xl (p-1) ㊉ x2 (pl) ㊉' And -6 This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 8 8 8 8 A Β c D 474068 6. Scope of patent application x3 (p) = I2 (p-1) ㊉ Father l (p-1) ㊉ χ2 (P-1). Γ: 6. The parallel acceleration encoder block according to item 2 or 3 of the patent application scope, characterized in that the degree of parallelization is 8, the N = 3, M = 1, α = [0, 1, 1], the β = [1,1,0, 1] and the structure of the acceleration encoder device is Q〇 (p) = IO (pl) ㊉ 工 l (pl) ㊉ Ι2 (ρ-1) @! 3 (ρ-1) ㊉ Ι6 (ρ-1) ㊉ xUp-l) ㊉ χ2 (ρ-1) Ql (p) = Il (pl) ㊉ 工 2 (ρ-1) Θ Ι3 (ρ-1) ㊉ Ι4 (ρ-1) ㊉ Ι7 (ρ-1) @ χ2 (ρ-1) ㊉ χ3 (ρ-1) Q2 (p) = Ι2 (ρ-1) ㊉ Ι3 (ρ-1) ㊉ 工 4 (ρ-1) ㊉ Ι5 ( ρ · 1) Θ χι (ρ-1) Q3 (p) = Ι3 (ρ-1) ㊉ Ι4 (ρ-1) ㊉ 工 5 (ρ-1) ㊉ 工 6 (ρ-ι) © χ2 (ρ- 1) Q4 (p) = Ι4 (ρ-1) θ Ι5 (ρ-1) ㊉ 工 6 (ρ-1) ㊉ 工 7 (ρ-ΐ) © χ3 (ρ-. 1) Q5 (p) = Ι5 (ρ-1) ㊉ 工 6 (ρ-1) © Ι7 (ρ-1) ㊉ Xl (pD ㊉ χ3 (ρ. 1) QS (p) = IS (pi) © Ι7 (ρ-1) ㊉ Χι ( ρ-ι) ㊉ xyp- ”㊉ χ3 (ρ_ 1) Q7 (p) = Ι7 (ρ-1) ㊉ xUp-l) ® χ2 (ρ-1), this paper size applies Chinese National Standard (CNS) Α4 (210 X 297 mm) 8 8 8 8 AB c D 474068 6. The scope of patent application where Xi (p) = IO (ρ ·· 1) ㊉ I2 (p-1) ㊉ I3 (p-1) ㊉ I4 ( p-1) 7 (pl) ㊉ X2 (p-1) ㊉ X3 (p-1), x2 (P) =) 1 (P-1) ㊉ I3 (p-1) ㊉ I4 (p-1) ㊉ I5 (p -1) ㊉ Xi (p-1), and x3 (p) = I2 (p-1) I4 (p-1) ㊉ I5 (p-1) ㊉ I6 (p-1) ㊉ x2 (pl). 7. —A computer-readable storage medium, which is encoded with a software code portion, which enables a computer to execute the parallel acceleration encoder implementation method as described in the scope of patent application item 1. 8. As a computer in the scope of patent application item 7. Readable storage media, where the software code portion is of the VHDL type. 9. For a computer-readable storage medium, which is subject to the scope of patent application No. 8, the software code portion is defined as: LIBRARY ieee; USE ieee.std_logic_1164. ALL; USE ieee.std_logic_arith.ALL; ENTITY eurbo_coder11 IS P〇RT (— Ge πθ] T3.1: reset_p: IN STD ^ LOGIC; clk32m: IN STD—LOGIC; — Clock (rising edge triggered) -8- V, 、 This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 474068 A8 B8 C8 D8 VII. Patent application scope input: _8 input: _4 input: _2 input—1 --turboCoding 2 output—8 output: —4 outp ut_2 output ”); EOT) en turbo coder rtl; IM std_logic_vector (7 DOWNTO 0) / IMstd_logic_vector (3 DOWNTO 0); IN std_logic_vector (1 DOWNTO 0) / IN std_logic; bit parallel: OUT std_logic_vector * (7 DOWNTO 0);: OUT std_logic_three vector (3 DOWNTO 0);: OUT std_logic_vector (1 DOWNTO 0);: OUT std_logic ARCHITECTURE rtl OF en turbo coder rtl IS SIGNAL sl_xl SIGNAL Si_x2 SIGNAL si_x3 SIGNAL si_i SIGNAL si o SIGNAL s2_xl SIGNAL S2_x2 SIGNAL s2_x3 SIGNAL s2_i SIGNAL s2_〇std_logic, std_logic; std_logic; r std logic; std—logic; std_logic; std_logic, std_logic; std_logic_vector (1 DOWNTO 0); std_logic_vector (1 DOWNTO 0); -9- This paper standard applies to China National Standard (CNS) A4 specification (210X297 mm) 8 8 8 8 A BCD 474068 6. Patent application scope SIGNAL s4. Jcl: std · a logic; SIGNAL S4 · _x2: std_ _logic; SIGNAL s4__x3: std_ logic; SIGNAL S4_: std · logic —Vector (3 DOWNTO 〇); SIGNAL S4_ a o: st d_ JLogic_vector (3 DOWNTO 〇) / SIGNAL s8_ jcl: std__logic; SIGNAL S8__x2: std_ logic; SIGNAL S8_ jk3: st d__logic; SIGNAL s8 · i: std_logic_vector (7 DOWNTO 〇) _8 p: std_ • logic_vector (7 DOWNTO 〇); BEGIN tc_l: PROCESS (clk32m, reset_p)-seriell building of TC BEGIN process F reset_p =: 11 'THEN si_xl &lt; = 10'; sl_x2 &lt; = '0 1; Sl_x3 &lt; = 10 1; si—i &lt; =' 0 ·; Sl_〇 &lt; = 101; ELSIF clk32m, EVENT AND clk32m = »1 'THEN A f si—i &lt; = input: ”;,” -10- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 47406S A8 B8 C8 D8 VI. Application scope sl_xl &lt; = sl_i X〇R sl_x2 XOR sl_x3; si-x2 &lt; = sl_xl; sl_x3 &lt; = sl_x2; sl_o &lt; = sl_i XOR sl_x2 XOR sl_xl; END IF; END PROCESS tc-1 1; output: _l &lt; = sl_o; tc-1 2: PROCESS ( clk32m / reset a p)-2bit par building of TC BEGIN IF reset a p = 11 'THEN s2—xl &lt; = 101; s2—x2 &lt; = 101; s2 x3 &lt; = 10 '; s2—i &lt; = (OTHERS = &gt;101); s2—o &lt; = (OTHERS = &gt;' 0 f); ELSIF clk32m, EVENT AND clk32m = 111 THEN s2_i &lt; = input_2; s2_xl &lt; = s2_i (0) XOR s2_xl XOR s2_x2; s2_x2 s2 i (1) XOR s2 x2 XOR s2 x3; -11-This paper size applies to China National Standard (CNS) A4 (210x 297 mm) Binding 8 8 8 8 A BCD 474068 6. Scope of patent application s2_x3 &lt; = s2—xl; s2—. (0) &lt; = s2 i (0) XOR s2 i (1) XOR s2 xl XOR s2 x2 XOR s2 x3; s2 o (l) &lt; = s2 i (1) XOR s2 xl XOR s2 x2; — — — — END IF; END PROCESS tc_2; output_2 &lt; = s2_o; tc-4: PROCESS (clk32m / reset_p)-4bit par building of TC BEGIN IF reset_p = 111 THEN S4- _xl &lt; =, 〇 ·; S4 ^ _x2 &lt; = · 〇 ,; S4_ _x3 &lt; = 10 '; S4_ &lt; = (OTHERS =: &gt; · 〇); S4_ o &lt; = (OTHERS =: &gt; · 〇 ·); ELSIF clk32m »EVENT AND clk32m = Ί1 THEN s4—i &lt; = input—4; s4—xl &lt; = s4—i (0) XOR s4_i (2) XOR s4—i (3) XOR S4 xl XOR s4 x3; -12- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm) 474068 A8 B8 C8 D8, patent application scope S4_x2 &lt; = s4_i (l) XOR. S4_i (3) XOR s4_xl XOR s4_x2 XOR S4_x3; S4_x3 &lt; = s4_i (2) XOR s4_xl XOR s4_x2; s4_o (0) &lt; = s4_i (0) XOR s4_i (l) XOR s4_i (2) X〇R s4_i (3) XOR s4 a l) &lt; = s4_i (l) XOR s4_i (2) XOR s4_i (3) • XOR s4_xl XOR S4_x3; s4 one. (2) &lt; = s4_i (2) XOR s4_i (3) XOR s4—xl XOR S4_x2 XOR s4—x3; s4_o (3) &lt; = s4_i (3) XOR s4_xl XOR S4—X2; END IF; END PROCESS tc ; output_4 &lt; = s4_o; tc—8: PROCESS (clk32m, reset_p)-8bit par building of TC BEGIN IF reset ^ p = 111 THEN s8_xl &lt; = 10 '/ s8_x2 &lt; = (01; s8_x3 &lt; = 101; s8 i &lt; = (OTHERS = &gt;101); -13- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 474068 8 8 8 8 AB c D s8 ο (OTHERS 〇f); ELSIF clk32m'EVENT clk32m 11 THEN s8_i s8 xl &lt; = input_8 s8 i (0) s8 x2 s8 x3 s8—i (1) s8 i (2) s8 〇 (0) &lt; = s8 i (0) s8 o (l) &lt; = s8 i (1) s8_o (2) s8 one. (3) s8_o (4) s8—. (5) s8_o (6) s8 o (7) &lt; = s8_i (2) s8_i (3) s8_i (4) s8_i (5) s8_i (6) s8 i (7) XOR s8_i (2) XOR s8_i (3) X〇R s8_i (4) XOR s8_i (7) XOR S8 one x2 XOR s8 」c3; XOR s8Jl (3) XOR s8_i (4) XOR s8_i (5) XOR s8_xl; XOR s8_'i (4〉 XOR s8_i (5) XOR s8_'i (S) XOR s8_x2; XOR s8—i (l) XOR s8—i (2) XOR s8_i (3) XOR s 8_i (6) XOR s8_xl XOR s8_x2; XOR s8—i (2) XOR s8—i (3) XOR s8_i (4) XOR s8—i⑺ XOR s8—x2 XOR s8—x3; XOR s8_i (3) XOR s8_i (4 ) X〇R s8—i (5) XOR s8—xl; XOR s8_i (4) XOR s8_i (5) XOR s8—i (6) XOR s8_x2; XOR s8_i (5) XOR s8_i (6) XOR s8_i (7) XOR s8—x3; XOR s8—i⑹ XOR s8_i (7) XOR s8_xl XOR s8_x3; XOR s8_i (7) XOR s8—xl XOR S8_x2 XOR s8_x3; XOR s8 xl XOR s8 x2; -14- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 8 8 8 8 AB c D 0 474068 6. Scope of patent application END IF; END PROCESS tc_8; output—8 &lt; = s 8 一 o ; END rtl 0 5 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)