WO2020155074A1

WO2020155074A1 - Processing apparatus, method, and related device

Info

Publication number: WO2020155074A1
Application number: PCT/CN2019/074309
Authority: WO
Inventors: 陈政荫; 刘宇; 朱强; 卢晓博
Original assignee: 华为技术有限公司
Priority date: 2019-01-31
Filing date: 2019-01-31
Publication date: 2020-08-06
Also published as: CN113383317B; CN113383317A

Abstract

Disclosed in the embodiments of the present invention are a processing apparatus, a method, and a related device. The processing apparatus comprises processing modules and N dynamic random access memory (DRAM) memory interfaces, the processing module being connected to the N DRAM memory interfaces by means of a bus, and the processing modules being also directly connected to the N DRAM memory interfaces by means of physical wires, respectively, wherein the processing module is used to determine whether a first command is a DRAM read/write command, and if the first command is a DRAM read/write command, send, by means of a first physical wire, a first indication signal to a first DRAM memory interface, the first DRAM memory interface being used to control the first DRAM rank to enter a working state upon receiving the first indication signal. The present application ensures low power consumption and low time delay of a processing apparatus.

Description

Processing device, method and related equipment

Technical field

This application relates to the technical field of memory processing, and in particular to a processing device, method and related equipment.

Background technique

Memory (Memory) is an important part of data processing equipment (such as computers, mobile terminals, etc.). The function of Memory is to temporarily store the calculation data in the Central Processing Unit (CPU) and exchange it with external storage such as hard disks. data. Since the programs in the CPU are all executed in the memory, the performance of the memory has a great influence on the performance of the data processing device.

In existing data processing equipment, a synchronous DRAM (Dynamic Random Access Memory, DRAM) medium is usually used as a memory to store codes and data required for the operation of a data processing system such as a CPU. DRAM has a larger capacity and a higher read and write speed, which can better meet the memory requirements of the data processing system. However, because DRAM uses capacitor storage, in order to ensure that data is not lost, it is necessary to ensure continuous power supply and refresh during operation, which in turn generates a large amount of power consumption. Data show that the use of DRAM memory power consumption accounts for about 40% of the overall power consumption of the computer system. It can be seen that optimizing the power consumption of the memory system is of great significance to improving the power consumption of the entire data processing system.

In the prior art, the main method to reduce the power consumption of DRAM is to control the DRAM to enter a low power consumption state when the DRAM read and write commands are not monitored for a period of time. However, when the DRAM is in a low power consumption state, the CPU cannot perform the control on the DRAM. Read and write operations; when the CPU needs to read and write data, it needs to wake up the DRAM through a series of operations to exit the aforementioned low power consumption mode to enter the normal working state. Although this method can significantly reduce the power consumption of the system, the time difference in wake-up after the DRAM enters the low-power mode causes the delay of the CPU to read and write data, which ultimately affects the read and write efficiency of the entire data processing device.

Summary of the invention

The embodiment of the present invention provides a processing device, a method and related equipment, which can ensure low power consumption and low time delay in the memory processing process.

In the first aspect, an embodiment of the present invention provides a processing device, which may include, a processing module and N dynamic random access memory DRAM memory interfaces, and a bus is used between the processing module and the N DRAM memory interfaces. And the processing module is also directly connected to the N DRAM memory interfaces through physical connections, where N is an integer greater than or equal to 1; the processing module is used to determine whether the first command is dynamic Random access memory DRAM read and write commands, the first command is a command sent by the processing module through the bus; if the first command is a DRAM read and write command, it is sent to the first DRAM memory interface through the first physical connection A first indicator signal, the first DRAM memory interface is a memory interface corresponding to the first command among the N DRAM memory interfaces, and the first indicator signal is used to instruct the first DRAM module RANK to enter a working state Wherein, the first physical connection is a physical connection between the processing module and the first DRAM memory interface; the first DRAM RANK is the DRAM RANK connected to the first DRAM memory interface; The first DRAM memory interface is configured to control the first DRAM RANK to enter a working state when the first indication signal is received.

In the embodiment of the present invention, by adding a physical direct connection line between the processing module and multiple DRAM memory interfaces in the processing device, when the processing module needs to read or write data from a certain DRAM RANK, it can pass The physical direct connection line with the corresponding DRAM memory interface directly sends an indication signal to the DRAM memory interface to instruct the corresponding DRAM RANK to enter the working state (for example, wake up in advance and exit the low power consumption mode). Different from the processing module in the prior art that needs to pass the command path of the bus, it starts to instruct the DRAM to enter the working state when the first command is sent and arrives at the DRAM memory interface, and after the instruction, a series of operations (such as control Logic, physical layer interface protocol, etc.) can control the DRAM to actually enter the working state, and the duration of the entire wake-up process causes the read and write delay of the first command. In the embodiment of the present invention, while the first command is sent through the bus, the instruction signal can be directly sent to the DRAM memory interface through the added physical direct connection line, thereby instructing the DRAM memory interface to start a series of wake-up operations in advance. Therefore, the waiting time delay after the first command reaches the DRAM memory interface can be greatly reduced or even eliminated, thereby greatly ensuring the low power consumption and low time delay of the processing device.

In a possible implementation manner, the first DRAM memory interface is further configured to: receive the first command issued by the processing module through the bus, and after determining that the first DRAM RANK enters the working state In the case of, the first command is issued to the first DRAM RANK.

In the embodiment of the present invention, the corresponding DRAM memory interface in the processing device not only receives the first instruction signal sent by the processing module through the direct physical connection, but also receives the first command sent by the processing module through the bus (for example, for the first DRAM RANK read and write command), and after confirming that the first DRAM RANK has entered the working state, the command is issued to the first DRAM RANK for corresponding read and write operations.

In a possible implementation manner, the processing module is further configured to: if the first command is a DRAM read/write command, determine the first DRAM memory corresponding to the first command according to the address of the first command interface.

In the embodiment of the present invention, the processing module in the processing device judges which DRAM memory interface the first instruction is specifically sent to by the address in the first command, thereby determining which physical direct connection line is used to send the first instruction signal, and then controls the corresponding The DRAM memory interface wakes up the corresponding DRAM RANK and enters the working state.

In a possible implementation manner, the first indication signal is a high-level signal; the first DRAM memory interface is specifically configured to: when the high-level signal is received, control the first DRAM RANK enters the working state. Optionally, a high-level output can be realized through the first physical connection, thereby instructing the first DRAM memory interface to control the corresponding DRAM Rank to enter the working state by pulling the high level.

In the embodiment of the present invention, the processing module in the processing device sends a high-level signal through a first physical connection. For example, a high-level output can be realized through the first physical connection, thereby sending a high-level signal to the first DRAM. The memory interface instructs and controls the corresponding DRAM RANK to enter the working state, and the first DRAM memory interface can continue to control the first DRAM RANK to remain in the working state while monitoring that the high level is maintained. Therefore, the first DRAM RANK can quickly enter the working state when there is data read and write, and the low power consumption and low latency of the processing device are ensured.

In a possible implementation manner, the first DRAM RANK is a first double-rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR physical interface PHY; A DRAM memory interface is specifically used to: when the DDR controller receives the high-level signal, control the DDR PHY to exit the low power consumption state, and control the first DDR RANK through the DDR PHY Exit the power-off state or self-refresh state.

In the embodiment of the present invention, when the DRAM RANK is DDR RANK, and the DRAM memory interface includes a DDR controller and DDR PHY, the process of controlling the DDR RANK to enter the working state includes first controlling the DDR PHY to exit the DFI low power state, and then exiting the DFI The DDR PHY in the low power consumption state controls the first DDR RANK to exit the power-off state or self-refresh state.

In a possible implementation manner, the processing module is further configured to: when it is not detected that the first command is sent through the bus or when the first DRAM RANK has executed and completed the first command , Sending a second indication signal to the first DRAM memory interface through the first physical connection, the second indication signal is used to instruct the first DRAM RANK to enter a low power consumption state; the first DRAM memory The interface is also used to control the first DRAM RANK to enter a low power consumption state when the second indication signal is received.

In the embodiment of the present invention, when there is no first command to be sent, or when the first command needs to be sent but the corresponding DRAM RANK has been executed, the processing module can connect to the corresponding DRAM memory interface through a physical connection. Send the second indication signal to instruct the corresponding DRAM memory interface to control the corresponding DRAM RANK to enter a low power consumption state after the preset time period, so as to save power consumption. Optionally, the reason why the DRAM memory interface can control the DRAM to enter the low-power state after a preset period of time is that if there is no DRAM command to be executed currently, it does not mean that no new commands will be received in a short time (multiple Command is issued, there may be a short time difference), in order to reduce the frequent wake-up operations caused by entering the low-power state prematurely, you can confirm that no more commands need to be executed after a preset period of time and in the process. Determining to enter a low power consumption state is more conducive to ensuring the low power consumption and low latency of the system.

In a possible implementation manner, the second indication signal is a low-level signal; the first DRAM memory interface is specifically configured to: when the low-level signal is received, control the first DRAM RANK enters a low power consumption state. Optionally, the low-level output can be realized through the first physical connection, thereby instructing the first DDR memory interface to control the corresponding DRAM Rank to enter the working state by pulling the low level.

In the embodiment of the present invention, the processing module in the processing device sends a low-level signal through a first physical connection. For example, a low-level output can be realized through the first physical connection, so as to send a low-level signal to the first DDR. The memory interface instructs and controls the corresponding DRAM RANK to enter the low power consumption state after a preset time period, and the first DDR memory interface can continue to control the first DRAM RANK to maintain the low power consumption state while monitoring the low level maintenance. Therefore, the first DRAM RANK can quickly enter the working state when there is data to read and write, and when there is no data to read and write, it will enter the low power consumption mode after a certain wait, while ensuring the low power consumption and low time of the processing device. Ductility.

In a possible implementation manner, the first DRAM RANK is a first double-rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR physical interface PHY; A DRAM memory interface is specifically used to control the first DDR RANK to enter the power-off state or the self-refresh state through the DDR PHY when the DDR controller receives the low-level signal, and control all The DDR PHY enters a low power consumption state.

In the embodiment of the present invention, when the DRAM RANK is DDR RANK, and the DRAM memory interface includes a DDR controller and DDR PHY, the process of controlling the DDR RANK to enter a low power consumption state includes first controlling the first DDR RANK to exit power off through the DDR PHY State or self-refresh state, and then control DDRPHY to enter a low power state, such as DFI low power state. Optionally, it may also include, after the preset time period, first control the first DDR RANK to exit the power-off state or self-refresh state through the DDR PHY, and then control the DDR PHY to enter and remain in the DFI during the second time period In a low power consumption state, the second time period is a time period during which the first physical connection maintains a low level.

In a possible implementation manner, the first DRAM memory interface is connected to M first DRAM RANKs, where M is an integer greater than or equal to 2; the processing module and the first DRAM memory interface pass through The M first physical connections are directly connected, wherein one first physical connection corresponds to one first DRAM RANK.

In the embodiment of the present invention, when multiple DRAM RANKs are included in the DRAM, that is, when the first DRAM memory interface is connected to and controls multiple DRAM RANKs, since controlling the DRAM to enter the working state or enter the low power consumption state is based on the DRAM RANK, Therefore, multiple physical connections need to be connected between the processing module and the first DRAM memory interface, so that one physical connection can correspondingly control one DRAM RANK, which improves the accuracy of control.

In a possible implementation manner, the device and the first DRAM RANK are on different packaging substrates.

In the embodiment of the present invention, the processing device and the DRAM can be distributed on different chips, that is, the processing device can flexibly expand the DRAM memory to meet different application scenarios; it can also avoid the processing device and the DRAM from being too large on the same chip. , The packaging is difficult to achieve; at the same time, because the DRAM production process is relatively behind the SOC, therefore, the use of external expansion can save costs.

In a second aspect, an embodiment of the present invention provides a processing method, which is characterized in that it includes: a processing module determines whether the first command is a dynamic random access memory DRAM read/write command; if the first command is a DRAM read/write command, The processing module sends a first indication signal to the first DRAM memory interface through the first physical connection; the processing module is connected to the N DRAM memory interfaces through a bus, and the processing module is also connected through the physical connection. It is directly connected to the N DRAM memory interfaces, where N is an integer greater than or equal to 1; the first DRAM memory interface is the memory interface corresponding to the first command among the N DRAM memory interfaces, and the first An indication signal is used to instruct the first DRAM module RANK to enter the working state; wherein, the first physical connection is a physical connection between the processing module and the first DRAM memory interface; the first DRAM RANK is the DRAM RANK connected to the first DRAM memory interface; when the first DRAM memory interface receives the first indication signal, it controls the first DRAM RANK to enter the working state.

In a possible implementation manner, the method further includes: the method further includes: receiving, through the first DRAM memory interface, the first command issued by the processing module through the bus, and When it is determined that the first DRAM RANK enters the working state, the first command is issued to the first DRAM RANK.

In a possible implementation manner, the method further includes: if the first command is a DRAM read/write command, judging the first DRAM memory interface corresponding to the first command according to the address of the first command.

In a possible implementation manner, the first indication signal is a high-level signal; when the first DRAM memory interface receives the first indication signal, the first DRAM RANK is controlled to enter work Status, including:

The first DRAM memory interface controls the first DRAM RANK to enter the working state according to the high-level signal.

In a possible implementation manner, the first DRAM RANK is a first double-rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR physical interface PHY; the first The DRAM memory interface controls the first DRAM RANK to enter the working state according to the high-level signal, which includes: when the DDR controller receives the high-level signal, controls the DDR PHY to exit DFI low Power consumption state, and control the first DDR RANK to exit the power-off state or the self-refresh state through the DDR PHY.

In a possible implementation manner, the method further includes: when it is not detected that the first command is sent through the bus or when the first DRAM RANK has executed and completed the first command, The processing module sends a second indication signal to the first DRAM memory interface through the first physical connection, where the second indication signal is used to instruct the first DRAM RANK to enter a low power consumption state; When receiving the second indication signal, a DRAM memory interface controls the first DRAM RANK to enter a low power consumption state.

In a possible implementation manner, the second indication signal is a low level signal; when the first DRAM memory interface receives the second indication signal, it controls the first DRAM RANK to enter low The power consumption state includes: when the first DRAM memory interface receives the low-level signal, controlling the first DRAM RANK to enter a low power consumption state.

In a possible implementation manner, the first DRAM RANK is a first double-rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR physical interface PHY; When a DRAM memory interface receives the low-level signal, controlling the first DRAM RANK to enter a low-power consumption state includes: when the DDR controller receives the low-level signal, The DDR PHY controls the first DDR RANK to enter a power-off state or a self-refresh state, and controls the DDR PHY to enter a low power consumption state.

In a possible implementation manner, the processing module and the N DRAM memory interfaces are on the same packaging substrate, and are on a different packaging substrate from the first DRAM RANK.

In the third aspect, this application provides a semiconductor chip, which may include:

The foregoing first aspect and the processing device provided in combination with any one of the foregoing first aspect implementation manners, a central processing unit coupled to the processing device, and a memory external to the processing device are provided.

In a fourth aspect, this application provides a semiconductor chip, which may include:

The foregoing first aspect and a processing device provided in combination with any one of the foregoing first aspects.

On the fifth aspect, the present application provides a system-on-chip SoC chip. The SoC chip includes the above-mentioned first aspect and the processing device provided in combination with any one of the above-mentioned first aspects, coupled to the center of the processing device. The processing unit and the external memory of the processing device. The chip system can be composed of chips, or include chips and other discrete devices.

In a sixth aspect, the present application provides a processing device system. The chip system includes: a processing device including the first aspect described above and the processing device provided in combination with any one of the foregoing first aspects, and including a processing device coupled to the processing device The central processing unit and the external memory chip of the processing device. The chip system can be composed of chips, or include chips and other discrete devices.

In a seventh aspect, the present application provides a terminal device, which includes the processing device provided in the foregoing first aspect and any one of the implementation manners of the foregoing first aspect, and an external memory of the processing device, wherein: The processing device and the external memory of the processing device are provided in different semiconductor chips.

In an eighth aspect, the present application provides a terminal device, which includes the processing device provided in the first aspect and any one of the implementation manners of the first aspect, the external memory of the processing device, and the coupling In the central processing unit of the processing device. The external memory is used to store necessary program instructions and data, and the central processing unit is used to run a general operating system necessary for the terminal device, and is used to couple with the processing device to complete related processing functions in the processing device. The terminal device may also include a communication interface for the terminal device to communicate with other devices or a communication network.

In a ninth aspect, the present application provides a computer storage medium that stores a computer program, and when the computer program is executed by a processor, it can implement any one of the above second aspect and in combination with the above second aspect The process performed by the processing module and the first DRAM memory interface in the processing method provided by the implementation manner.

In a tenth aspect, an embodiment of the present invention provides a computer program, the computer program includes instructions, when the computer program is executed by a computer, the computer can execute the second aspect and any combination of the second aspect described above. The process performed by the processing module and the first DRAM memory interface in the processing method provided by the method.

Description of the drawings

Fig. 1 is a hardware structure diagram of a SoC+DRAM provided by an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a processing device provided by an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of another processing device provided by an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of another processing device provided by an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of an early wake-up module provided by an embodiment of the present invention.

Fig. 6 is a schematic flowchart of a processing method provided by an embodiment of the present invention.

detailed description

The embodiments of the present invention will be described below in conjunction with the drawings in the embodiments of the present invention.

The terms "first", "second", "third" and "fourth" in the specification and claims of this application and the drawings are used to distinguish different objects, not to describe a specific order . In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes unlisted steps or units, or optionally also includes Other steps or units inherent to these processes, methods, products or equipment.

Reference to "embodiments" herein means that a specific feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art clearly and implicitly understand that the embodiments described herein can be combined with other embodiments.

The terms "component", "module", "system", etc. used in this specification are used to denote computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, the component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program, and/or a computer running on a processor. Through the illustration, both the application running on the computing device and the computing device can be components. One or more components may reside in processes and/or threads of execution, and components may be located on one computer and/or distributed among two or more computers. In addition, these components can be executed from various computer readable media having various data structures stored thereon. A component can be based on a signal having one or more data packets (for example, data from two components interacting with another component between a local system, a distributed system, and/or a network, such as the Internet that interacts with other systems through signals) Communicate through local and/or remote processes.

First, some terms in this application are explained to facilitate the understanding of those skilled in the art.

(1) System-on-Chip (SoC), SoC is called system-on-chip, also called system-on-chip, which means that it is a product, an integrated circuit with a dedicated target, which contains a complete system and has embedded software The entire contents of. At the same time, it is a kind of technology to realize the whole process from determining the system function to dividing the software/hardware and completing the design.

(2) Random Access Memory (RAM), used to store and save data. It can be read and written at any time. RAM is usually used as a temporary storage medium for operating systems or other running programs (which can be called system memory). RAM cannot retain data when the power is turned off. If you need to save data, you must write them into a long-term storage (such as a hard disk).

(3) Random Access Memory RAM can be further divided into two categories: Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The basic principles of the two have the same place. Both store the charge inside the memory. Among them, the structure of SRAM is more complicated, the capacity per unit area is small, and the access speed is very fast; DRAM has a simple structure and stores per unit area. The capacity is relatively large, and the access time is slower than that of SRAM. At the same time, because the structure of DRAM is relatively simple, the stored charge will gradually disappear over time, so it needs to be recharged regularly (Refresh) to maintain the data stored in the capacitor.

(4) Double Data Rate Synchronous Dynamic Random Access Memory (Dynamic Random Access Memory, DDR SDRAM), abbreviated as DDR, DDR memory is developed on the basis of SDRAM memory, and still uses the SDRAM production system. As far as memory manufacturers are concerned, they only need to make slight improvements to the equipment for manufacturing ordinary SDRAM to realize the production of DDR memory, which can effectively reduce costs. Compared with the traditional single data rate, DDR technology implements two read/write operations in one clock cycle, that is, one read/write operation is performed on the rising and falling edges of the clock.

(5) Time delay (Latency), its unit is generally ns. The time delay in this application may include one-way delay (One-way Latency) and round trip delay (Round Trip Latency). Among them, the Latency for the DRAM write command in this application refers to the time interval between the processing module sending the first command (DRAM write command) and the DRAM writing data according to the DRAM write command, which can be understood as a one-way delay; The latency of the DRAM read command refers to the time interval between the processing module sending the first command (DRAM read command) and the DRAM feeding back the read data to the processing module according to the DRAM read command and the processing module receiving the data, which can be understood as the round trip delay.

(8) Module RANK, the "R" in the "module configuration" means "RANK", which can be controlled by the chip select signal to select a die for access. "2R" refers to 2 RANKs (Number of ranks of memory installed). There are usually two types of "1R" and "2R"; in order to ensure a certain memory capacity and bandwidth utilization in some access scenarios, the current LPDDRx series of memory usually uses a module with two RANK architectures, and multiple modules Parallel groups work in parallel to meet SOC bandwidth requirements. Correspondingly, the DRAM connected to a DRAM interface in this application may be a memory structure including two RANKs, of course, it may also be a structure including one RANK or even multiple RANKs, which is not specifically limited in this application.

In order to facilitate the understanding of the embodiments of the present invention, the following takes DRAM as DDR as an example to exemplarily enumerate the specific technical problems to be solved by the embodiments of the present invention and corresponding actual application scenarios.

As shown in FIG. 1, FIG. 1 is a hardware structure diagram of a SoC+DRAM provided by an embodiment of the present invention. For example, the system-on-chip SoC of a mobile terminal (smartphone, palmtop computer, etc.) consists of data processing subsystems such as the application processor 120, the media system 122, and the communication system 124 through the bus 200, the memory controller Memory Controller 300, and the DDR physical interface PHY 302 A system connected to off-chip DRAM 304. Off-chip DRAM 304 serves as the access center for SoC programs and data, and memory controllers Memory Controller 300 and DDR PHY 302 serve as access to off-chip DRAM 304. Their energy efficiency is critical to the energy efficiency of mobile terminals.

In the current mobile terminal SoC+DRAM design and use plan, in order to save DDRPHY 302 power consumption, the DDRPHY interface standard protocol (DFI protocol) has a defined low power interface (DFI Low Power interface); in order to save DRAM 302 power consumption, DRAM It uses Low Power Double Data Rate DRAM, which has two low power consumption modes: Power Down and Self refresh. The current methods of using these low-power features and the corresponding problems are as follows:

(1) Monitor whether there is a command to read and write DRAM in the Memory Controller 300. If there is no command to read or write DRAM for a period of time (timing time value register is configurable), the Memory Controller 300 controls DDR PHY 302 to enter DFI Low Power, DRAM 304 enters the power-off mode Power Down, and it has timed for a longer period of time (the timer time value register can be configured) without a command to read and write DRAM, then the Memory Controller further controls the DRAM 304 to enter Self Refresh;

(2) When the command to read and write DRAM reaches Memory Controller 300, Memory Controller 300 will control DDR PHY 302 to exit DFI Low Power and DRAM 304 to exit Power Down&Self Refresh;

(3) However, if you want to exit DFI Low Power, you need to go through a series of control exits from the DFI Low Power step in the Memory Controller300 state machine. In addition, the Memory Controller300 and DDRPHY 302 need to exchange handshake control to exit DFI Low Power. Both will cause a delay in exiting DFI Low Power;

(4) And to exit DRAM Power Down & Self Refresh, it takes tXP (the delay from DRAM exits Power Down to accept valid commands) and tXSR (the delay from DRAM exits Self Refresh to accept valid commands) specified in the DRAM protocol respectively;

(5) Since DRAM 304 cannot be read and written during the process of exiting the above-mentioned low-power state, then when DDRPHY302 and DRAM304 are in the above-mentioned low-power state, the system-side Masters (such as application processor, media, communication and other subsystems) ) The read DRAM operation will have a large latency loss;

(6) Therefore, DDR PHY 302 and DRAM 304 are usually not allowed to advance and retreat DFI Low Power and DRAM Power Down&Self Refresh frequently, so as not to affect performance; but DDR PHY 302 and DRAM 304 do not frequently advance and retreat DFI Low Power and DRAM Power Down&Self Refresh. The time spent in the low-power state is relatively small, leading to an increase in power consumption; thus, both situations affect the energy efficiency ratio.

Through actual business tests, in order to balance performance and power consumption, on the premise of meeting performance requirements, a compromise is configured between waiting to enter DRAM Power Down time and waiting to enter DRAM Self Refresh time to control advance and retreat DFI Low Power and DRAM Power Down&Self Refresh frequency To achieve the best energy efficiency ratio achievable under the existing technical solutions.

However, because it takes a long time to exit DFI Low Power and DRAM Power Down & Self Refresh, in order to meet performance requirements when weighing performance and power consumption, the waiting time for entering DRAM Power Down and waiting for entering DRAM Self Refresh cannot be configured to be small. It is that if the configuration is small, it is easy to enter these low-power states, resulting in an increase in the number of exits from these low-power consumption per unit time, and the total time to exit these low-power consumption per unit time = the time required for one exit *The number of exits, but the DRAM cannot be read and written during the process of exiting these low-power states, so the time percentage of the DRAM that can be read and written per unit time becomes smaller, which may cause the Latency not to meet the requirements and make the system performance requirements If it cannot be satisfied, at this time, the DDR frequency needs to be increased to compensate for Latency, which may result in more waste of power consumption. However, if the waiting time to enter DRAM Power Down and the waiting time to enter DRAM Self Refresh are configured too large, the proportion of low power consumption states will be smaller, and the power consumption of the system will be higher.

In summary, the technical problems to be solved in this application include how to reduce the latency caused by the time of exiting DFI Low Power and DRAM Power Down & Self Refresh, that is, how to ensure both low power consumption and low latency of the memory system.

Based on the foregoing, the processing apparatus and related equipment provided in the embodiments of the present invention are described below. Please refer to FIG. 1. FIG. 2 is a schematic structural diagram of a processing device provided by an embodiment of the present invention. The processing device 40 may include one or more processing modules 401 (2 are taken as an example in FIG. 2) and N dynamic modules. Random access memory DRAM memory interface 402 (four as an example in FIG. 2), where any processing module 401 and N DRAM memory interfaces 402 are connected by a bus, and any processing module 401 is also physically connected The lines are respectively directly connected to the N DRAM memory interfaces 402, where N is an integer greater than or equal to 1. Optionally, at least one DRAM RANK 403 is connected to each DRAM memory interface, and one or more processing modules 401 and N DRAM memory interfaces can be located on an integrated circuit substrate, that is, the processing device in the embodiment of the present invention 40. The off-chip DRAM RANK 403 uses the DRAM memory interface 402 as the access center for the programs and data of the processing module 401. among them,

The processing module 401 (which can be any one of 401 in FIG. 2) is used to determine whether the first command is a dynamic random access memory DRAM read and write command, and the first command is a command sent by the processing module through the bus; if The first command is a DRAM read and write command, and a first instruction signal is sent to a first DRAM memory interface through a first physical connection, and the first DRAM memory interface is one of the N DRAM memory interfaces and the first instruction signal. Command the corresponding memory interface, the first indication signal is used to instruct the first DRAM module RANK to enter the working state; wherein, the first physical connection is the connection between the processing module and the first DRAM memory interface Physical connection. It should be noted that any DRAM memory interface 402 in FIG. 2 may be the first DRAM memory interface, and any DRAM RANK in FIG. 2 may be the first DRAM RANK. In this embodiment of the present invention, the first command The memory interface to be sent is the first DRAM memory interface, and the DRAM RANK connected to the first DRAM memory interface is the first DRAM RANK. Any processing module 401 in the embodiment of the present invention may be a processor, a coprocessor, a modem, a multimedia system, and other devices or devices with DRAM read and write capabilities, which is not specifically limited in this application.

Specifically, in the embodiment of the present invention, the timing for the processing module 401 to determine whether the first command is a dynamic random access memory DRAM read/write command may include sending the first command through the bus, and may also include the preset before sending the command through the bus. The time may also include a specified period of time after the first command is sent through the bus. The timing of the trigger to determine whether the first command is a DRAM read/write command can be flexibly changed according to actual application scenarios, which is not specifically limited in this application. It can be understood that triggering the judgment at the same time or before the preset time when the first command is sent through the bus is more conducive to reducing the time delay of the first command.

In the embodiment of the present invention, judging whether the first command is a DRAM read and write command may include the following three cases: 1. Only judge whether the first command is a DRAM read command, that is, when the first command is sent through the bus, it is judged Whether the first command is a DRAM read command, if so, continue to perform subsequent judgments and instructions; 2. Only judge whether the first command is a DRAM write command, that is, when the first command is sent through the bus, judge whether the first command is It is a DRAM write command. If it is, continue to perform subsequent judgments and instructions; 3. At the same time, judge whether the first command is a DRAM read or write command, that is, when the first command is sent through the bus, judge whether the first command is DRAM Read command or DRAM write command, if it is DRAM read command or DRAM write command, continue to perform subsequent judgment and instruction operations. It should be noted that, because the read operation of DRAM usually requires timely read feedback of DRAM, otherwise it will cause read delay. In some scenarios, the write operation of DRAM does not require timely write feedback of DRAM. Therefore, this The application does not specifically limit which of the above three situations to take, and different judgment conditions can be adopted according to different application scenarios.

The first DRAM memory interface 402 is configured to control the first DRAM RANK to enter a working state when the first indication signal is received. Among them, controlling the first DRAM RANK to enter the working state can be instructing the first DRAM RANK to exit the low power consumption state, or it can be confirming that the first DRAM RANK is currently working, that is, no matter what state the first DRAM RANK was in before, as long as it can It is sufficient to ensure that it can be controlled to enter the working state when the first indication signal is received.

In this application, the working state and low power consumption state of DRAM (DRAM RANK) are two different states. When the DRAM RANK is in the working state, the DRAM RANK can be read and written by the processing module in this application, that is, data can be read or written from the DRAM RANK; when the DRAM RANK is in a low power consumption state, The DRAM RANK cannot be read and written by the processing module in this application, that is, data cannot be read or written from the DRAM RANK; and when the DRAM RANK is in a low-power state, the power consumption is lower than its In working condition. For example, when DRAM RANK is DDR RANK, the low power consumption state of DDR RANK is Power Down or Self Refresh: and its working state refers to exiting the aforementioned Power Down or Self Refresh state, that is, it is not in Power Down or Self Refresh. Correspondingly, the working state of DDR PHY means that it can control the DRAM (DRAM RANK) it is connected to, read and write, and its low power consumption state means that it cannot be connected to the DRAM (DRAM RANK). DRAM RANK) performs control such as reading and writing. For example, the DDR PHY low-power mode is specifically the DFI low-power mode, and the working state refers to exiting the aforementioned DFI low-power mode. among them,

Power Down: When there is no read and write access to DRAM, it is a low power consumption state of DRAM that can turn off the DRAM clock for a period of time, but needs to be periodically exited and refreshed by the SOC control (the refresh cycle is changed by the SOC according to the environmental temperature change) To maintain data in DRAM;

Self Refresh: When there is no read/write access to DRAM, it is a low power consumption state of DRAM that can always let DRAM control refresh by itself (the refresh cycle is changed by DRAM according to changes in ambient temperature), and does not need to be periodically exited by SOC control. The SOC only needs to maintain the DRAM port signal to make the DRAM in a self-refresh state.

Optionally, the first DRAM memory interface 402 is further configured to: receive the first command issued by the processing module 401 via the bus, and when it is determined that the first DRAM RANK 403 enters the working state, set the first command A command is issued to the first DRAM RANK 403. That is, after the first DRAM memory interface 402 receives the first command sent by the processing module 401 through the bus, at this time, because the first DRAM RANK has already performed the wake-up operation in advance (there are two situations, the first is that the wake-up is completed, the first The second type is awakened in advance but not completed yet). Therefore, only when it is determined that the first DRAM RANK 403 enters the working state, the first command can be normally sent to the first DRAM RANK for read and write operations. In the embodiment of the present invention, the corresponding DRAM memory interface in the processing device not only receives the first indication signal sent by the processing module through the direct physical connection, but also receives the first command sent by the processing module through the bus (for example, for The read and write command of the first DRAM RANK), and after confirming that the first DRAM RANK has entered the working state, the command is issued to the first DRAM RANK for corresponding read and write operations.

In a possible implementation, if the first command is a DRAM read and write command, the processing module 401 is further configured to, if the first command is a DRAM read and write command, determine the address of the first command according to the address of the first command. The first DRAM memory interface corresponding to the first command. In the embodiment of the present invention, the processing module 401 in the processing device 40 determines which DRAM memory interface the first command is sent to by using relevant valid information (such as address information) in the first command, thereby determining which physical direct connection is passed The line sends the first indication signal, and then controls the corresponding DRAM memory interface to wake up the corresponding DRAM RANK and enter the working state.

In a possible implementation manner, the first indication signal is a high-level signal; the first DRAM memory interface is specifically configured to: when the high-level signal is received, control the first DRAM RANK enters the working state. Optionally, the processing module 401 may implement a high-level output through the first physical connection, and maintain the high-level output for a first period of time; the first DRAM memory interface 402 is specifically used to The high-level output controls the first DRAM RANK 403 to enter and maintain the working state in the first time period. It is understandable that the specific indication manner of the first indication signal in this application can be multiple, for example, the preset indication signal, the preset indication information, etc., can all instruct the first DRAM memory interface to perform an early wake-up operation. However, the instruction method in the embodiment of the present invention is that the processing module 401 in the processing device 40 sends a high-level signal through the first physical connection, for example, to achieve a high-level output, thereby pulling a high level to the first The DRAM memory interface 402 instructs to control the corresponding DRAM RANK 403 to enter the working state, and the first DRAM memory interface will continue to control the first DRAM RANK 403 to remain in the working state while monitoring that the high level is maintained. Therefore, the first DRAM RANK can quickly enter the working state when there is data reading and writing, and at the same time, the low power consumption and low latency of the processing device can be ensured.

In a possible implementation, the first DRAM RANK 403 is the first double-rate synchronous dynamic random access memory DDR RANK; as shown in FIG. 3, FIG. 3 is a structure of another processing device provided by an embodiment of the invention In a schematic diagram, the first DRAM memory interface 402 includes a DDR controller and a DDR physical interface PHY; the first DDR memory interface 402 is specifically used to control the DDR when the DDR controller receives the high-level signal. The PHY exits the DFI low power consumption state, and controls the first DDR RANK403 to exit the power-off state or the self-refresh state through the DDRPHY. That is, when DRAM RANK is DDR RANK, the DRAM memory interface includes DDR controller and DDR PHY, then the specific process of controlling DDR RANK to enter the working state includes first controlling DDR PHY to exit the low-power state, such as the DDR physical layer interface (The DDR PHY Interface, DFI) low power consumption state, and then control the first DDR RANK to exit the power-off state or self-refresh state by exiting the DDR PHY in the DFI low power state.

In a possible implementation manner, the processing module 401 is further configured to use the first physical connection when sending the first command is not detected or when the first command is not a DRAM read/write command. The line sends a second indication signal to the first DRAM memory interface 402, where the second indication signal is used to instruct the first DRAM RANK 403 to enter a low power consumption state; the first DRAM memory interface 402 is used for receiving the second In the case of an indication signal, the first DRAM RANK 403 is controlled to enter a low power consumption state. Optionally, when the first DRAM memory interface 402 receives the second indication signal, it may control the first DRAM RANK 403 to enter the low power consumption state after a preset time period, for example, the preset time period is 100ns, 200ns Etc., this application does not specifically limit this. That is, when there is no first command to send, or there is a first command to send but the corresponding DRAM RANK has been executed, the processing module can send a second instruction to the corresponding DRAM memory interface through a physical connection The signal indicates that the corresponding DRAM memory interface controls the corresponding DRAM RANK to enter a low power consumption state immediately or after a preset period of time, so as to save power consumption. Among them, the reason why the DRAM is controlled to enter the low-power state after the preset time period is that if there is no DRAM command to be executed currently, it does not mean that no new command will be received in a short time (multiple commands are issued, there may be a short In order to reduce the frequent wake-up operations caused by entering the low-power state too early, you can enter the low-power state by confirming that there are no more commands to be executed after a preset period of time. , Which is more conducive to ensuring the low power consumption and low latency of the system. Optionally, after the first DRAM memory interface receives the second indication signal, other conditions are also judged to confirm that there will be no more DRAM commands to be executed in a short period of time, and then further control the DRAM to enter the low state. Power consumption mode.

In a possible implementation manner, the second indication signal is a low-level signal; the first DRAM memory interface is specifically configured to: when the low-level signal is received, control the first DRAM RANK enters a low power consumption state. Optionally, the processing module 401 may implement low-level output through the first physical connection, and maintain the low-level output during the second time period; the first DRAM memory interface 402 is specifically used to Low-level output, after the preset period of time, the first DRAM RANK 403 is controlled to enter and maintain a low power consumption state in the second period of time. In the embodiment of the present invention, the processing module in the processing device sends a low-level signal through the first physical connection, for example, realizes low-level output, thereby instructing the first DRAM memory interface to control the corresponding DRAM by pulling the low level. The RANK enters the low power consumption state, and the first DRAM memory interface continues to control the first DRAM RANK to maintain the low power consumption state while monitoring that the low level is maintained. Thus, the first DRAM RANK can quickly enter the working state when there is data read and write, and when there is no data read or write, it can enter the low power consumption mode immediately or after a certain wait, while ensuring the low power consumption of the processing device And low latency.

In a possible implementation, the first DRAM RANK 403 is the first double-rate synchronous dynamic random access memory DDR RANK; referring to FIG. 3, the first DRAM memory interface 402 includes a DDR controller and a DDR physical interface PHY; The first DRAM memory interface 402 is specifically configured to control the first DDR RANK to enter the power-off state or the self-refresh state through the DDR PHY when the DDR controller receives the low-level signal, and Control the DDR PHY to enter a low power consumption state. Optionally, the first DRAM memory interface 402 is specifically configured to control the first DRAM through the DDR PHY after the preset period of time when the DDR controller receives the low-level output. A DDR RANK enters a power-off state or a self-refresh state, and controls the DDR PHY to enter and maintain the DFI low power consumption state during the second time period. That is, when DRAM RANK is DDR RANK, and the DRAM memory interface includes DDR controller and DDR PHY, the process of controlling DDR RANK to enter the low power consumption state includes, immediately or after the preset time period, first through DDR PHY control The first DDR RANK exits the power-off state or the self-refresh state, and then controls the DDR PHY to enter and maintain the DFI low power consumption state in the second time period. The second time period is when the first physical connection maintains a low level period.

In a possible implementation manner, the first DRAM memory interface 402 is connected to M first DRAM RANKs, where M is an integer greater than or equal to 2; the processing module 401 and the first DRAM memory interface 402 pass through M RANKs. The first physical connection is directly connected, where one first physical connection corresponds to a first DRAM RANK. In the embodiment of the present invention, when multiple DRAM RANKs are included in the DRAM, that is, when the first DRAM memory interface is connected to and controls multiple DRAM RANKs, the DRAM RANK is the unit of controlling the DRAM to enter the working state or enter the low power consumption state. Therefore, multiple physical connections need to be connected between the processing module and the first DRAM memory interface, so that one physical connection can control one DRAM RANK correspondingly, and improve the accuracy of control.

In a possible implementation manner, the chip and the first DRAM RANK are on different packaging substrates. In the embodiment of the present invention that shows that the chip protected by this application is separated from the memory, the processing device and the DRAM can be distributed on different chips, that is, the processing device can flexibly expand the DRAM memory to meet different application scenarios; It can also avoid the problem that the processing device and the DRAM are too large on the same chip and the packaging is difficult to achieve; at the same time, because the DRAM production process is relatively behind the SOC, the use of external expansion can save costs.

Because the processing module 401 of the processing device 40 in this application can be any processing device or processing device (such as a processor, a coprocessor, a modem, a multimedia system, etc.) that has the ability to read and write to DRAM. Therefore, the processing module 401 in the present application not only implements the corresponding functions of the embodiments in FIGS. 2 to 3, but also needs to implement the functions of a processor, a coprocessor, a modem, a multimedia system, etc. Therefore, in order not to affect the function of the processing module as the aforementioned device or device, the embodiment of the present invention provides a method of adding an early wake-up module 110 (Fast Wake Up module) to the processing module 401 to implement the early wake-up function of the processing module 401.

Please refer to FIG. 4, which is a schematic structural diagram of another processing device provided by an embodiment of the present invention. In FIG. 4, the processing modules 401 are Master100, Master102, and Master104 as an example, and the DRAM memory interface 402 is Memory Controller 300A+ DDR PHY 302A, Memory Controller 300B+DDR PHY 302B, Memory Controller 300C+DDR PHY 302C and Memory Controller 300D+DDR PHY 302D as examples, take DRAM 304A, DRAM 304B, DRAM 304C, DRAM 304D corresponding to the DRAM memory interface as examples. And taking the judgment condition of whether it is a DRAM read command as an example, how the processing device implements the early wake-up function in this application is described based on actual application scenarios. According to the functions performed by different functional modules in the processing device 40 in time sequence, the following steps may be included:

1. Add a Fast Wake Up110 module (integrated in these Maters subsystems) at the exit of Latency-sensitive Masters (100, 102, 104), and determine whether it is a read command to access DRAM based on the command address and attributes, and if so, go further According to the command address, determine which channel and rank to read DRAM;

2. Each Fast Wake Up module 110 will generate an indication signal for each rank of each channel to request exit DFI Low Power and DRAM Power Down & Self Refresh, as shown in Figure 4: ch0_rank0_exit and ch0_rank1_exit are the rank0 and rank0 of requesting channel0, respectively The indication signal for rank1 to exit low power consumption is hardwired from the Fast Wake Up module 110 to the Memory Controller (300A) of channel 0; ch1_rank0_exit and ch1_rank1_exit are the indication signals for requesting rank0 and rank1 of channel1 to exit low power consumption, respectively. Hard-wired from the Fast Wake Up module 110 to the Memory Controller (300B) of channel1; ch2_rank0_exit and ch2_rank1_exit are indication signals for requesting rank0 and rank1 of channel2 to exit the low-power consumption, and hardwired directly from the Fast Wake Up module 110 Connected to the Memory Controller (300C) of channel2; ch3_rank0_exit and ch3_rank1_exit are indication signals for requesting rank0 and rank1 of channel3 to exit low power consumption, and are hard-wired from the Fast Wake Up module 110 to the Memory Controller (300D) of channel3;

3. When the Fast Wake Up module 110 does not detect a read command to access a certain rank of a certain channel, it will exit the channel's request for that rank. DFI Low Power and DRAM Power Down&Self Refresh indicator signals are maintained low, and wait for detection At that time, the indicator signal of the rank of the channel will be pulled high, and the Memory Controller (300A, 300B, 300C, 300D) will control the corresponding channel to exit DFI Low Power and the corresponding channel+rank to exit DRAM Power Down&Self Refresh according to the raised indicator signal;

In the embodiment of the present invention, the Fast Wake Up module 110 (integrated in these Maters subsystems) is added at the exit of the Latency-sensitive Masters (100, 102, 104) to identify read commands to access DRAM in advance and use direct connection Control the read command in advance before it reaches the Memory Controller 300 (the advance amount is the command path delay of Masters (100, 102, 104) to the Memory Controller 300 minus the direct connection delay) to wake up the DFI Low Power of the corresponding channel and the corresponding channel+rank DRAM Power Down&Self Refresh, so that after the DRAM read command reaches the Memory Controller 300, the time required to exit the low power feature is shortened, thereby reducing the impact of the low power feature on latency, and then waiting to enter DFI low power, DRAM Power Down time and waiting to enter the DRAM Self Refresh time configuration can be reduced, advance and retreat DFI low power and DRAM Power Down&Self Refresh can be more frequent, and ultimately achieve the purpose of improving energy efficiency;

In the embodiment of the present invention, the exit low-power consumption indication signal is divided into channels and ranks, so that other channel+ranks are not awakened when they are not accessed, thereby achieving the purpose of saving power consumption; and whether Fast Wake Up is enabled The function register can be configured to realize the effect of selecting whether to enable or not according to the actual business scenario, so as to achieve the best energy efficiency ratio of the corresponding scenario; further, the maintenance time register is configurable after the exit low power consumption indicator signal is pulled high to realize the Cancellation is too early and when the command reaches Memory Controller 300, Memory Controller 300 has re-entered DFI Low Power and DRAM Power Down&Self Refresh, so as to avoid the maintenance time being too long and cause DFI Low Power and DRAM Power Down&Self Refresh to be delayed next time. Effect, so as to achieve the purpose of performance improvement and power consumption reduction.

As a refinement of part of the content in FIG. 4, FIG. 5 is a schematic structural diagram of an early wake-up module provided by an embodiment of the present invention. The early wake-up module 110 may be located in a processing module 401. The processing module 401 may be a processor, a coprocessor, a modem, a multimedia system, and other devices or devices with DRAM read and write capabilities. The early wake-up module includes a detector 500, an address index code register 502, a comparator 504, a timer 506, and a register 508 for controlling and maintaining level signals. among them,

1. The detector 500 judges whether it is a read command to access DRAM according to the address and attributes of the first command (command_info from Masters (100, 102, 104) to the Fast Wake Up module); if the read command channel is not Merged, the command_info connected to the Fast Wake Up module 110 can only be a read command related signal, so you only need to judge whether it is a command to access DRAM according to the command address and attribute signal; if the read and write command channels are merged (some Master designs In order to reduce the connection with the downstream module, the read and write command channels will be combined. At this time, the read and write time-sharing command lines are multiplexed. The read and write type indicates the signal to distinguish the read command or the write command). The command_info (that is, part or all of the information in the first command) connected to the command_info of the Fast Wake Up module 110 determines whether it is a read command, and then determines whether it is a read command to access DRAM according to the command address and attribute signal.

2. The address index code register 502, according to the channel arrangement order and channel interleaving granularity information in the address mapping information address_map_info (configured by the register), obtains the bit field indicating which channel belongs to which bit field of the address, and the code of each channel;

3. The address index code register 502, according to the rank mapping and rank interleaving information in the address mapping information address_map_info (configured by the register), obtains the bit field indicating which rank belongs to which bit field of the address, and the code of each rank;

4. After the comparator 504 determines that it is a read command to access the DRAM, it first compares the bits of the read command address of the access DRAM indicating which channel it belongs to and compares it with the codes of each channel to find out which channel the read DRAM command is accessing ；

5. The comparator 504 then compares the bit indicating which rank belongs to the read command address of the access DRAM with the code of each rank to find out which rank the read DRAM command is accessing;

6. The register 508 that controls and maintains the level signal pulls the exit low power consumption indication signal of the channel+rank accessed by the read DRAM command to high, and triggers the corresponding channel+rank timer 506 to be determined by wakeup_keep_info (configured by the register) The number of cycles starts to count down. Before counting to 0, the exit low power consumption indication signal of the corresponding channel+rank remains high. After counting to 0, the exit low power consumption indication signal of the corresponding channel+rank is pulled down;

7. When fast_wakeup_en (configured by the register) of the register 508 that controls and maintains the level signal is 0, the exit low power consumption indication signal of each channel+rank is fixed to low; when it is 1, it is determined by the above judgment and control process;

It is understandable that the specific system architecture applied by the embodiment of the present invention includes but is not limited to the architecture based on the processing device in Figures 2 to 4, as long as the processing device in this application can be applied to perform early wake-up related processing architectures. The scope of protection and coverage of this application.

Please refer to FIG. 6. FIG. 6 is a schematic flowchart of a processing method provided by an embodiment of the present invention. The processing method is applicable to any of the processing apparatuses in FIGS. 2 to 5 and the equipment including the processing apparatus. The method may include the following steps S601-S604.

S601: The processing module determines whether the first command is a dynamic random access memory DRAM read and write command;

S602: If the first command is a DRAM read and write command, the processing module sends a first instruction signal to the first DRAM memory interface through the first physical connection;

The processing module is connected to the N DRAM memory interfaces through a bus, and the processing module is also directly connected to the N DRAM memory interfaces through physical connections, where N is an integer greater than or equal to 1; A DRAM memory interface is the memory interface corresponding to the first command among the N DRAM memory interfaces, and the first indication signal is used to instruct the first DRAM module RANK to enter the working state; wherein, the first physical The connection is a physical connection between the processing module and the first DRAM memory interface; the first DRAM RANK is the DRAM RANK connected to the first DRAM memory interface;

S603: When receiving the first indication signal, the first DRAM memory interface controls the first DRAM RANK to enter a working state.

S604: Receive the first command issued by the processing module through the bus through the first DRAM memory interface, and when it is determined that the first DRAM RANK enters the working state, set the first command The command is issued to the first DRAM RANK.

In a possible implementation manner, the first indication signal is a high-level signal; when the first DRAM memory interface receives the first indication signal, the first DRAM RANK is controlled to enter work The state includes: the first DRAM memory interface controls the first DRAM RANK to enter the working state according to the high-level signal.

In a possible implementation manner, the first DRAM RANK is a first double-rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR physical interface PHY; A DRAM memory interface controls the first DRAM RANK to enter the working state according to the high level signal, including: the DDR controller controls the DDR PHY to exit DFI when the high level signal is received Low power consumption state, and controlling the first DDR RANK to exit the power-off state or the self-refresh state through the DDR PHY.

It should be noted that, for the specific process in the processing method described in the embodiment of the present invention, please refer to the related description in the embodiment of the present invention described in FIG. 1 to FIG. 4, which will not be repeated here.

An embodiment of the present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program includes part or all of the steps of any one of the above method embodiments when executed.

The embodiment of the present invention also provides a computer program, the computer program includes instructions, when the computer program is executed by a computer, the computer can execute part or all of the steps of any processing method.

In the above-mentioned embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in an embodiment, reference may be made to related descriptions of other embodiments.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that this application is not limited by the described sequence of actions. Because according to this application, some steps may be performed in other order or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

In the several embodiments provided in this application, it should be understood that the disclosed device may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated. To another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical or other forms.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc., specifically a processor in a computer device) execute all or part of the steps of the above methods in the various embodiments of the present application. Among them, the aforementioned storage media may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviation: ROM) or Random Access Memory (Random Access Memory, abbreviation: RAM), etc. A medium that can store program codes.

Claims

A processing device, characterized in that it includes a processing module and N dynamic random access memory DRAM memory interfaces, the processing module and the N DRAM memory interfaces are connected by a bus, and the processing module is also connected through The physical wires are respectively directly connected to the N DRAM memory interfaces, where N is an integer greater than or equal to 1;

The processing module is used to:

Judging whether the first command is a dynamic random access memory DRAM read/write command, the first command being a command sent by the processing module through the bus;

If the first command is a DRAM read and write command, a first instruction signal is sent to the first DRAM memory interface through the first physical connection, and the first DRAM memory interface is the first instruction signal of the N DRAM memory interfaces. A memory interface corresponding to a command, the first indication signal is used to instruct the first DRAM module RANK to enter the working state; wherein, the first physical connection is between the processing module and the first DRAM memory interface The physical connection; the first DRAM RANK is the DRAM RANK connected to the first DRAM memory interface;

The first DRAM memory interface is configured to control the first DRAM RANK to enter a working state when the first indication signal is received.
The device of claim 1, wherein the first DRAM memory interface is further used for:

Receiving the first command issued by the processing module via the bus, and in the case where it is determined that the first DRAM RANK enters a working state, issuing the first command to the first DRAM RANK.
The device according to claim 1 or 2, wherein the processing module is further configured to:

If the first command is a DRAM read/write command, the first DRAM memory interface corresponding to the first command is determined according to the address of the first command.
The device according to any one of claims 1-3, wherein the first indication signal is a high-level signal; the first DRAM memory interface is specifically configured to: upon receiving the high-level signal In the case of controlling the first DRAM RANK to enter the working state.
The device according to claim 4, wherein the first DRAM RANK is a first double rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR physical interface PHY ；

The first DRAM memory interface is specifically configured to: when the DDR controller receives the high-level signal, control the DDR PHY to exit the low power consumption state, and control the second DDR PHY through the DDR PHY A DDR RANK exits the power-off state or self-refresh state.
5. The device according to any one of claims 1-5, wherein the processing module is further configured to:

When it is not detected that the first command is sent through the bus or when the first DRAM RANK has executed and completed the first command, send to the first DRAM memory interface through the first physical connection A second indicator signal, where the second indicator signal is used to instruct the first DRAM RANK to enter a low power consumption state;

The first DRAM memory interface is further configured to control the first DRAM RANK to enter a low power consumption state when the second indication signal is received.
7. The device of claim 6, wherein the second indication signal is a low-level signal;

The first DRAM memory interface is specifically configured to control the first DRAM RANK to enter a low power consumption state when the low-level signal is received.
8. The device according to claim 7, wherein the first DRAM RANK is a first double-rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR Physical interface PHY;

The first DRAM memory interface is specifically configured to control the first DDR RANK to enter a power-off state or a self-refresh state through the DDR PHY when the DDR controller receives the low-level signal, And control the DDR PHY to enter a low power consumption state.
The device according to any one of claims 1-8, wherein the first DRAM memory interface is connected to M first DRAM RANKs, and M is an integer greater than or equal to 2; the processing module and the The first DRAM memory interfaces are directly connected through M first physical connections, where one first physical connection corresponds to one first DRAM RANK.
The device according to any one of claims 1-9, wherein the device and the first DRAM RANK are on different packaging substrates.
A processing method, characterized by comprising:

The processing module determines whether the first command is a dynamic random access memory DRAM read and write command;

If the first command is a DRAM read and write command, the processing module sends a first instruction signal to the first DRAM memory interface through the first physical connection; the processing module is connected to the N DRAM memory interfaces through a bus , And the processing module is also directly connected to the N DRAM memory interfaces through physical connections, where N is an integer greater than or equal to 1; the first DRAM memory interface is connected to all the N DRAM memory interfaces. The memory interface corresponding to the first command, the first indication signal is used to instruct the first DRAM module RANK to enter the working state; wherein, the first physical connection is the processing module and the first DRAM memory interface The physical connection between the first DRAM RANK is the DRAM RANK connected to the first DRAM memory interface;

When receiving the first indication signal, the first DRAM memory interface controls the first DRAM RANK to enter a working state.
The processing method according to claim 11, wherein the method further comprises:

Through the first DRAM memory interface, the first command issued by the processing module through the bus is received, and when it is determined that the first DRAM RANK enters the working state, the first command is issued Issued to the first DRAM RANK.
The processing method according to claim 11 or 12, wherein the method further comprises:

If the first command is a DRAM read/write command, the first DRAM memory interface corresponding to the first command is determined according to the address of the first command.
The processing method according to any one of claims 11-13, wherein the first indication signal is a high-level signal; when the first DRAM memory interface receives the first indication signal , Controlling the first DRAM RANK to enter the working state, including:

The first DRAM memory interface controls the first DRAM RANK to enter the working state according to the high-level signal.
The processing method according to claim 14, wherein the first DRAM RANK is a first double-rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and a DDR physical interface PHY;

The first DRAM memory interface controlling the first DRAM RANK to enter the working state according to the high-level signal includes:

Upon receiving the high-level signal, the DDR controller controls the DDR PHY to exit the DFI low power consumption state, and controls the first DDR RANK to exit the power-off state or self-refresh through the DDR PHY status.
15. The processing method according to any one of claims 11-15, wherein the method further comprises:

When it is not detected that the first command is sent via the bus or when the first DRAM RANK has executed and completed the first command, the processing module sends the first command to the first command through the first physical connection. A DRAM memory interface sends a second indication signal, where the second indication signal is used to instruct the first DRAM RANK to enter a low power consumption state;

The first DRAM memory interface, upon receiving the second indication signal, controls the first DRAM RANK to enter a low power consumption state.
The processing method according to claim 16, wherein the second indication signal is a low-level signal;

When the first DRAM memory interface receives the second indication signal, controlling the first DRAM RANK to enter a low power consumption state includes:

When the first DRAM memory interface receives the low-level signal, it controls the first DRAM RANK to enter a low power consumption state.
The processing method according to claim 17, wherein the first DRAM RANK is a first double rate synchronous dynamic random access memory DDR RANK; the first DRAM memory interface includes a DDR controller and DDR physical interface PHY;

When the first DRAM memory interface receives the low-level signal, controlling the first DRAM RANK to enter a low power consumption state includes:

When the DDR controller receives the low-level signal, the DDR PHY controls the first DDR RANK to enter a power-off state or a self-refresh state, and controls the DDR PHY to enter a low power consumption state .
The processing method according to any one of claims 11-18, wherein the first DRAM memory interface is connected to M first DRAM RANKs, and M is an integer greater than or equal to 2; the processing module is connected to The first DRAM memory interfaces are directly connected through M first physical connections, where one first physical connection corresponds to one first DRAM RANK.
The processing method according to any one of claims 11-19, wherein the processing module and the N DRAM memory interfaces are on the same packaging substrate, and are different from the first DRAM RANK. On the package substrate.
A semiconductor chip, characterized in that it comprises:

The processing device according to any one of claims 1 to 10, a central processing unit coupled to the processing device, and a memory external to the processing device.
A terminal device, characterized by comprising:

The processing device according to any one of claims 1 to 10, and a memory external to the processing device, wherein the processing device and the memory external to the processing device are provided in different semiconductor chips.