WO2023231437A1 - Memory, system-on-a-chip, terminal device and power supply control method - Google Patents

Abstract

A memory, a system-on-a-chip, a terminal device and a power supply control method, relating to the technical field of storage. The memory comprises m storage element groups, each storage element group comprising at least one storage element, and m being an integer greater than 1; the m storage element groups are in one-to-one correspondence with m groups of power cables, the m groups of power cables being separately controlled; for the ith storage element group of the m storage element groups, when the power cable corresponding to the ith storage element group is turned on, storage elements in the ith storage element group are in a power-on state, and when the power cable corresponding to the ith storage element group is disconnected, the storage elements in the ith storage element group are in a power-off state, i being a positive integer smaller than or equal to m. The present application provides the memory supporting flexible control of power-on or power-off of the storage elements, which can realize more flexible and fine-granularity power-on and power-off control, helping to reduce power consumption.

Description

Memory, system on chip, terminal equipment and power supply control method

This application claims priority to the Chinese patent application with application number 202210613550.5 and the invention title "Memory, System-on-Chip, Terminal Equipment and Power Supply Control Method" submitted on May 31, 2022, the entire content of which is incorporated into this application by reference. middle.

Technical field

Embodiments of the present application relate to the field of storage technology, and in particular to a memory, a system on a chip, a terminal device, and a power supply control method.

Background technique

Memory is an essential electronic component in terminal equipment.

In related art, a memory includes multiple storage elements. When the memory needs to work, all the storage elements included in the memory can be set to the powered-on state; when the memory does not need to work, all the storage elements included in the memory can be set to the powered-off state to save power consumption.

However, the above method can no longer meet the power saving needs in some scenarios.

Contents of the invention

Embodiments of the present application provide a memory, system-on-chip, terminal and power supply control method. The technical solutions are as follows:

According to an aspect of an embodiment of the present application, a memory is provided, the memory includes: m storage element groups, each of the storage element groups includes at least one storage element, and m is an integer greater than 1;

The m storage element groups and the m groups of power lines are in one-to-one correspondence, and the m groups of power lines are controlled respectively;

For the i-th storage element group among the m storage element groups, when the power line corresponding to the i-th storage element group is turned on, the storage elements in the i-th storage element group are at the upper level. Electrical state; when the power line corresponding to the i-th storage element group is disconnected, the storage elements in the i-th storage element group are in a power-off state, and i is a positive integer less than or equal to m.

According to an aspect of an embodiment of the present application, a system-on-chip is provided. The system-on-chip includes: a memory and a power management chip;

The memory is connected to the power management chip;

The memory is a memory as described above;

The m sets of power lines are used to transmit the output voltage of the power management chip.

According to one aspect of the embodiment of the present application, a terminal device is provided, and the terminal device is provided with the memory as described above.

According to an aspect of an embodiment of the present application, a power supply control method is provided. The method is executed by a control circuit, and the control circuit is used to control the memory as described above. The method includes:

A control signal is sent to the switching element, and the control signal is used to control the switching element to be turned on or off, so as to independently control the power on or off of each of the storage element groups through the switching element.

The technical solutions provided by the embodiments of this application can bring the following technical effects:

Embodiments of the present application provide a memory that supports flexible control of powering on or off storage elements by dividing the memory into multiple storage element groups. Each storage element group contains at least one storage element, and each storage element group Corresponding to different power lines, the power lines corresponding to each storage element group are controlled separately, so that power on and off control can be realized with the storage element group as the granularity, and a part of the storage elements in the memory can be flexibly selected to be in the powered on state. Another part of the storage elements is in a power-off state; compared to the memory provided by the related art, all the storage elements are either in a power-on state. state, or both are in the power-off state. The technical solution provided by this application can achieve more flexible and fine-grained power-on and power-off control, which is more conducive to saving power consumption.

Description of the drawings

Figure 1 is a schematic structural diagram of a system-on-chip including a memory provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a memory provided by an embodiment of the present application;

Figure 3 is a schematic diagram of a memory including two storage element groups provided by an embodiment of the present application;

Figure 4 is a schematic diagram of a memory including four storage element groups provided by an embodiment of the present application;

Figure 5 is a schematic diagram of a memory including 8 storage element groups provided by an embodiment of the present application;

Figure 6 is a schematic diagram of a memory including three storage element groups provided by an embodiment of the present application;

Figure 7 is a schematic diagram of a power cord composition provided by an embodiment of the present application;

Figure 8 is a schematic diagram of functional components corresponding to different power lines provided by an embodiment of the present application;

Figure 9 is a schematic diagram of multiple sets of power lines connected to the same switching element according to an embodiment of the present application;

Figure 10 is a schematic diagram of each group of power lines connected to a switching element according to an embodiment of the present application;

Figure 11 is a schematic diagram of the setting position of the switch element provided by an embodiment of the present application;

Figure 12 is a schematic diagram of a memory provided by an embodiment of the present application divided into two storage element groups;

Figure 13 is a schematic diagram of a memory provided by an embodiment of the present application divided into three storage element groups;

Figure 14 is a flow chart of a power supply control method provided by an exemplary embodiment of the present application;

Figure 15 is a schematic diagram of a terminal device provided by an exemplary embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Figure 1 is a schematic structural diagram of a system on chip (SoC) including a memory provided by an exemplary embodiment of the present application. The system-on-chip in this application can be used in mobile terminals, such as smartphones, smart watches, e-book readers, tablet computers, laptop computers, desktop computers, televisions, game consoles, and augmented reality (Augmented Reality, AR) terminals. Taking at least one of a virtual reality (Virtual Reality, VR) terminal, a mixed reality (MR) terminal, a wearable device, etc. as an example for explanation. The system-on-chip 100 in this embodiment includes: a main device 101, a main bus 103, a memory controller 105 and a memory 200.

The main device 101 is connected to the storage controller 105 through the main bus 103 (Primary Bus), and the storage controller 105 is connected to the memory 200 through a physical layer (Physical Layer, PHY) interface. In some embodiments, the memory 200 is a dynamic random access memory (Dynamic Random Access Memory, DRAM). Optionally, the DRAM adopts Packaging on Packaging (PoP) packaging.

The master device 101 is a processor or non-processor with data reading and writing requirements. The main device may include, but is not limited to, a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU), a neural network processor (Neural-network Processing Unit, NPU), a digital signal processor (Digital Signal Processors such as Processor (DSP), and non-processors such as Image Sensor (Image Sensor), Image Signal Processing Unit (ISP), and Video Processing Unit (VPU). The above-mentioned main devices all have memory data reading and/or writing requirements during operation. In Figure 1, the processor includes CPU, GPU and NPU, and the non-processor includes image sensor and VPU as an example for schematic illustration, but this is not a limitation.

Among them, the processor uses various interfaces and lines to connect various parts of the entire terminal device, and executes the terminal device by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory. various functions and process data.

In some embodiments, the processor may adopt at least one of digital signal processing (DSP), field-programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). A form of hardware implementation.

The processor can integrate one or a combination of CPU, GPU, NPU and baseband chip. Among them, the CPU mainly handles the operating system, user interface and applications; the GPU is responsible for the rendering and drawing of the content that needs to be displayed on the display; the NPU is used to implement AI (Artificial Intelligence, artificial intelligence) functions; the baseband chip is used for processing Wireless communication.

In some embodiments, m links using the AXI (Advanced eXtensible Interface, Advanced Extension Interface) protocol are established between the main device 101 and the main bus 103, and between the main bus 103 and the storage controller 105. As shown in FIG. 1 , four AXI links with a width of 256 bits are established between each master device 101 and the main bus 103, and between the main bus 103 and the memory controller 105.

In some embodiments, the storage controller 105 includes a secondary bus, k controllers (corresponding to k memory channels), and physical layer interfaces corresponding to each controller, where k is a positive integer.

In some embodiments, a link using the AXI protocol is established between the slave bus and the controller, and the branching function is implemented at the slave bus. For example, after the slave bus is branched (k branches are n branches, n is a positive integer), 8 AXI links with a bit width of 128 bits are established between the slave bus and the controller. Correspondingly, eight AXI links with a bit width of 128 bits are established between the memory controller 105 and the memory 200 .

The memory 200 is a memory that supports n (n>k) memory channels, and the n storage elements in the memory 200 each have a working bus, that is, the working bus of each storage element is connected to the storage controller 105 in a concurrent manner.

Figure 1 takes a system on a chip that integrates a memory (that is, the memory is arranged inside the system on a chip) as an example. In other possible designs, the memory can be arranged outside the system on a chip. This is not limited in the embodiments of the present application.

Figure 2 is a schematic structural diagram of a memory provided by an exemplary embodiment of the present application.

The memory 200 includes n storage elements 201, where n is an integer greater than 1. In some embodiments, the memory 200 is a DRAM, and the storage element 201 is a memory die. Optionally, the DRAM is packaged in TOP. The embodiment of the present application does not limit the specific types of the memory 200 and the storage element 201.

In some embodiments, the internal particles of the storage element 201 may be arranged in a 2D (Two Dimensional, two-dimensional) manner or a 3D (Three Dimensional, three-dimensional) manner. Among them, the 3D arrangement can adopt simple stack (Simple Stack), vertical channel (Vertical Channel, VC) or vertical gate (Vertical Grid, VG) and other methods.

In some embodiments, the element parameters (such as capacity) of each storage element 201 are the same. For example, each storage element 201 has a specification of 16Gb×16 data width (Datawidth). In other embodiments, some storage elements have the same component parameters, some storage components have different component parameters, or different storage components have different component parameters. The embodiments of this application do not limit the specific component parameters of each storage component.

n storage elements 201 are packaged into a storage particle, such as a DRAM device using POP packaging. In some possible designs, the n storage elements 201 adopt 2D packaging or 3D packaging. The embodiments of this application do not limit the specific packaging method.

The memory 200 in the embodiment of the present application supports n memory channels, so the number of storage elements 201 in the memory 200 is equal to n, and different storage elements 201 correspond to respective memory channels, that is, n storage elements correspond to n memory channels. . For example, for a memory that supports 8 memory channels, 8 storage elements are provided in the memory; for a memory that supports 6 memory channels, 6 storage elements are provided with the memory. The embodiments of the present application do not limit the specific number of storage elements (a positive integer is sufficient, and it can be an even number or an odd number).

In some embodiments, the memory 200 includes: m storage element groups, each storage element group includes at least one storage element 201, and m is an integer greater than 1. That is to say, the n storage elements 201 included in the memory 200 are divided into m storage element groups. One storage element group may have one and only one storage element 201, or may include multiple (two or more) storage elements 201. Storage element 201.

In some embodiments, for the above m storage element groups, the number of storage elements 201 included in each storage element group is the same.

Illustratively, as shown in FIG. 3, the memory 200 includes 8 storage elements 201, and the 8 storage elements 201 are divided into It is divided into two storage element groups, denoted as a first storage element group and a second storage element group, and each storage element group includes four storage elements 201 . In FIG. 3 , the first storage element group includes storage elements 201 corresponding to memory channels A, B, C and D respectively, and the second storage element group includes storage elements 201 corresponding to memory channels E, F, G and H respectively.

For example, as shown in Figure 4, the memory 200 includes 8 storage elements 201, which are divided into 4 storage element groups, denoted as a first storage element group, a second storage element group, and a third storage element group. The storage element group and the fourth storage element group, each storage element group includes 2 storage elements 201 . In Figure 4, the first storage element group includes storage elements 201 corresponding to memory channels A and B respectively, the second storage element group includes storage elements 201 corresponding to memory channels C and D respectively, and the third storage element group includes memory channel E. and F respectively correspond to storage elements 201. The fourth storage element group includes storage elements 201 corresponding to memory channels G and H respectively.

Exemplarily, as shown in Figure 5, each storage element group includes one storage element 201, and the memory 200 includes 8 storage elements 201, and the 8 storage elements 201 are divided into 8 storage element groups. In Figure 5, Each dotted box represents a storage element group, and each storage element group includes one storage element 201.

In some embodiments, for the above-mentioned m storage element groups, there are at least two storage element groups that contain different numbers of storage elements 201 .

For example, as shown in Figure 6, the memory 200 includes 8 storage elements 201, which are divided into 3 storage element groups, denoted as a first storage element group, a second storage element group and a third storage element group. Storage element group; wherein, the first storage element group includes 2 storage elements 201, such as the storage elements 201 corresponding to memory channels A and B shown in Figure 6; the second storage element group includes 2 storage elements 201, as shown in Figure 6 Memory channels C and D shown in Figure 6 correspond to storage elements 201 respectively; the third storage element group includes four storage elements 201, such as memory channels E, F, G and H shown in Figure 6 correspond to storage elements 201 respectively.

Of course, the above-mentioned FIGS. 3 to 6 are only examples of how to divide several storage element groups. This application specifies the number of storage element groups included in the memory 200 and the storage elements 201 included in each storage element group. There is no limit to the quantity, which can be designed and divided according to actual needs.

In some embodiments, the m storage element groups and the m groups of power lines correspond one to one, and the m groups of power lines are controlled respectively. That is to say, each storage element group has a corresponding set of power lines. Since the m groups of power lines are controlled separately, the m storage element groups can be independently controlled to power on or off.

In some embodiments, for the i-th storage element group among the m storage element groups, when the power line corresponding to the i-th storage element group is turned on, the storage elements in the i-th storage element group are at the upper level. Electrical state; when the power line corresponding to the i-th storage element group is disconnected, the storage elements in the i-th storage element group are in a power-off state, and i is a positive integer less than or equal to m.

Exemplarily, as shown in FIG. 3 , the first storage element group corresponds to the first power supply line, and the second storage element group corresponds to the second power supply line. The first power line and the second power line are controlled separately. For example, when the first power line is turned on, the four storage elements 201 included in the first storage element group (that is, the storage elements 201 corresponding to memory channels A, B, C, and D respectively) are in a powered-on state; When the first power line is disconnected, the four storage elements 201 included in the first storage element group (that is, the storage elements 201 corresponding to memory channels A, B, C, and D respectively) are in a power-off state. For another example, when the second power line is turned on, the four storage elements 201 included in the second storage element group (i.e., the storage elements 201 corresponding to the memory channels E, F, G, and H respectively) are in the powered-on state; When the second power line is disconnected, the four storage elements 201 included in the second storage element group (that is, the storage elements 201 corresponding to the memory channels E, F, G, and H respectively) are in a power-off state.

Exemplarily, as shown in Figure 4, the first storage element group corresponds to the first power line, the second storage element group corresponds to the second power line, the third storage element group corresponds to the third power line, and the fourth storage element Group corresponds to the fourth power cord. The first power line, the second power line, the third power line and the fourth power line are controlled respectively. For example, when the first power line is turned on, the two storage elements 201 included in the first storage element group (that is, the storage elements 201 corresponding to memory channels A and B respectively) are in a powered-on state; when the first power line When disconnected, the two storage elements 201 included in the first storage element group (that is, the storage elements 201 corresponding to memory channels A and B respectively) are in a power-off state. For another example, when the second power line is turned on, the two storage elements 201 included in the second storage element group (that is, the storage elements corresponding to memory channels C and D respectively) 201) is in the powered-on state; when the second power line is disconnected, the two storage elements 201 included in the second storage element group (ie, the storage elements 201 corresponding to memory channels C and D respectively) are in the powered-off state. The third storage element group and the fourth storage element group can be deduced in the same way.

For example, as shown in Figure 5, 8 storage element groups and 8 groups of power lines correspond one to one, and the 8 groups of power lines are controlled respectively. For example, when the first power line is turned on, one storage element 201 included in the first storage element group (that is, the storage element 201 corresponding to memory channel A) is in a powered-on state; when the first power line is turned off, In this case, one storage element 201 included in the first storage element group (that is, the storage element 201 corresponding to memory channel A) is in a power-off state. For another example, when the second power line is turned on, one storage element 201 included in the second storage element group (that is, the storage element 201 corresponding to memory channel B) is in a powered state; when the second power line is turned off, In the case of , one storage element 201 included in the second storage element group (that is, the storage element 201 corresponding to memory channel B) is in a power-off state. Other storage element groups can be deduced in this way.

For example, as shown in FIG. 6 , the first storage element group corresponds to the first power line, the second storage element group corresponds to the second power line, and the third storage element group corresponds to the third power line. The first power line, the second power line and the third power line are controlled separately. For example, when the first power line is turned on, the two storage elements 201 included in the first storage element group (that is, the storage elements 201 corresponding to memory channels A and B respectively) are in a powered-on state; when the first power line When disconnected, the two storage elements 201 included in the first storage element group (that is, the storage elements 201 corresponding to memory channels A and B respectively) are in a power-off state. For another example, when the second power line is turned on, the two storage elements 201 included in the second storage element group (that is, the storage elements 201 corresponding to memory channels C and D respectively) are in a powered-on state; when the second power supply When the line is disconnected, the two storage elements 201 included in the second storage element group (that is, the storage elements 201 corresponding to memory channels C and D respectively) are in a power-off state. For another example, when the third power line is turned on, the four storage elements 201 included in the third storage element group (i.e., the storage elements 201 corresponding to memory channels E, F, G, and H respectively) are in the powered-on state; When the third power line is disconnected, the four storage elements 201 included in the third storage element group (that is, the storage elements 201 corresponding to the memory channels E, F, G, and H respectively) are in a power-off state.

In some embodiments, each set of power lines includes one power line, and the one power line is used to power each functional component in the storage element 201 .

In some embodiments, each group of power lines includes a plurality of different power lines, and the plurality of different power lines are used to power different functional components in the storage element 201 . For example, each group of power cords includes three different power cords, denoted as power cord 1, power cord 2 and power cord 3. It is assumed that the storage element 201 includes functional part 1, functional part 2, functional part 3, functional part 4 and function Component 5, for example, the power line 1 is used to supply power to the functional components 1 and 2 in the storage element 201, the power line 2 is used to supply power to the functional component 3 in the storage element 201, and the power line 3 is used to supply power to the storage element 201. Functional components 4 and 5 in element 201 are powered.

In some embodiments, as shown in Figures 7 and 8, each group of power lines includes a total of four different power lines: VDD1 power line, VDD2H power line, VDD2L power line, and VDDQ power line. These four different power lines are used to supply power to different functional components in the storage element 201 to provide different voltages. Each power wire is used to provide its corresponding functional component with a voltage suitable for the operation of the functional component. For example, the VDDQ power line is used to provide the VDDQ voltage, which may be called the input-output interface voltage, and is used to provide the input-output interface component in the storage element 201 . The VDD1 power line is used to provide VDD1 voltage, the VDD2 power line is used to provide VDD2 voltage, and the VDD2 power line can be divided into a VDD2H power line and a VDD2L power line. The VDD2H power line is used to provide VDD2H voltage, and the VDD2L power line is used to provide VDD2L. Voltage. Both the VDD1 voltage and the VDD2 voltage can be called core voltages and are used to provide core components in the storage element 201 . The VDD2H voltage can be called the high-frequency core voltage, and the VDD2L voltage can be called the low-frequency core voltage. There are differences in the operating frequencies of the core components corresponding to the two. In addition, the VDD1 voltage is higher than the VDD2 voltage and is used to provide power supply voltage to some core components that require high-voltage operation. In the example of FIG. 8 , the functional components indicated by diagonal filling in the storage element 201 are supplied with power supply voltage by VDDQ. The functional components indicated by dotted filling in the storage element 201 are supplied with power supply voltage by VDD2H or VDD2L. The crossed lines in the storage element 201 The features shown in the fill are powered by VDD1.

Embodiments of the present application provide a memory that supports flexible control of powering on or off storage elements by dividing the memory into multiple storage element groups. Each storage element group contains at least one storage element, and each storage element group Corresponding to different power lines, the power lines corresponding to each storage element group are controlled separately, so that power on and off control can be realized with the storage element group as the granularity, and a part of the storage elements in the memory can be flexibly selected to be in the powered on state. Another part of the storage elements is in a power-off state; compared with the related technology that all storage elements in the memory are either in the same power-on state or in the same power-off state, the technical solution provided by this application can achieve more flexible and fine-grained Power on and off control is more conducive to saving power consumption.

In addition, the number of storage element groups included in the memory and the number of storage elements included in each storage element group can be flexibly divided. In some embodiments, dividing multiple storage elements into the same storage element group can prevent the number of divided storage element groups in the memory from being too large, which helps to reduce complexity. In some embodiments, when there is only one storage element in each storage element group, power on and off control can be achieved at the granularity of a single storage element. This method is more flexible and more conducive to energy saving, but The corresponding complexity will also be higher.

In some embodiments, as shown in Figure 9, the power line is connected to one end of the switching element 300, the other end of the switching element 300 is used to receive the input voltage, and the switching element 300 is used to control the power line to be turned on or off.

In some embodiments, in the above-mentioned m groups of power lines, each group of power lines is connected to a switching element, and different power lines are connected to different switching elements; wherein, the i-th group of power lines in the m groups of power lines is connected to a switch. Component, used to control the conduction or disconnection of the i-th group of power lines. For example, as shown in FIG. 10 , the memory 200 includes 8 storage elements 201 , and the 8 storage elements 201 are divided into 2 storage element groups. The first storage element group corresponds to the first power line, and the first storage element group corresponds to the first power line. The two storage element groups correspond to second power lines, the first power line is connected to the first switching element 301 , and the second power line is connected to the second switching element 302 . The first switching element 301 and the second switching element 302 are two different switching elements. The first switch element 301 is used to control the first power line to be turned on or off, so that the storage element 201 in the first storage element group is powered on or off. The second switch element 302 is used to control the second power line to be turned on or off, so that the storage element 201 in the second storage element group is powered on or off. In this way, storage element groups, power lines and switching elements correspond one to one, achieving independent and flexible control of the power on and off states of each storage element group.

In some embodiments, among the above-mentioned m sets of power lines, there are at least two sets of power lines connected to the same switching element; wherein, the switching element is used to control each of the at least two sets of power lines to be turned on or off independently. open. For example, as shown in FIG. 9 , the memory 200 includes 8 storage elements 201 , and the 8 storage elements 201 are divided into 2 storage element groups. The first storage element group corresponds to the first power line, and the first storage element group corresponds to the first power line. The two storage element groups correspond to the second power lines, and the first power line and the second power line are connected to the same switching element 300 . The switching element 300 can control the first power line and the second power line to be turned on or off independently. For example, the switching element 300 can control both the first power line and the second power line to be turned on, so that the storage elements 201 in the first storage element group and the second storage element group are both in a powered state; the switching element 300 can The first power line and the second power line are both controlled to be disconnected, so that the storage elements 201 in the first storage element group and the second storage element group are both in a power-off state; the switching element 300 can control the first power line to be turned on. And the second power line is disconnected, so that the storage element 201 in the first storage element group is in the powered-on state, and the storage element 201 in the second storage element group is in the powered-off state; the switch element 300 can control the first power line The power supply line is disconnected and the second power line is connected, so that the storage elements 201 in the first storage element group are in a power-off state, and the storage elements 201 in the second storage element group are in a power-on state. In this way, multiple sets of power lines can be connected to the same switching element, and each group of power lines can be controlled to be independently turned on or off through the switching element. This can also achieve independent and flexible control of the power on and off states of each storage element group. , and can save the number of switching components.

In the above-mentioned memory 200 shown in FIG. 9 and FIG. 10 , the memory 200 includes eight storage elements 201 and the eight storage elements 201 are divided into two storage element groups as an example for introduction and explanation. For memories 200 in other partitioning modes, the method introduced above can also be adopted, and switching elements are used to control the conduction or disconnection of the power line.

Next, the setting positions of the switching elements are introduced and explained. As shown in FIG. 11 , several possible arrangement positions of the switching element are exemplarily shown.

In some embodiments, the switching element is disposed inside the memory 200, as shown at position numbered (1) in FIG. 11 .

In some embodiments, the switching element is disposed inside the power management chip (Power Management IC, PMIC) 400, as shown at the position numbered (2) in Figure 11. The power management chip 400 is used to provide input voltage to the memory 200 .

In some embodiments, the switching element is disposed between the memory 200 and the power management chip 400, as shown at the position numbered (3) in FIG. 11 . Optionally, in this case, if the memory 200 and the power management chip 400 are arranged on the same circuit board, the switching element can also be arranged on the circuit board; if the memory 200 and the power management chip 400 are arranged on two On different circuit boards, the switching element can be provided on the circuit board used to carry the memory 200, or can be provided on the circuit board used to carry the power management chip 400, or can also be provided in addition to the above two circuit boards. on another circuit board, this application does not limit this.

The embodiments of the present application provide a variety of setting methods for switching elements. In practical applications, an appropriate method can be selected to set the switching elements based on actual needs.

In addition, as mentioned above, the power line is connected to one end of the switching element, and the other end of the switching element is used to receive the input voltage. The input voltage can be provided by the power management chip 400 . In the embodiment of the present application, the wire between one end of the switching element and the memory 200 (or storage element 201) is called a power line, and the wire between the other end of the switching element and the power management chip 400 is called a voltage transmission line. .

For example, when the switching element is inside the power management chip 400, the power line may include a wire between the power management chip 400 and the memory 200, and the voltage transmission line may include a wiring inside the power management chip 400; when the switching element is inside In the case inside the memory 200 , the power lines may include wiring inside the memory 200 , and the voltage transmission lines may include wires between the power management chip 400 and the memory 200 ; in the case where the switching element is between the memory 200 and the power management chip 400 , the power line may include a wire between the memory 200 and the switching element, and the voltage transmission line may include a wire between the switching element and the power management chip 400 .

In some embodiments, as shown in Figure 9 or Figure 10, the control end of the switching element is connected to the control circuit 500. The control circuit 500 is used to control the switching element to be turned on or off to independently control each storage element through the switching element. Power on or off the group. The control circuit 500 may be any form of processor, controller, microprocessor, or integrated circuit chip with data processing capabilities. This application does not limit the implementation form of the control circuit 500.

In some embodiments, the control circuit 500 can be disposed inside the memory 200 , the control circuit 500 can also be disposed inside the power management chip 400 , and the control circuit 500 can also be disposed in a circuit used to carry the memory 200 and/or the power management chip 400 on the board. This application also does not limit the installation location of the control circuit 500.

In some embodiments, the control circuit 500 is used to send a control signal to the switching element according to the working mode, and the control signal is used to control the switching element to be turned on or off. Regarding the working process of the control circuit 500, please refer to the introduction in the method embodiment below for details.

In some embodiments, the n storage elements in the memory are divided into at least two storage element groups (or storage regions), and different storage element groups do not affect each other.

Optionally, different storage element groups are used for different objects, and the objects may include at least one of an operating system, a kernel space (Kernel Space), a reserved space (Reserved Space), and an application program.

In an illustrative example, as shown in Figure 12, multiple storage elements in the memory are divided into a first storage element group 51 and a second storage element group 52, where the first storage element group 51 is used to provide high Used by performance applications, which refer to applications with high memory requirements, such as game applications, AI applications, etc.; the second storage element group 52 is used for default kernel (Kernel) space, reserved space and commonly used applications (Normal Usage Application), which can be default settings or customized or determined based on frequency of use, such as desktop applications, clock applications, etc. That is to say, when no high-performance application program is running, the second storage element group 52 in the memory is in the powered-on state, and the first storage element group 51 is in the powered-off state, thereby saving power consumption; when there is a high-performance application program running At this time, both the second storage element group 52 and the first storage element group 51 in the memory are in the powered-on state. exist In some embodiments, when the second storage element group 52 and the first storage element group 51 are both powered on, the high-performance application can either use the first storage element group 52 for data storage or the second storage element group 51 . The storage element group 52 performs data storage; similarly, the default kernel space, reserved space, and commonly used applications can also use the first storage element group 52 and the second storage element group 52 for data storage. After the high-performance application switches from the running state to the stopped running state, if the first storage element group 52 stores the default kernel space, reserved space and data related to common applications, then the first storage element group 52 can be first The stored data related to the default kernel space, reserved space, and commonly used applications are migrated to the second storage element group 52, and then the first storage element group 52 is controlled to be powered off.

In an illustrative example, as shown in Figure 13, multiple storage elements in the memory are divided into a first storage element group 51, a second storage element group 52 and a third storage element group 53, where the first storage element group The component group 51 and the third storage component group 53 are used for high-performance applications, which refer to applications with high memory requirements, such as game applications, AI applications, etc.; the second storage component group 52 is used for the default kernel space, reserved space and commonly used applications. The commonly used applications can be default settings or customized or determined based on frequency of use, such as desktop applications, clock applications, etc. That is to say, when no high-performance application is running, the second storage element group 52 in the memory is in the powered-on state, and the first storage element group 51 and the third storage element group 53 are in the powered-off state, thereby saving power consumption; When a high-performance application is running, in addition to the second storage element group 52 being in the powered-on state, the first storage element group 51 and/or the third storage element group 53 are also in the powered-on state. Compared with the example shown in Figure 12, the example shown in Figure 13 is that the high-performance application corresponds to multiple (such as 2) storage element groups, so that one of them can be flexibly selected as needed when the high-performance application is running. Or multiple storage element groups can be opened to achieve more flexible control.

In some embodiments, at least one of the m storage element groups included in the memory 200 is configured to be enabled during system startup. The above system may refer to the software and hardware system of the terminal device where the memory 200 is located, including the operating system, processor, etc. of the terminal device. That is to say, among the m storage element groups included in the memory 200, some of the storage element groups are configured to be enabled during the system startup process, while another part of the storage element groups are configured to not be enabled temporarily during the system startup process, and in the Enable it when needed. For example, the memory 200 includes a first storage element group 51 and a second storage element group 52 as shown in FIG. 12 , the second storage element group 52 is configured to be enabled during system startup, and the first storage element group 51 is configured to Disable it during system startup and enable it when high-performance applications are running.

Through the above method, it can be ensured that during the system startup process, some storage element groups are first enabled to meet some basic data reading and writing requirements, instead of directly enabling all storage element groups to achieve the purpose of saving power consumption.

Figure 14 is a flow chart of a power supply control method provided by an exemplary embodiment of the present application. The method may be performed by the control circuit introduced above, which is used to control the memory introduced above. The method may include the following steps:

Step 1410: The control circuit sends a control signal to the switching element. The control signal is used to control the switching element to be turned on or off, so as to independently control the power on or off of each storage element group through the switching element.

In some embodiments, if the memory includes m storage element groups, the m storage element groups correspond to m groups of power lines one-to-one, each group of power lines is connected to a switching element, and different power lines are connected to different switching elements. , in this case, when the control circuit needs to control the power on or off of the i-th storage element group, the switch element corresponding to the i-th storage element group (that is, the switch element corresponding to the i-th storage element group The switching element connected to the power line) sends a control signal. The control signal is used to control the switching element corresponding to the i-th storage element group to be on or off, so as to control each storage in the i-th storage element group through the switching element. Components are powered on or off uniformly.

In some embodiments, if the memory includes m storage element groups, the m storage element groups correspond to m groups of power lines one-to-one, and there are at least two sets of power lines connected to the same switching element. In this case, when the control When the circuit needs to control the power on or off of the i-th storage element group, it can send a signal to the switching element corresponding to the i-th storage element group (that is, the switching element connected to the power line corresponding to the i-th storage element group). A control signal, which is used to control the switching element to turn on or off the power line corresponding to the i-th storage element group, so as to control the unified power-on or power-off of each storage element in the i-th storage element group.

In the embodiment of the present application, the form of the control signal is not limited. The control signal may be a digital signal or an analog signal.

In some embodiments, the control circuit sends a control signal to the switching element according to the operating mode. For different working modes, different storage element groups can be controlled to power on or off.

In the embodiment of the present application, the basis for dividing the working modes is not limited.

In some embodiments, the memory can be divided according to objects using the memory, which can include at least one of an operating system, a kernel space (Kernel Space), a reserved space (Reserved Space), and an application program. For example, in the first working mode, no high-performance applications are running, and only the default kernel space, reserved space, and commonly used applications use memory; in the second working mode, there are high-performance applications running, except for the default kernel space, reserved space, and common applications. In addition to space and common applications using memory, there are also high-performance applications that also require memory. As shown in FIG. 12 , in the first working mode, only the second storage element group 52 can be controlled to work in the powered-on state; in the second working mode, the second storage element group 52 and the first storage element group can be controlled 51 are all powered on and working.

In some embodiments, the working modes can be divided according to the operating status of the terminal device or processor. For example, in different working modes, the terminal device or processor is in different running states, such as different applications running in different running states, or the number of tasks executed by the processor in different running states is different.

In some embodiments, the working modes can be divided according to the running requirements of the application program. For example, applications have different operating requirements in different working modes. Take game applications as an example. In different working modes, game applications have different refresh frame rates, which results in different memory usage requirements.

Of course, the above is only an illustrative introduction to the division of several working modes, and this application is not limited to the division of working modes according to other dimensions.

For example, as shown in Figure 9 or Figure 12, the memory can support two working modes, denoted as a first working mode and a second working mode. In the first operating mode, the control circuit 500 sends a first control signal to the switching element 300. The first control signal is used to control the first power line to be turned on and the second power line to be turned off, so that the first storage element group The four storage elements 401 included in the second storage element group are in a power-on state, and the four storage elements 401 included in the second storage element group are in a power-down state. In the second operating mode, the control circuit 500 sends a second control signal to the switching element 300. The second control signal is used to control the first power line to be turned on, and the second power line is also turned on, so that the first storage element group The four storage elements 401 included in are in the powered-on state, and the four storage elements 401 included in the second storage element group are also in the powered-on state. In addition, the maximum number of working modes that a memory can support is related to the number of storage element groups contained in the memory. In different working modes, the power-on and power-off states of each storage element group included in the memory are not exactly the same. Through the above method, the storage element group that needs to be powered on and the storage element group that does not need to be powered on can be flexibly selected according to the working mode, so as to save terminal power consumption as much as possible while meeting the operation requirements of the application program.

In some embodiments, the control circuit obtains power supply configuration information corresponding to the working mode, and the power supply configuration information is used to indicate the power supply status of each storage element group in the memory. The control circuit generates a control signal adapted to the power supply status of each storage element group based on the power supply configuration information. The control circuit sends the generated control signal to the switching element. The mapping relationship between different working modes and power supply configuration information can be stored in the terminal device in advance, and the control circuit can determine the power supply configuration information corresponding to the working mode from the above mapping relationship according to the working mode. The power supply configuration information defines the power supply status of each storage element group in the memory, that is, whether each storage element group in the memory is in the power-on state or the power-off state. The control circuit generates corresponding control signals based on the power supply configuration information. Each storage element group in the memory is controlled to work according to the above state. Through the above method, the control circuit can accurately and efficiently obtain the power supply status of each storage element group and perform corresponding control, thereby improving the efficiency and robustness of the control.

In some embodiments, each storage element group in the memory is used to store data generated in the same operating mode. In this way, for any storage element group, when the storage element group is not in the working mode corresponding to the storage element group, the control circuit 500 can control the storage element group to power off through the switching element.

For example, as shown in Figure 9 or Figure 12, the memory can support two working modes, denoted as a first working mode and a second working mode. In the first operating mode, the first storage element group is in a power-on state, and the second storage element group is in a power-down state. power state; in the second working mode, both the first storage element group and the second storage element group are in the power-on state. The first storage element group is used to store data generated in the first working mode, and is also used to store data generated in the second working mode. For example, in the first working mode, the first storage element group is used to store data generated in the first working mode; in the second working mode, the first storage element group is used to store data generated in the second working mode. The second storage element group is used to store data generated in the second operating mode. That is to say, in the second operating mode, the first storage element group and the second storage element group jointly store data generated in the second operating mode. Through the above method, the power on and off status of each storage element group can be controlled according to different working modes, and the storage element group corresponding to the current working mode can be used to store the data generated in the current working mode, realizing the data generation in different working modes. Storage isolation helps improve the security and reliability of data storage.

Next, taking the encoding and decoding scenario of audio data as an example, the working status of the memory is introduced and explained. In this example, still taking the example shown in Figure 9 or Figure 12, the memory includes a first storage element group and a second storage element group, supports two working modes, and in the first working mode and the second working mode, The power-on and power-off status of the storage element group is as described above.

In the audio data encoding and decoding scenario, the terminal device operates in the above-mentioned first working mode. The second storage element group is in a power-off state in the first working mode, the first storage element group is in a power-on state in the first working mode, and the first storage element group maintains normal operation.

The CPU sends the compressed audio file (usually 60 seconds) to memory (such as DDR (Double Data Rate, Double Data Rate) memory, DRAM, etc.) for decoding, and then the CPU enters a deep sleep state. The memory uses the first storage element group to store the compressed data.

Audio DMA (Direct Memory Access) extracts compressed data from memory to audio SRAM (Static Random-Access Memory) (usually 1 second), and then the memory enters a deep sleep state (also known as self-refresh status). Whenever the buffer in SRAM is almost empty, HIFI (High-Fidelity, High Fidelity) 5DSP will send a memory wake-up request to SRAM.

HIFI5DSP takes out the compressed data from SRAM for decoding, and the frame length is 20 milliseconds. For different scenes, different mixing effects will be achieved. The decoded audio data will be written back to SRAM with a frame length of 20 milliseconds. In some embodiments, ping-pong buffering may be used, for a total of 40 milliseconds.

Audio DMA moves data from SRAM to the CODEC (coder-decoder, codec) chip through the Soundwire bus. Soundwire can be clock-gated when a block of data transfer is complete.

Embodiments of the present application provide a memory that supports flexible control of powering on or off storage elements, which is more conducive to saving power consumption. For example, the power consumption calculation formula of the memory is as follows:

N*(IDDread*Utilizationread+IDDwrite*Utilizationwrite+IDDstby*Utilizationstby+IDDsr*Utilizationsr+IDDref+IDDactive)*(VDD);

Among them, N is the number of storage elements in the power-on state in the memory, IDDread is the memory current when data is read, Utilizationread is the memory usage when data is read, IDDwrite is the memory current when data is written, and Utilizationwrite is the data Memory usage during writing, IDDstby is the standby memory current, Utilizationstby is the standby memory usage, IDDsr is the self-refresh (selfrefresh) current, Utilizationsr is the self-refresh usage, IDDref is the refresh (refresh) current, and IDDactive is Active current, VDD is the voltage value of the input voltage, and VDD includes at least one of VDD1, VDD2H, VDD2L, and VDDQ.

It can be seen from the above formula that the power consumption of the memory is positively correlated with the number N of storage elements in the powered-on state in the memory. Therefore, by controlling the power-off of unused storage elements, it helps to reduce the power consumption of the memory, thereby saving money. Terminal power.

Figure 15 is a schematic diagram of a terminal device provided by an exemplary embodiment of the present application. Take the terminal device 1500 in this embodiment including a main device and a memory as an example for explanation:

The terminal device 1500 is provided with a main device 101 and the memory 200 described in the above embodiment, and the main device 101 and the memory 200 are electrically connected. The memory 200 may be provided inside the system-on-chip or outside the system-on-chip. It should be noted that in addition to the system on a chip, the terminal device 1500 may also include other necessary components, such as read-only memory (Read-Only Memory, ROM), display components, input units, audio circuits, speakers, microphones, Components such as power supply will not be described in detail in this embodiment.

The "plurality" mentioned in this article means two or more than two. "And/or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the related objects are in an "or" relationship.

The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims (18)

1. A memory, the memory includes: m storage element groups, each of the storage element groups includes at least one storage element, m is an integer greater than 1;

   The m storage element groups and the m groups of power lines are in one-to-one correspondence, and the m groups of power lines are controlled respectively;

   For the i-th storage element group among the m storage element groups, when the power line corresponding to the i-th storage element group is turned on, the storage elements in the i-th storage element group are at the upper level. Electrical state; when the power line corresponding to the i-th storage element group is disconnected, the storage elements in the i-th storage element group are in a power-off state, and i is a positive integer less than or equal to m.
2. The memory according to claim 1, wherein the power line is connected to one end of a switching element, the other end of the switching element is used to receive an input voltage, and the switching element is used to control the power line to be turned on or off. open.
3. The memory according to claim 2, wherein in the m groups of power lines, each group of power lines is connected to a switching element, and different power lines are connected to different switching elements;

   Wherein, the switching element connected to the i-th group of power lines in the m groups of power lines is used to control the i-th group of power lines to be turned on or off.
4. The memory according to claim 2, wherein among the m groups of power lines, there are at least two groups of power lines connected to the same switching element;

   Wherein, the switch element is used to control each group of power lines in the at least two groups of power lines to be turned on or off independently.
5. The memory according to any one of claims 2 to 4, wherein,

   The switching element is arranged inside the memory; or,

   The switching element is arranged inside the power management chip; or,

   The switching element is arranged between the memory and the power management chip;

   Wherein, the power management chip is used to provide the input voltage to the memory.
6. The memory according to any one of claims 2 to 5, wherein the control end of the switching element is connected to a control circuit, and the control circuit is used to control the switching element to be turned on or off to pass the switch. The components independently control the power on or off of each of the storage component groups.
7. The memory of claim 6, wherein:

   The control circuit is arranged inside the memory; or,

   The control circuit is arranged inside the power management chip; or,

   The control circuit is disposed on a circuit board used to carry the memory and/or the power management chip.
8. The memory according to claim 6 or 7, wherein the control circuit is used to send a control signal to the switching element according to the working mode, and the control signal is used to control the switching element to be turned on or off;

   Each storage element group in the memory is used to store data generated in the same working mode.
9. The memory of any one of claims 1 to 8, wherein at least one storage element group among the m storage element groups is configured to be enabled during system startup.
10. The memory according to any one of claims 1 to 9, wherein each said storage element group includes one said storage element.
11. The memory according to any one of claims 1 to 10, wherein,

    Each set of said power cords includes one power cord;

    or,

    Each group of the power lines includes a plurality of different power lines, and the plurality of different power lines are used to power different functional components in the storage element.
12. A system on a chip, the system on a chip includes: a memory and a power management chip;

    The memory is connected to the power management chip;

    The memory includes the memory according to any one of claims 1 to 11;

    The m sets of power lines are used to transmit the output voltage of the power management chip.
13. A terminal device, which is provided with the memory according to any one of claims 1 to 11.
14. The terminal device according to claim 13, wherein the terminal device is provided with a system on a chip, and the memory is provided outside the system on a chip, or the memory is provided inside the system on a chip.
15. A power supply control method, the method is executed by a control circuit, the control circuit is used to control the memory as claimed in claim 6, the method includes:

    A control signal is sent to the switching element, and the control signal is used to control the switching element to be turned on or off, so as to independently control the power on or off of each of the storage element groups through the switching element.
16. The method of claim 15, wherein sending a control signal to the switching element includes:

    Depending on the operating mode, the control signal is sent to the switching element.
17. The method of claim 16, wherein sending the control signal to the switching element according to the operating mode includes:

    Obtain power supply configuration information corresponding to the working mode, where the power supply configuration information is used to indicate the power supply status of each storage element group in the memory;

    According to the power supply configuration information, generate a control signal adapted to the power supply status of each of the storage element groups;

    The control signal is sent to the switching element.
18. The method according to claim 16 or 17, wherein each storage element group in the memory is used to store data generated in the same working mode.