CN113961490A

CN113961490A - System and method for monitoring DDR signal based on FPGA, FPGA and medium

Info

Publication number: CN113961490A
Application number: CN202111301327.9A
Authority: CN
Inventors: 袁丰磊
Original assignee: Shanghai Anlu Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co ltd
Priority date: 2021-11-04
Filing date: 2021-11-04
Publication date: 2022-01-21
Anticipated expiration: 2041-11-04
Also published as: CN113961490B

Abstract

The invention provides a system, a method, an FPGA and a medium for monitoring DDR (double data rate) signals based on an FPGA (field programmable gate array). the method can be applied to the FPGA, the FPGA is externally connected with a DDR target controller and DDR particles, and comprises a DDR signal analysis monitoring module and an IO (input/output) mode control module; in the read mode, the IO mode control module is used for controlling IO corresponding to the DDR target controller to be in an input state and controlling IO corresponding to the DDR particles to be in an output state; in the write mode, the IO mode control module is used for controlling IO corresponding to the DDR target controller to be in an output state and controlling IO corresponding to the DDR particles to be in an input state; the IO mode control module is also used for configuring the IO of the FPGA into an input state in a monitoring mode; and the DDR signal analysis monitoring module is used for acquiring each DDR DRAM signal to be monitored in a monitoring mode, and the system is used for monitoring and analyzing the DDR DRAM signals.

Description

System and method for monitoring DDR signal based on FPGA, FPGA and medium

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a system, a method, an FPGA and a medium for monitoring DDR signals based on an FPGA.

Background

A Double Data Rate Synchronous Dynamic Random Access Memory (DDR DRAM) plays a crucial role as the most important Memory device in an electronic system, and then since the DDR DRAM granule does not provide any debug interface, all accesses must be uniformly performed through a Double Data Rate Synchronous (DDR) bus, so that a very high requirement is placed on the reliability of a DDR bus controller. Debugging the location problem can be very difficult and time consuming if the DDR bus controller is defective. In addition, the performance optimization of the DDR DRAM as a main data storage device of the system has a great influence on the overall performance of the system, however, it is difficult to observe and confirm whether the access sequence of the DDR DRAM is fully optimized by analyzing the DDR controller, which causes the current debugging and positioning problem to be very difficult and time-consuming for development and debugging of the DDR controller.

Therefore, for development and debugging of the DDR controller, a DDR monitor analysis system is needed to monitor all events on the DRAM granule, so as to debug and optimize the DDR controller.

Disclosure of Invention

The invention provides a method, an FPGA and a medium for monitoring DDR signals based on the FPGA, which are used for monitoring and analyzing DDR DRAM signals.

In a first aspect, the invention provides a system for monitoring DDR signals based on an FPGA, which can be applied to the FPGA, wherein the FPGA is externally connected with a DDR target controller and DDR particles, and comprises a DDR signal analysis monitoring module and an IO mode control module; the DDR target controller is used for reading data from DDR particles in a reading mode, wherein in the reading mode, the IO mode control module is used for controlling IO corresponding to the DDR target controller to be in an input state and controlling IO corresponding to the DDR particles to be in an output state; the DDR target controller is further used for driving write data corresponding to the DDR target controller to the DDR particles in a write mode, wherein in the write mode, the IO mode control module is used for controlling IO corresponding to the DDR target controller to be in an output state and controlling IO corresponding to the DDR particles to be in an input state; the IO mode control module is also used for configuring the IO of the FPGA into an input state in a monitoring mode; and the DDR signal analysis monitoring module is used for acquiring each DDR dynamic random access memory DRAM signal to be monitored in a monitoring mode.

The method for monitoring DDR signals based on the FPGA has the advantages that: due to the programmable characteristic of the FPGA, IO pins supporting a DDR DRAM interface can be programmed, the IO can be configured into a required mode according to needs, for example, all DDR DRAM signal pins of a monitoring end are configured into an input mode to monitor DDR DRAM signals, the system has the advantages of flexibility and low cost, and the characteristic functions of various DDR DRAM controllers can be flexibly supported.

In a possible embodiment, the DDR signal analyzing and monitoring module is further configured to analyze each DDR DRAM signal and the related read-write data information, and analyze and record the related timing information in real time. By analyzing each DDR DRAM signal and the relevant read-write data information, the embodiment can flexibly record, report or further analyze and process the observed and analyzed information as required, such as performing performance statistical analysis, monitoring specified addresses or data, and specifying a time sequence checking function under a protocol mode.

In one possible embodiment, the DDR DRAM signals include: command and address CA signals and bi-directional data DQ/DQs signals. The DDR DRAM monitoring, analyzing and recording function is achieved through the FPGA, and the DDR DRAM monitoring, analyzing and recording function is connected to all DDR DRAM target signals including all CA and DQ/DQS signals through programmable IO.

In a possible embodiment, the DDR interface analysis monitoring module, after acquiring and parsing the DRAM command in the monitoring mode, is further configured to: and identifying an illegal DRAM command, and prompting error reporting information and error reporting time related to the illegal DRAM command in error reporting information of the FPGA.

In one possible embodiment, the DDR particles are any one of DDR3, DDR4, DDR5, LPDDR3, LPDDR 4.

In a second aspect, an embodiment of the present invention provides a method for monitoring DDR signals based on an FPGA, where the method may be applied to a field programmable gate array FPGA, where the FPGA is externally connected with a double-rate synchronous DDR particle, and the method includes:

in a read mode, controlling the IO corresponding to the DDR target controller to be in an input state, controlling the IO corresponding to the DDR particles to be in an output state, and reading data from the DDR particles;

in a write mode, controlling IO corresponding to a DDR target controller to be in an output state, controlling IO corresponding to DDR particles to be in an input state, and driving write data corresponding to the DDR target controller to the DDR particles;

configuring IO of the FPGA into an input state in a monitoring mode;

in monitor mode, each monitored DDR DRAM signal is acquired.

In a possible embodiment, the method further comprises:

resolving DRAM commands and related read-write data information of the dynamic random access memory, and resolving and recording related time sequence information in real time.

In one possible embodiment, the DDR DRAM signals include: command and Address (CA) signals and bi-directional Data (DQ/DQs) signals.

In a possible embodiment, the method further comprises: and identifying an illegal DRAM command, and prompting error reporting information and error reporting time related to the illegal DRAM command in error reporting information of the FPGA.

In a third aspect, an embodiment of the present invention further provides an FPGA, wherein the memory is used for storing one or more computer programs; the one or more computer programs stored in the memory, when executed by the processor, enable the FPGA to implement any one of the possible design approaches of the second aspect described above.

In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium includes a computer program, and when the computer program runs on a terminal device, the computer program causes the terminal device to perform any one of the possible design methods of any one of the aspects.

In a fifth aspect, an embodiment of the present invention further provides a method including a computer program product, when the computer program product runs on a terminal device, causing the terminal device to execute any one of the possible designs of any one of the aspects.

For the beneficial effects of the second to fifth aspects, reference may be made to the description of the first aspect, and the description is not repeated.

Drawings

Fig. 1 is a schematic diagram of a system for monitoring DDR signals based on an FPGA according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a method for monitoring DDR signals based on an FPGA according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.

Detailed Description

The technical solution of the present invention will be described with reference to the accompanying drawings.

Hereinafter, some terms referred to hereinafter will be explained to facilitate understanding by those skilled in the art.

(1) Application Specific Integrated Circuit (ASIC)

An ASIC is a special purpose chip that is specialized chip for certain specific requirements. Such as a dedicated audio processor and a video processor, and currently, many dedicated Artificial Intelligence (AI) chips can also be regarded as an ASIC.

(2) FPGA (field programmable gate array)

An FPGA is a logic device composed of many logic units, wherein the logic units include gates, lookup tables and flip-flops, and the FPGA has rich hardware resources, strong parallel processing capability and flexible reconfigurable capability, and is increasingly and widely applied in many fields of data processing, communication and network. The FPGA is a product developed further on the basis of programmable devices such as PAL, GAL and CPLD, and appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), thereby not only solving the defects of the custom circuit, but also overcoming the defect of limited gate circuits of the original programmable devices.

The method for monitoring DDR signals based on the FPGA can be based on the Programmable characteristic of the FPGA, IO pins supporting DDR DRAM interfaces can be programmed, all the IO pins of a monitoring end can be configured into a required mode according to needs, for example, all DDR DRAM signal pins of the monitoring end are configured into an input mode, so that the DDR DRAM signals can be monitored, and the system has the advantages of flexibility and low cost, and can flexibly support the characteristic functions of various DDR DRAM controllers.

The technical solution in the embodiment of the present invention is described below with reference to the drawings in the embodiment of the present invention. In the description of the embodiments of the present invention, the terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, such as "one or more", unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of the present invention, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe an association relationship that associates objects, meaning that three relationships may exist; for example, a and/or B, may represent: a alone, both A and B, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the invention. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more, but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise. The term "coupled" includes both direct and indirect connections, unless otherwise noted. "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

In the embodiments of the present invention, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described as "exemplary" or "e.g.," an embodiment of the present invention is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "e.g.," is intended to present relevant concepts in a concrete fashion.

As shown in fig. 1, a communication system suitable for use in embodiments of the present invention includes an FPGA10, DDR particles 20, and DDR target controller 30. The FPGA10 is externally connected with a Double Data Rate (DDR) DDR particle 20 and a DDR target controller 30, where the specification of the DDR particle 20 may be any one of DDR3, DDR4, DDR5, LPDDR3, and LPDDR 4. The FPGA10 includes a DDR signal analysis monitoring module 101 and an Input/Output (IO) mode control module 102.

The terminal device comprising the ASIC/FPGA of the present invention may also be referred to as a User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user device. The terminal device in the embodiment of the present invention may be a mobile phone (mobile phone), a tablet computer (Pad), a smart printer, a train detector, a gas station detector, a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in self driving (self driving), a wireless terminal in remote medical (remote medical), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety, a wireless terminal in city (smart city), and a wireless terminal in smart home (smart home). The embodiment of the invention does not limit the application scenarios.

It should be understood that fig. 1 is a simplified schematic diagram of an example for ease of understanding only, and that other image signal processors may be included in the communication system or other terminal devices may be included, which are not shown in fig. 1.

The method for monitoring the DDR signal based on the FPGA provided by the embodiment of the invention can be executed by the FPGA10 in the communication system shown in FIG. 1. It is to be understood that the steps performed by FPGA10 may also be specifically performed by one or more modules or components of FPGA10 in the present invention. As shown in fig. 2, a method for monitoring DDR signals based on an FPGA according to an embodiment of the present invention is shown, where the method includes:

s201, in a read mode, the IO mode control module 102 controls an IO corresponding to the DDR target controller 30 to be in an input state, and controls an IO corresponding to the DDR particle 20 to be in an output state, so that the DDR target controller 30 reads data from the DDR particle 20 in the read mode; in the write mode, the IO mode control module 102 controls the IO corresponding to the DDR target controller 30 to be in an output state, and controls the IO corresponding to the DDR particle 20 to be in an input state, so that the DDR target controller 30 drives write data corresponding to the DDR target controller 30 to the DDR particle 20 in the write mode.

S202, in the monitoring mode, the IO mode control module 102 configures the IO of the FPGA into an input state.

S203, in the monitoring mode, the DDR signal analyzing and monitoring module 101 obtains each monitored DDR DRAM signal.

Wherein the DDR DRAM signal may include: command and Address (CA) signals and Data Strobe signal (DQ/DQs) signals in both directions.

In the method, the IO mode of the FPGA is configured by utilizing the programmable characteristic of the FPGA, so that all DDR DRAM signals can be observed, and expensive and low-efficiency oscilloscopes can be avoided from being used for observing the DDR signals one by one.

In a possible embodiment, the method further includes: the DDR signal analysis monitoring module 101 analyzes the DRAM command and the related read-write data information, and analyzes and records the related timing information in real time. The DDR DRAM signal observed by the IO of the FPGA is further analyzed and processed according to the requirement by utilizing the abundant programmable logic resource of the FPGA, and various customized events can be recorded, monitored, triggered and reported for analysis, so that a flexible and low-cost DDR protocol analysis scheme is realized, and the required analysis or monitoring function can be customized according to the function of a test or monitoring target.

In another possible embodiment, the DDR signal analysis monitoring module 101 may further identify an illegal DRAM command, and prompt error information and error time related to the illegal DRAM command in the error information of the FPGA. The method can help monitor all events on the DRAM particle, so as to debug and optimize the DDR controller.

In the embodiment provided by the invention, the monitoring of the DDR DRAM interface is realized by taking flexibly configured FPGA IO as an input state, all DDR DRAM signal pins of a monitoring end are required to be configured into an input mode, and a reference level and a termination resistance are configured according to a monitoring environment, for example, all DDR DRAM signal pins of the monitoring end are configured into the input mode to realize the monitoring of DDR DRAM signals.

Fig. 3 shows a schematic structural diagram of a terminal device 300. The terminal device 300 may include the FPGA described above, and is configured to implement the method described in the above method embodiment, which may be referred to in the description of the above method embodiment. The terminal device 300 may be a chip, a network device (e.g., a base station), a terminal device or other network device.

The terminal device 300 comprises one or more processors 301. The processor 301 may be a general purpose processor or a special purpose processor. For example, a baseband processor, or a central processor. The baseband processor may be used to process communication protocols and communication data, and the central processor may be used to control a communication device (e.g., a base station, a terminal, or a chip), execute a software program, and process data of the software program. The communication device may include a transceiving unit to enable input (reception) and output (transmission) of signals. For example, the communication device may be a chip, and the transceiving unit may be an input and/or output circuit of the chip, or a communication interface. The chip can be used for a terminal or a base station or other network equipment. As another example, the communication device may be a terminal or a base station or other network equipment, and the transceiver unit may be a transceiver or a radio frequency chip.

The terminal device 300 comprises one or more of the processors 301, and the one or more processors 301 may implement the method shown in the embodiment shown in fig. 2.

Optionally, the processor 301 may also implement other functions besides the method of the embodiment shown in fig. 2.

Optionally, in one design, the processor 301 may also include instructions 303, which may be executed on the processor, so that the terminal device 300 performs the method described in the above method embodiment.

In yet another possible design, the terminal device 300 may include one or more memories 302 having instructions 304 stored thereon, which are executable on the processor, so that the terminal device 300 performs the method described in the above method embodiment. Optionally, the memory may further store data therein. Instructions and/or data may also be stored in the optional processor. For example, the one or more memories 302 may store the correspondence described in the above embodiments, or related parameters or tables referred to in the above embodiments. The processor and the memory may be provided separately or may be integrated together.

In yet another possible design, the terminal device 300 may further include a communication interface 305 and an antenna 306. The processor 301 may be referred to as a processing unit and controls a communication device (terminal or base station). The communication interface 305 may be referred to as a transceiver, transceiving circuitry, or transceiver for implementing transceiving functions of a communication device through the antenna 306.

It should be understood that the processor in the embodiments of the present invention may be a Central Processing Unit (CPU), and the processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

It should be noted that the processor in the embodiments of the present invention may be an integrated circuit chip having signal processing capability. In implementation, the steps of the above method embodiments may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash, rom, prom or eprom, or a storage medium with registers that are well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

It will be appreciated that the memory in embodiments of the invention may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

An embodiment of the present invention further provides a computer-readable medium, on which a computer program is stored, where the computer program, when executed by a computer, implements the method of any of the above method embodiments.

The embodiment of the invention also provides a computer program product, and the computer program product realizes the method of any one of the above method embodiments when being executed by a computer.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with embodiments of the invention, to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or can be an integrated server, data center data storage device that includes one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., Digital Video Disk (DVD)), or a semiconductor medium (e.g., Solid State Disk (SSD)).

It should be understood that the processing device may be a chip, the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit or an integrated circuit; when implemented in software, the processor may be a general-purpose processor implemented by reading software code stored in a memory, which may be integrated in the processor, located external to the processor, or stand-alone.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In short, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A system for monitoring DDR signals based on an FPGA is characterized in that the system is applied to a field programmable gate array FPGA, the FPGA is externally connected with double-rate synchronous DDR particles and a DDR target controller, and the FPGA comprises a DDR signal analysis monitoring module and an input/output IO mode control module;

the IO mode control module is used for controlling IO corresponding to the DDR target controller to be in an input state and controlling IO corresponding to the DDR particles to be in an output state in a read mode, so that the DDR target controller reads data from the DDR particles in the read mode;

the IO mode control module is further configured to control IO corresponding to a DDR target controller to be in an output state and control IO corresponding to the DDR particles to be in an input state in a write mode, so that the DDR target controller drives write data corresponding to the DDR target controller to the DDR particles in the write mode;

the IO mode control module is also used for configuring the IO of the FPGA into an input state in a monitoring mode;

and the DDR signal analysis monitoring module is used for acquiring each DDR dynamic random access memory DRAM signal to be monitored in a monitoring mode.

2. The system of claim 1, wherein the DDR signal analysis and monitoring module is further configured to parse and record each DDR DRAM signal and associated read-write data information, and to parse and record associated timing information in real time.

3. The system of claim 1 or 2, wherein the DDR DRAM signals comprise: command and address CA signals and bi-directional data DQ/DQs signals.

4. The system of claim 1 or 2, wherein the DDR interface analysis monitor module, after fetching and parsing DRAM commands in monitor mode, is further configured to:

and identifying an illegal DRAM command, and prompting error reporting information and error reporting time related to the illegal DRAM command in error reporting information of the FPGA.

5. The system of claim 1 or 2, wherein the DDR particles are any one of DDR3, DDR4, DDR5, LPDDR3, LPDDR 4.

6. A method for monitoring DDR signals based on an FPGA is characterized in that the method is applied to a field programmable gate array FPGA, the FPGA is externally connected with double-rate synchronous DDR particles and a DDR target controller, and the method comprises the following steps:

in a read mode, controlling the IO corresponding to the DDR target controller to be in an input state, and controlling the IO corresponding to the DDR particles to be in an output state, so that the DDR target controller reads data from the DDR particles in the read mode;

in a write mode, controlling IO corresponding to a DDR target controller to be in an output state, and controlling IO corresponding to DDR particles to be in an input state, so that write data corresponding to the DDR target controller is driven to the DDR particles by the DDR target controller in the write mode; configuring IO of the FPGA into an input state in a monitoring mode;

and acquiring the signals of each DDR dynamic random access memory DRAM to be monitored in the monitoring mode.

7. The method of claim 6, further comprising:

8. The method of claim 6 or 7, wherein the DDR DRAM signaling comprises: command and address CA signals and bi-directional data DQ/DQs signals.

9. The method according to claim 6 or 7, characterized in that the method further comprises:

10. The method as claimed in claim 6 or 7, wherein the DDR particles are any one of DDR3, DDR4, DDR5, LPDDR3, LPDDR 4.

11. An FPGA, characterized in that it comprises a system according to any one of claims 1 to 5.

12. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 6 to 10.