CN113961490B - System, method, FPGA and medium for monitoring DDR signal based on FPGA - Google Patents

Abstract

The invention provides a system, a method, an FPGA and a medium for monitoring DDR signals based on the FPGA, wherein the method can be applied to the FPGA, the FPGA is externally connected with a DDR target controller and DDR particles, and the FPGA comprises a DDR signal analysis and monitoring module and an IO mode control module; in a read mode, the IO mode control module is used for controlling the IO corresponding to the DDR target controller to be in an input state and controlling the IO corresponding to the DDR particles to be in an output state; in the write mode, the IO mode control module is used for controlling the IO corresponding to the DDR target controller to be in an output state and controlling the IO corresponding to the DDR particles to be in an input state; the IO mode control module is also used for configuring the IO of the FPGA into an input state in a monitoring mode; the DDR signal analysis and monitoring module is used for acquiring each monitored DDR DRAM signal in a monitoring mode, and the system is used for monitoring and analyzing the DDR DRAM signal.

Description

System, method, FPGA and medium for monitoring DDR signal based on FPGA

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a system, a method, an FPGA and a medium for monitoring DDR signals based on the FPGA.

Background

Double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR DRAM) plays a vital role as the most important memory device in electronic systems, and then since DDR DRAM particles do not provide any debug interface, all accesses must be made uniformly over the double rate synchronous (Double Data Rate Synchronous, DDR) bus, thus placing very high demands on the reliability of DDR bus controllers. Debug localization problems can be very difficult and time consuming if the DDR bus controller is defective. In addition, the DDR DRAM is used as a main data storage device of the system, and whether the performance is optimized has a great influence on the overall performance of the system, however, it is difficult to observe and confirm whether the DDR controller is fully optimized for the access sequence of the DDR DRAM, so that the current debugging and positioning problem is very difficult and time-consuming for the development and debugging of the DDR controller.

Therefore, for development and debugging of DDR controllers, there is a need for a DDR monitoring and analysis system to monitor all events on DRAM particles, thereby debugging and optimizing DDR controllers.

Disclosure of Invention

The invention provides a method for monitoring DDR signals based on an FPGA, the FPGA and a medium, which are used for monitoring and analyzing DDR DRAM signals.

In a first aspect, the invention provides a system for monitoring DDR signals based on an FPGA, the method can be applied to the FPGA, the FPGA is externally connected with a DDR target controller and DDR particles, and the FPGA comprises a DDR signal analysis monitoring module and an IO mode control module; the DDR target controller is used for reading data from the DDR particles in a reading mode, wherein in the reading mode, the IO mode control module is used for controlling the IO corresponding to the DDR target controller to be in an input state and controlling the IO corresponding to the DDR particles to be in an output state; the DDR target controller is also used for driving write data corresponding to the DDR target controller to DDR particles in a write mode, wherein in the write mode, the IO mode control module is used for controlling IO corresponding to the DDR target controller to be in an output state and controlling IO corresponding to the DDR particles to be in an input state; the IO mode control module is also used for configuring the IO of the FPGA into an input state in a monitoring mode; and the DDR signal analysis and monitoring module is used for acquiring the monitored DDR dynamic random access memory DRAM signals in a monitoring mode.

The method for monitoring DDR signals based on the FPGA has the beneficial effects that: because of the programmable characteristic of the FPGA, the IO pins supporting the DDR DRAM interface can be programmed, and the IO pins can be configured into a required mode according to the requirement, for example, all DDR DRAM signal pins at a monitoring end are configured into an input mode, so that the DDR DRAM signal can be monitored.

In a possible embodiment, the DDR signal analysis and monitoring module is further configured to parse each DDR DRAM signal and related read/write data information, and parse and record related timing information in real time. According to the embodiment, through analyzing the DDR DRAM signals and related read-write data information, the information analyzed by observation can be flexibly recorded, reported or subjected to further analysis processing, such as performance statistics analysis, monitoring of designated addresses or data, and a time sequence checking function in a designated protocol mode.

In one possible embodiment, the signals of the DDR DRAM include: command and address CA signals and bi-directional data DQ/DQs signals. The invention uses FPGA to realize the function of monitoring, analyzing and recording DDR DRAM, and is connected to all DDR DRAM target signals, including all CA and DQ/DQS signals, through programmable IO.

In one possible embodiment, the DDR interface analysis monitoring module, after acquiring and parsing the DRAM command in the monitoring mode, is further configured to: identifying illegal DRAM commands, and prompting error reporting information and error reporting time related to the illegal DRAM commands in the error reporting information of the FPGA.

In one possible embodiment, the DDR particles are any one of DDR3, DDR4, DDR5, LPDDR3, LPDDR 4.

In a second aspect, an embodiment of the present invention provides a method for monitoring DDR signals based on an FPGA, where the method may be applied to a field programmable gate array FPGA, the FPGA is externally connected with double rate synchronous DDR particles, the method includes:

in a reading mode, controlling the IO corresponding to the DDR target controller to be in an input state, controlling the IO corresponding to the DDR particles to be in an output state, and reading data from the DDR particles;

in a writing mode, controlling IO corresponding to a DDR target controller to be in an output state, controlling IO corresponding to DDR particles to be in an input state, and driving write data corresponding to the DDR target controller to the DDR particles;

in a monitoring mode, configuring IO of the FPGA into an input state;

in the monitoring mode, each monitored DDR DRAM signal is acquired.

In one possible embodiment, the method further comprises:

and analyzing the DRAM command and related read-write data information, and analyzing and recording related time sequence information in real time.

In one possible embodiment, the signals of the DDR DRAM include: command and address (Command andAddress, CA) signals and bi-directional data (Data and Data Strobe signal, DQ/DQs) signals.

In one possible embodiment, the method further comprises: identifying illegal DRAM commands, and prompting error reporting information and error reporting time related to the illegal DRAM commands in the error reporting information of the FPGA.

In a third aspect, embodiments of the present invention further provide an FPGA, wherein the memory is configured to store one or more computer programs; the one or more computer programs, when executed by the processor, enable the FPGA to implement the method of any one of the possible designs of the second aspect described above.

In a fourth aspect, embodiments of the present invention also provide a computer readable storage medium, the computer readable storage medium comprising a computer program, which when run on a terminal device causes the terminal device to perform the method of any one of the possible designs of the above aspect.

In a fifth aspect, embodiments of the present invention also provide a method comprising a computer program product, which when run on a terminal device, causes the terminal device to perform any one of the possible designs of the above aspect.

The advantageous effects of the second to fifth aspects may be referred to the description of the first aspect, and the detailed description will not be repeated.

Drawings

FIG. 1 is a schematic diagram of a system for monitoring DDR signals based on an FPGA according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart of a method for monitoring DDR signals based on an FPGA according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.

Detailed Description

The technical scheme of the invention will be described below with reference to the accompanying drawings.

The following is a description of some of the terms referred to below to facilitate understanding by those skilled in the art.

(1) Application specific integrated circuit (application specific integrated circuit, ASIC)

The ASIC is a special chip, which is a chip that is specially customized for a specific requirement. Such as a dedicated audio processor, video processor, while many dedicated artificial intelligence (artificial intelligence, AI) chips can now be considered as one of the ASICs.

(2) Field programmable gate array (fieldprogrammable gate array, FPGA)

FPGAs are logic devices made up of many logic cells, including gates, look-up tables, and flip-flops, which have rich hardware resources, powerful parallel processing capabilities, and flexible reconfigurable capabilities, and are increasingly being used in many fields of data processing, communications, and networking. FPGA is a product further developed on the basis of PAL, GAL, CPLD programmable devices, and is developed as a semi-custom circuit in the field of special chips (ASIC), so that the defects of custom circuits are overcome, and the defect of limited gate numbers of the original programmable devices is overcome.

The invention provides a method for monitoring DDR signals based on FPGA (Field-Programmable gate array) by adding double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), which can be based on the Programmable characteristic of the FPGA, and can support the IO pins of DDR DRAM interface to be Programmable, and can configure the IO pins into required modes according to the need, such as configuring all DDR DRAM signal pins of a monitoring end into an input mode, so as to realize the monitoring of DDR DRAM signals.

The technical solutions in the embodiments of the present invention are described below with reference to the accompanying drawings in the embodiments of the present invention. In the description of embodiments of the invention, the terminology used in the embodiments below is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary. It should also be understood that in the following embodiments of the present invention, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe an association relationship of associated objects, meaning that there may be three relationships; for example, a and/or B may represent: a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the invention. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment, but mean "one or more, but not all, embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. The term "coupled" includes both direct and indirect connections, unless stated otherwise. The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

In embodiments of the invention, the word "exemplary" or "such as" is used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" or "e.g." is intended to present the relevant concepts in a concrete manner.

As shown in fig. 1, a communication system suitable for use in an embodiment of the present invention includes an FPGA10, a DDR granule 20, and a DDR target controller 30. The FPGA10 is externally connected with a double rate synchronous (Double Data Rate Synchronous, DDR) DDR granule 20 and a DDR target controller 30, wherein the DDR granule 20 can be any one of DDR3, DDR4, DDR5, LPDDR3, and LPDDR 4. The FPGA10 includes a DDR signal analysis monitoring module 101 and an Input/Output (IO) mode control module 102.

The terminal device comprising ASIC/FPGA in the present invention may also be referred to as User Equipment (UE), access terminal, subscriber unit, subscriber station, mobile station, remote terminal, mobile device, user terminal, wireless communication device, user agent or user equipment. The terminal device in the embodiment of the present invention may be a mobile phone (mobile phone), a tablet computer (Pad), a smart printer, a train detector, a gas station detector, a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in self driving (self driving), a wireless terminal in remote medical (remote media), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation security (transportation safety), a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home). The embodiment of the invention does not limit the application scene.

It should be appreciated that fig. 1 is a simplified schematic diagram that is merely illustrative for ease of understanding, and that other image signal processors may be included in the communication system or other terminal devices may be included, not shown in fig. 1.

The method for monitoring DDR signals based on the FPGA provided by the embodiment of the invention can be executed by the FPGA10 in the communication system shown in fig. 1. It should be understood that in the present invention, the steps performed by the FPGA10 may also be performed specifically by one or more modules or components of the FPGA 10. As shown in fig. 2, a method for monitoring DDR signals based on an FPGA according to an embodiment of the present invention is shown, where the method includes:

s201, in a read mode, the IO mode control module 102 controls the IO corresponding to the DDR target controller 30 to be in an input state and controls the IO corresponding to the DDR particle 20 to be in an output state, so that the DDR target controller 30 reads data from the DDR particle 20 in the read mode; in the write mode, the IO mode control module 102 controls the IO corresponding to the DDR target controller 30 to be in an output state and controls the IO corresponding to the DDR granule 20 to be in an input state, so that the DDR target controller 30 drives write data corresponding to the DDR target controller 30 to the DDR granule 20 in the write mode.

S202, in the monitoring mode, the IO mode control module 102 configures the IO of the FPGA into an input state.

S203, in the monitoring mode, the DDR signal analysis monitoring module 101 acquires the DDR DRAM signals to be monitored.

Wherein, the signal of the DDR DRAM may include: command and address (Command and Address, CA) signals and bi-directional data (Data and Data Strobe signal, DQ/DQs) signals.

In the method, the IO mode of the FPGA is configured by utilizing the programmable characteristic of the FPGA so that all DDR DRAM signals can be observed, and the problem that an expensive and low-efficiency oscilloscope is used for observing DDR signals one by one can be avoided.

In one possible embodiment, the method further comprises: the DDR signal analysis and monitoring module 101 analyzes the DRAM command and the related read-write data information, and analyzes and records the related time sequence information in real time. The DDR DRAM signals observed by the IO of the FPGA are further analyzed and processed according to the need by utilizing the abundant programmable logic resources of the FPGA, various customized events can be recorded, monitored and promoted, and reported for analysis, so that a flexible and low-cost DDR protocol analysis scheme is realized, and the required analysis or monitoring functions can be customized according to the functions of the test or monitoring targets.

In another possible embodiment, the DDR signal analysis monitoring module 101 may also identify an illegal DRAM command, and prompt the error reporting information and the error reporting time related to the illegal DRAM command in the error reporting information of the FPGA. The method can help monitor all events on the DRAM particles to debug and optimize the DDR controller.

In the embodiment provided by the invention, through flexibly configured IO of the FPGA as an input state, the DDR DRAM interface is monitored, all DDR DRAM signal pins of a monitoring end are required to be configured into an input mode, and a reference level and a termination resistor are configured according to a monitoring environment, for example, all DDR DRAM signal pins of the monitoring end are configured into the input mode, so that the DDR DRAM signal is monitored.

Fig. 3 shows a schematic structure of a terminal device 300. The terminal device 300 may comprise the FPGA described above for implementing the method described in the method embodiments described above, see the description in the method embodiments described above. The terminal device 300 may be a chip, a network device (e.g., a base station), a terminal device, or other network device.

The terminal device 300 comprises one or more processors 301. The processor 301 may be a general purpose processor or a special purpose processor. For example, a baseband processor, or a central processing unit. The baseband processor may be used to process communication protocols and communication data, and the central processor may be used to control a communication device (e.g., a base station, terminal, or chip), execute a software program, and process the data of the software program. The communication device may comprise a transceiver unit for enabling input (reception) and output (transmission) of signals. For example, the communication device may be a chip, and the transceiver unit may be an input and/or output circuit of the chip, or a communication interface. The chip may be used for a terminal or a base station or other network device. As another example, the communication device may be a terminal or a base station or other network equipment, and the transceiver unit may be a transceiver, a radio frequency chip.

The terminal device 300 comprises one or more of the processors 301, which one or more processors 301 may implement the method shown in the embodiment shown in fig. 2.

Alternatively, the processor 301 may implement other functions in addition to the method of implementing the embodiment shown in fig. 2.

Optionally, in a design, the processor 301 may also include instructions 303, which may be executed on the processor, to cause the terminal device 300 to perform the method described in the above method embodiments.

In yet another possible design, the terminal device 300 may include one or more memories 302 having instructions 304 stored thereon that are executable on the processor to cause the terminal device 300 to perform the methods described in the method embodiments above. Optionally, the memory may further store data. The optional processor may also store instructions and/or data. For example, the one or more memories 302 may store the correspondence described in the above embodiments, or related parameters or tables involved in the above embodiments. The processor and the memory may be provided separately or may be integrated.

In yet another possible design, the terminal device 300 may further include a communication interface 305 and an antenna 306. The processor 301 may be referred to as a processing unit for controlling the communication device (terminal or base station). The communication interface 305 may be referred to as a transceiver, transceiver circuitry, or transceiver for implementing the transceiver functions of the communication device via the antenna 306.

It is to be appreciated that the processor in embodiments of the invention may be a central processing unit (Central Processing Unit, CPU) that may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate arrays (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, various media in which program codes can be stored.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

It should be noted that the processor in the embodiments of the present invention may be an integrated circuit chip with signal processing capability. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor. The steps of the method disclosed in connection with the embodiments of the present invention may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers, as well as storage media well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.

It will be appreciated that the memory in embodiments of the invention may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (Double Data Rate SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

The present invention also provides a computer readable medium having stored thereon a computer program which, when executed by a computer, implements the method of any of the method embodiments described above.

The present invention also provides a computer program product which, when executed by a computer, implements the method of any of the method embodiments described above.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave) means. The computer readable storage medium can be any available medium that can be accessed by a computer or a server, data center data storage device that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a high-density digital video disc (Digital Video Disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)).

It should be understood that the processing device may be a chip, and the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit or an integrated circuit; when implemented in software, the processor may be a general-purpose processor, implemented by reading software code stored in a memory, which may be integrated in the processor, or may reside outside the processor, and exist separately.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In summary, the foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. The system for monitoring DDR signals based on the FPGA is characterized by being applied to a Field Programmable Gate Array (FPGA), wherein the FPGA is externally connected with double-rate synchronous DDR particles and a DDR target controller, and the FPGA comprises a DDR signal analysis monitoring module and an input/output IO mode control module;

the IO mode control module is used for controlling the IO corresponding to the DDR target controller to be in an input state and controlling the IO corresponding to the DDR particles to be in an output state in a read mode, so that the DDR target controller can read data from the DDR particles in the read mode;

the IO mode control module is further configured to control an IO corresponding to a DDR target controller to be in an output state and control an IO corresponding to the DDR granule to be in an input state in a write mode, so that the DDR target controller drives write data corresponding to the DDR target controller to the DDR granule in the write mode;

the IO mode control module is also used for configuring IO of the FPGA into an input state in a monitoring mode;

the DDR signal analysis and monitoring module is used for acquiring the monitored DRAM signals of the DDR dynamic random access memories in a monitoring mode.

2. The system of claim 1, wherein the DDR signal analysis and monitoring module is further configured to parse each DDR DRAM signal and associated read and write data information, and parse record associated timing information in real time.

3. The system of claim 1 or 2, wherein the signal of the DDR DRAM comprises: command and address CA signals and bi-directional data DQ/DQs signals.

4. The system of claim 1 or 2, wherein the DDR interface analysis monitoring module, after retrieving and parsing DRAM commands in a monitoring mode, is further configured to:

identifying illegal DRAM commands, and prompting error reporting information and error reporting time related to the illegal DRAM commands in the error reporting information of the FPGA.

5. The system of claim 1 or 2, wherein the DDR particles are any one of DDR3, DDR4, DDR5, LPDDR3, LPDDR 4.

6. The method for monitoring DDR signals based on the FPGA is characterized by being applied to a Field Programmable Gate Array (FPGA), wherein the FPGA is externally connected with double-rate synchronous DDR particles and a DDR target controller, and the method comprises the following steps:

in a read mode, controlling the IO corresponding to the DDR target controller to be in an input state and controlling the IO corresponding to the DDR particles to be in an output state, so that the DDR target controller reads data from the DDR particles in the read mode;

in a write mode, controlling IO corresponding to a DDR target controller to be in an output state, and controlling IO corresponding to DDR particles to be in an input state, so that the DDR target controller drives write data corresponding to the DDR target controller to the DDR particles in the write mode; in a monitoring mode, configuring IO of the FPGA into an input state;

in the monitoring mode, each DDR DRAM signal to be monitored is acquired.

7. The method of claim 6, wherein the method further comprises:

and analyzing the DRAM command and related read-write data information, and analyzing and recording related time sequence information in real time.

8. The method of claim 6 or 7, wherein the DDR DRAM signal comprises: command and address CA signals and bi-directional data DQ/DQs signals.

9. The method according to claim 6 or 7, characterized in that the method further comprises:

identifying illegal DRAM commands, and prompting error reporting information and error reporting time related to the illegal DRAM commands in the error reporting information of the FPGA.

10. The method of claim 6 or 7, wherein the DDR particles are any one of DDR3, DDR4, DDR5, LPDDR3, LPDDR 4.

11. An FPGA comprising the system of any one of claims 1 to 5.

12. A computer readable storage medium having a computer program stored therein, characterized in that the computer program, when executed by a processor, implements the method of any of claims 6 to 10.