WO2022178772A1

WO2022178772A1 - Memory refresh method, memory, controller, and storage system

Info

Publication number: WO2022178772A1
Application number: PCT/CN2021/077941
Authority: WO
Inventors: 罗玉; 冯辉宇; 汪思君
Original assignee: 华为技术有限公司
Priority date: 2021-02-25
Filing date: 2021-02-25
Publication date: 2022-09-01
Also published as: CN116897395A

Abstract

Disclosed in the present application are a memory refresh method, a memory, a controller, and a storage system. When the memory refresh method is applied to the controller, the controller is used for controlling the memory; a storage area of the memory comprises at least one bank; at least one target bank to be refreshed is determined according to an idle state of at least one bank in the storage area; refresh indication information is generated and sent to the memory according to said at least one target bank; and the refresh indication information is used for controlling the memory to refresh said at least one target bank.

Description

A memory refresh method, memory, controller and storage system

technical field

The present application relates to the field of memory refresh technologies, and in particular, to a memory refresh method, a memory, a controller, and a storage system.

Background technique

Capacitive memory is one of the key components in current digital systems because of its low price and high storage density. For example, dynamic random access memory (DRAM) realizes data storage by using the storage function of capacitance to charge. For another example, double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM) has been widely used in many fields due to its large capacity, high speed and good compatibility.

Specifically, the storage space of the memory is generally configured as N banks (banks) arranged in parallel, where N is an integer greater than or equal to 1. Each bank can be understood as a two-dimensional storage array, in which the horizontal direction is called a row and the vertical direction is called a column. A memory cell in the memory array includes a capacitor, which can store 1 bit of data. Since the charge in the capacitor will be continuously lost with leakage, the data in the capacitor must be periodically read and rewritten to compensate for the lost charge. This operation is also called refresh. That is, DRAM needs to be refreshed periodically to retain the data in RAM, so refresh is an important operation in DRAM.

At present, the number of technical solutions for refreshing the memory is limited and cannot be flexibly adapted to different application scenarios. Therefore, the technical solution for refreshing the memory needs to be further studied.

SUMMARY OF THE INVENTION

The present application provides a memory refresh method, a memory, a controller and a storage system, which are used to improve the refresh effect of the memory.

In a first aspect, the present application provides a method for refreshing a memory, which is applied to a controller; the controller is used to control the memory; the storage area of the memory includes at least one bank; the method includes:

Determine at least one target bank to be refreshed according to the idle state of at least one bank in the storage area;

According to the at least one target bank to be refreshed, refresh indication information is generated and sent to the memory; the refresh indication information is used to control the memory to refresh the at least one target bank to be refreshed.

Through the above method, the bank is refreshed according to the idle state of at least one bank in the storage area, and the read and write delay caused by the interruption of the read and write command by the refresh command can be avoided on the premise of ensuring the refresh, and the read and write commands can be improved. Performance and the efficiency with which the memory executes read and write commands.

In a possible implementation manner, the determining at least one target bank to be refreshed includes: determining, in at least one bank in an idle state, at least one candidate bank whose number of under-refreshing times reaches a first threshold, wherein the under-refreshing The number of times is used to indicate the number of times that the bank has not been refreshed within the preset refresh duration; the target bank to be refreshed is determined in the at least one candidate bank.

Through the above method, at least one candidate bank whose number of under-refreshing times reaches the first threshold is preferentially refreshed, so as to ensure the refresh effect of the memory.

In a possible implementation manner, before determining the target bank to be refreshed in the at least one candidate bank, the method further includes: determining that the storage area satisfies a refresh condition; the refresh condition includes at least one of the following: the at least one The under-refresh count of one bank reaches the first threshold; the at least one bank is in an idle state; the at least one bank satisfies the forced refresh condition.

Through the above method, the controller can be made to select the target bank more flexibly, when the under-refresh count of the at least one bank reaches the first threshold; the at least one bank is in an idle state; the at least one bank satisfies the forced refresh condition When at least one of the items is selected, the target bank to be refreshed is determined, so that the memory can minimize the influence of the refreshed bank on the normal reading and writing of the bank.

In a possible implementation manner, the generating refresh indication information according to the at least one target bank to be refreshed includes: when it is determined that there is a target bank set that satisfies the full bank refresh mode, generating the target bank set Refresh instruction information, the refresh instruction information is used to indicate that the refresh mode of the target bank set is the full bank refresh mode, and the target bank to be refreshed in the target bank set is the target bank in the at least one target bank to be refreshed. one or more.

Through the above method, when there is a target bank set that satisfies the full-bank refresh mode, the target bank to be refreshed in the target bank set can be refreshed by using the full-bank refresh mode, avoiding that in the single-bank refresh mode, it is necessary to refresh the transmission for each bank. The refresh command of the corresponding bank greatly reduces the sending of the refresh command and the time delay caused by receiving the refresh command, and reduces the refresh time occupied by the refresh of the entire memory.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.

Through the above method, the refresh command of the corresponding bank is instructed through the single bank refresh mode or the same bank refresh mode, so that the target bank to be refreshed can be flexibly instructed.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the method further includes:

When it is determined that there is no target bank set satisfying the all-bank refresh mode in the at least one target bank to be refreshed, it is determined that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the method further includes: in the When at least one target bank to be refreshed includes N target banks to be refreshed in addition to the target bank set, it is determined that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode model.

Through the above method, combined with the full bank refresh mode, when there is no target bank set that satisfies the full bank refresh mode in the at least one target bank to be refreshed, the single bank refresh mode or the same bank refresh mode is used to realize the memory-to-idle refresh mode. The target bank in the state is refreshed, which improves the flexibility of refreshing the memory bank.

In the second aspect, an embodiment of the present application provides a controller. For the technical effect of the corresponding solution in the second aspect, reference can be made to the technical effect obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail. Exemplarily, the controller provided by the embodiment of the present application mainly includes a processing circuit and an interface circuit, wherein: the processing circuit is configured to determine at least one bank to be refreshed according to the idle state of at least one bank in the storage area of the memory. a target bank; generate refresh indication information according to the at least one target bank to be refreshed; the interface circuit is configured to send the refresh indication information to the memory, where the refresh indication information is used to control the memory to refresh all Describe at least one target bank to be refreshed.

In a possible implementation manner, the processing circuit is specifically configured to: determine, in at least one bank in an idle state, at least one candidate bank whose number of under-refreshes reaches a first threshold, wherein the number of under-refreshes is used to indicate The number of times that the bank has not been refreshed within a preset refresh duration; the target bank to be refreshed is determined in the at least one candidate bank.

In a possible implementation manner, the processing circuit is specifically configured to: before determining the target bank to be refreshed in the at least one candidate bank, determine that the storage area satisfies a refresh condition; the refresh condition includes at least the following: Item 1: the number of under-refreshes of the at least one bank reaches a first threshold; the at least one bank is in an idle state; the at least one bank satisfies the forced refresh condition.

In a possible implementation manner, when generating the refresh indication information according to the at least one target bank to be refreshed, the processing circuit is specifically configured to: when it is determined that there is a target bank set that satisfies the full bank refresh mode, generate Refresh indication information of the target bank set, where the refresh indication information is used to indicate that the refresh mode of the target bank set is the full bank refresh mode, and the target bank to be refreshed in the target bank set is the at least one to-be-refreshed target bank. One or more of the target banks to refresh.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the processing circuit is further configured to: When it is determined that there is no target bank set satisfying the all-bank refresh mode in the at least one target bank to be refreshed, it is determined that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the processing circuit is further configured to: after determining In the at least one target bank to be refreshed, when there are N target banks to be refreshed except the target bank set, it is determined that the refresh mode of the N target banks to be refreshed is a single bank refresh mode or the same bank refresh mode.

In the third aspect, an embodiment of the present application provides a memory. For the technical effect of the corresponding solution in the third aspect, reference may be made to the technical effect obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail. Exemplarily, the memory provided by the embodiments of the present application may include: a control circuit, a refresh circuit, and a storage area, wherein: the storage area includes at least one bank bank; the refresh circuit is configured to refresh the at least one bank; The control circuit is configured to receive refresh indication information sent by the controller, where the refresh indication information is used to indicate at least one target bank to be refreshed in the storage area; the at least one target bank to be refreshed is based on the memory The idle state of at least one bank in the storage area is determined; and according to the refresh indication information, the refresh circuit is controlled to refresh the at least one target bank to be refreshed.

In a possible implementation manner, the refresh circuit is at least one; the control circuit is specifically configured to respectively control the at least one refresh circuit to refresh at least one target bank to be refreshed respectively.

In a possible implementation manner, the refresh indication information is used to indicate that the refresh mode of the target bank to be refreshed in the target bank set is the full bank refresh mode; the target bank to be refreshed in the target bank set is the One or more items in at least one target bank to be refreshed; the control circuit is specifically configured to, according to the refresh indication information, control the refresh circuit corresponding to the target bank set to refresh the target bank through a full bank refresh mode The target bank in the collection to be refreshed.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode;

The control circuit is specifically configured to refresh the at least one target bank to be refreshed by controlling the refresh circuit corresponding to the at least one target bank to be refreshed through the single bank refresh mode or the same bank refresh mode according to the refresh instruction information.

In a possible implementation manner, the control circuit is further configured to: when it is determined that in the at least one target bank to be refreshed, there is no target bank set satisfying the full bank refresh mode, determine the at least one target bank to be refreshed The refresh mode of the target bank to be refreshed is the single-bank refresh mode or the same-bank refresh mode.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the N target banks to be refreshed In determining the at least one target bank to be refreshed, the target banks to be refreshed other than the target bank set;

The control circuit is further configured to control the refresh circuit corresponding to the at least one target bank to be refreshed to the N target banks to be refreshed through a single bank refresh mode or a same bank refresh mode according to the refresh instruction information. refresh.

In the fourth aspect, an embodiment of the present application provides a storage system. For the technical effect of the corresponding solution in the fifth aspect, reference can be made to the technical effect obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail. Exemplarily, the storage system provided by the embodiment of the present application includes a controller and a memory, wherein the controller may determine at least one target bank to be refreshed according to the idle state of at least one bank in the storage area; according to the For at least one target bank to be refreshed, refresh indication information is generated and sent to the memory; the refresh indication information is used to control the memory to refresh the at least one target bank to be refreshed. The memory can thus refresh the at least one target bank according to the refresh instruction information.

These and other aspects of the present application will be more clearly understood in the description of the following embodiments.

Description of drawings

FIG. 1a is a schematic structural diagram of a storage system to which an embodiment of the present application is applicable;

Fig. 1b-Fig. 1c are timing diagrams of a refresh method of a memory;

2 is a schematic flowchart of a method for refreshing a memory according to an embodiment of the present application;

3a is a schematic time sequence diagram of a method for refreshing a memory according to an embodiment of the present application;

3b is a schematic timing diagram of a method for refreshing a memory according to an embodiment of the present application;

3c is a schematic timing diagram of a method for refreshing a memory according to an embodiment of the present application;

3d is a schematic time sequence diagram of a method for refreshing a memory according to an embodiment of the present application;

4 is a schematic flowchart of a method for refreshing a memory according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a controller according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a memory according to an embodiment of the present application.

Detailed ways

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

The concepts involved in the embodiments of the present application are explained below first.

The refresh operation can include: automatic refresh (Auto Refresh) and self-refresh (Self Refresh). Among them, self-refresh is a way for DDR to automatically refresh and maintain data in a low power consumption state in a sleep mode. The automatic refresh is the way to complete the refresh and keep the data through the dynamic controller (Dynamic Memory Controller, DMC) control.

The controller is used in the computer system to control the data transmission between the CPU and the memory, and the data can be exchanged between the memory and the CPU through the controller. The controller can be used to process the instructions issued by the CPU; it can also be used to process the data read or written by the CPU in the memory; it can also be used to refresh the memory according to the refresh command. It should be noted that, in this embodiment of the present application, the controller may be integrated in the CPU, or may be a separate chip independent of the CPU. Integrating the controller into the CPU can make the path from the CPU to the memory shorter and reduce the data transmission delay between the CPU and the memory.

A channel can be understood as a controller and the memory space corresponding to the controller. If a computer system contains multiple channels, these channels are usually identical and independent. Commonly referred to as dual-channel memory, it can mean that the CPU has two completely independent controllers. For example, the data bit width of the controller can be 32bit or 64bit.

DIMM is commonly known as DIMM memory stick. The motherboard of the computer system is provided with DIMM slots, each DIMM slot can be inserted with a DIMM memory module, and one channel (channel) can correspond to one or more DIMM slots. DIMMs are implemented by attaching multiple identical memory particles to the same printed circuit board (PCB).

Memory particles (chips) are the basic units that make up DIMMs. The bit width of a single memory granule can be 4bit, 8bit or 16bit, and multiple memory granules are connected in parallel to form a 32bit or 64bit bit width to meet the bit width requirements of the controller.

A library (RANK) refers to a group of memory particles, which are parallelized so that the data bit width meets the bit width requirement of the controller. RANK is also called physical array bank (physical bank, P-bank). As mentioned above, the data bit width of the controller is generally 32bit or 64bit, and the bit width of a single memory particle can be 4bit, 8bit or 16bit. Therefore, multiple memory particles need to be paralleled to form a 32bit or 64bit bit width. Meet the bit width requirements of the controller. For example, if the data bit width of the controller is 64 bits, and the bit width of the memory particles is 8 bits, then 8 memory particles form a RANK; similarly, if the data bit width of the controller is 64 bits, and the bit width of the memory particles is 16 bits, then 4 Memory particles form a RANK. Usually, a DIMM can contain 1 to 4 RANKs.

Bank Group, which can be formed by forming multiple banks into a group, and each bank Group can independently read and write data. For example, the DDR4 architecture uses 8n prefetched bank groups, and the memory can include two or four selectable bank groups, so that each bank group of DDR4 memory has independent activation, reading, and writing. Enter and refresh operations. If the memory includes two independent bank groups, which is equivalent to 16-bit data per operation, the prefetch value can be increased to 16n; if the memory includes four independent bank groups, the prefetch value can be increased to 32n.

In actual implementation, different RANKs are connected to different chip select (CS) signal output pins on the controller, that is, the controller enables different RANKs through different CS signals. For example, a controller corresponds to 4 DIMMs, and each DIMM contains 2 RANKs, then the controller outputs 8 CS signals, each CS signal is used to enable a RANK; for another example, a controller corresponds to 4 DIMMs, Each DIMM contains 4 RANKs, then, the controller outputs 16 CS signals, each CS signal is used to enable one RANK.

It should be noted that when the memory space corresponding to a controller contains multiple RANKs, the multiple RANKs share the same set of command lines and the same set of address lines, and the refresh operation of each RANK is performed independently, that is, in the same time period. Inside, the controller enables only one CS signal among the multiple CS signals to refresh the RANK enabled by the CS signal.

In the description of this application, "at least one" refers to one or more, wherein a plurality of refers to two or more. In view of this, in the embodiment of the present invention, "a plurality" may also be understood as "at least two". "And/or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone. In addition, the character "/", unless otherwise specified, generally indicates that the related objects are an "or" relationship. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing the description, and should not be understood as indicating or implying relative importance, nor should it be understood as indicating or implied order.

FIG. 1a exemplarily shows a schematic structural diagram of a storage system to which this embodiment of the present application is applicable. The storage system 100 may be an electronic device or an integrated chip with a data storage function. For example, the storage system 100 may be an electronic device such as a mobile phone, a computer, and a smart camera, or a system on chip (SOC), a central processing unit, or a (central processing unit, CPU) and other chips, which are not limited in this embodiment of the present application.

As shown in FIG. 1 a , the storage system 100 includes a memory 101 and a controller 102 . The controller 102 may include a processing circuit 1021 and an interface circuit 1022 . Exemplarily, the processing circuit 1021 may be a logic operation circuit, and the processing circuit 1021 may generate instructions. The interface circuit 1022 may be a control bus interface, and the controller 102 may be connected to the memory 101 through a control bus through the interface circuit 1022 . The interface circuit 1022 can send an instruction to the control circuit 1011 of the memory 101, so as to instruct the control circuit 1011 to complete tasks such as data reading, storage, and refresh.

In general, the memory 101 may include a control circuit 1011, one or more refresh circuits (eg, refresh circuit 1, refresh circuit 2, . . . refresh circuit N), and a storage area 1012, where N is an integer greater than or equal to 1. The number of refresh circuits that the memory 101 may include is not limited in this embodiment of the present application.

The storage area 1012 may be a two-dimensional storage array composed of a plurality of storage cells. Each storage unit can store 1 bit of data. In this embodiment of the present application, the memory 101 may be a capacitive memory, for example, the memory 101 may be a DRAM. In this case, each storage unit corresponds to at least one capacitor, and each storage unit can realize data storage through the charge stored in the capacitor. For example, for any storage unit, if the capacitor of the storage unit stores charge, the data stored in the storage unit is 1, and if the capacitor of the storage unit does not store charge, the data stored in the storage unit is 0 .

Since the electric charge in the capacitor will be continuously lost along with the leakage, the controller 102 needs to refresh the memory 101 periodically. Specifically, the controller 102 may send a refresh command to the control circuit 1011. Currently, the refresh command is mostly an auto-refresh command, or an active command and a pre-charge command. Among them, the auto-refresh instruction may also be referred to as the refresh instruction.

Taking the refresh instruction as an example, the controller 102 may send the refresh instruction to the memory 101 . After receiving the refresh instruction, the control circuit 1011 will determine the target bank to be refreshed next according to the refresh logic preset in the control circuit 1011 . For example, the control circuit 1011 is internally provided with a refresh counter, which is used to automatically and sequentially generate the row addresses of the target banks to be refreshed. The control circuit 1011 can then complete the refresh of the target bank through the refresh circuit in the memory 101 .

Generally speaking, as shown in FIG. 1a, the storage area 1012 can be further divided into a plurality of banks. Each bank can be an m×n two-dimensional storage array, where m is the row number of the two-dimensional storage array, m is a positive integer greater than 1, n is the column number of the two-dimensional storage array, and n is a positive integer greater than 1 . It can be understood that different banks may have the same or different numbers of rows and columns, which are not limited in this embodiment of the present application.

The multiple refresh circuits in the memory 101 can respectively perform refresh operations on one or more banks. Exemplarily, as shown in FIG. 1a , the N refresh circuits in the memory 101 may refresh the N banks in the storage area 1012 respectively, that is, the N refresh circuits may correspond to the N banks one-to-one, such as refresh circuits. 1 corresponds to bank1, then refresh circuit 1 can refresh bank1. Next, the description will be given by taking the one-to-one correspondence between N refresh circuits and N banks. It should be understood that when there is a one-to-many correspondence between multiple refresh circuits and multiple banks, that is, one refresh circuit can When multiple banks are refreshed, the solutions provided by the embodiments of the present application can also be applied.

After determining the target bank, the control circuit 1011 may send instruction information to the refresh circuits 1 to N to instruct the refresh circuits 1 to N to refresh the banks 1 to N respectively. Specifically, the refresh circuit 1 can refresh bank1 after receiving the indication information, the refresh circuit 2 can refresh bank2 after receiving the indication information, and so on.

As mentioned earlier, the refresh module included in the controller can refresh the memory. When the memory space corresponding to a controller contains a bank (that is, a channel corresponds to a bank), the refresh operation of each channel in the computer system is performed independently; when the memory space corresponding to a controller contains When there are multiple banks, the refresh operation of each bank is performed independently. Taking a memory space corresponding to a controller including a bank as an example, the timing sequence of the refresh operation of each channel (channel) can be shown in Figure 1b.

At the beginning of the refresh, that is, during the automatic refresh process for all memory banks in the selected bank, the memory space corresponding to the channel (the selected bank) must be in an idle state, that is, there is no data transmission in the memory space corresponding to the channel. Through the row address refresh period and the memory refresh time interval, the characteristic information of the refresh can be represented. Among them, the row address refresh cycle (DRAM row refresh cycle time, tRFC) represents the duration of a refresh. That is, after the refresh command is generated, during the time period of tRFC, the controller refreshes the memory space corresponding to the channel, and the memory space corresponding to the channel must be in an idle state at this time.

The memory refresh interval (DRAM refresh interval, tREFI) represents the average interval between refresh operations. That is to say, for two adjacent refresh operations, the interval between the two (that is, the difference between the time when the second refresh operation is started and the time when the first refresh operation is started) can be less than tREFI, or Can be greater than tFEFI. As long as there are multiple refreshes, the average interval between refresh operations is tFEFI. Specifically, as shown in FIG. 1b, after a refresh is completed, the next refresh can be started immediately (ie, the interval duration of the refresh operation is tRFC); after the start of a refresh, the next refresh can also be performed after an interval of 9tREFI.

The memory uses the charge in the capacitor to store data. Since the charge will be continuously lost with the existence of leakage, it needs to be refreshed before the charge is lost to avoid data loss. If the interval between refresh operations is too long, data loss will occur. Therefore, the maximum interval duration of refresh operations specified in the protocol is 9tREFI.

In order to ensure that the average interval of refresh operations is tREFI, one of the simplest implementation methods is to perform a refresh at time T0 with an interval of tREFI, and then perform the next refresh at T0+tREFI, with an interval of tREFI, and then at T0+ 2tREFI time for the next refresh... and so on. That is, the refresh operation is performed periodically, and the period in which the refresh operation is performed is tREFI. However, in the specific implementation process, if the memory space corresponding to the channel is in the process of data transmission within the time period tRFC used for the refresh operation in a certain period, then according to the above mechanism, the memory space needs to stop data transmission and transfer. It is in an idle state, and data transmission is resumed after the refresh is completed. This approach will undoubtedly reduce the efficiency of memory access.

It should be pointed out that, in the current refresh operation, assuming that each bank includes 8192 rows of storage units, the controller 102 needs to send 32 refresh commands (each refresh command refreshes 256 rows) before the memory 101 can be refreshed. Each memory cell is refreshed once. Although currently the controller 102 can instruct the memory 101 to complete the refresh through the refresh instruction, this control method is relatively limited and cannot flexibly adapt to different application scenarios of the memory 101 .

Therefore, in order to make the refresh mechanism more flexible and improve the efficiency of memory access, a refresh postponing mechanism and a pull-in mechanism are introduced. The postponing mechanism is to delay the refresh time. For example, in the above example, if a channel is undergoing data transmission, then it is not necessary to refresh at this time, but to wait until the data transmission is completed before refreshing, so as to avoid the refresh operation affecting memory access. s efficiency. Similarly, the pulling-in mechanism is refreshed in advance. For example, when a channel is idle, it can be refreshed in advance even if the time since the last refresh is less than tFEFI.

The following is a brief description of the postponing mechanism as an example. As shown in Figure 1b, it is a timing diagram of the postponing mechanism. In Figure 1b, the interval of refresh operations is 9tREFI. Since the refresh mechanism needs to ensure that the average interval of refresh operations is tREFI, when the interval is 9tREFI, it can be considered that the channel is under-refreshed, and the number of under-refreshes of this channel is Can be 8 times. Then, in the process of subsequent refresh operations, 8 refresh operations may be performed continuously, so that the average interval duration of the refresh operations is tREFI.

Of course, the postponing mechanism shown in Figure 1b is an extreme case. In actual implementation, the interval of refresh operations can be any time between tRFC and 9tREFI. When the number of under-refreshes caused by the previous postponing is compensated, the refresh operation can be continuously refreshed. Multiple times, or multiple times to make up for the number of insufficient refreshes.

Although the postponing mechanism and the early (pulling-in) mechanism can reduce the impact of the refresh operation in this channel on the memory access efficiency to a certain extent, the postponing (postponing) mechanism and the early (pulling-in) mechanism only For the operation of this channel, it is difficult to realize the overall planning of multiple channels.

It is difficult to take into account the memory access requirements of multiple channels by using the above-mentioned postponing mechanism and pulling-in mechanism. If any channel in the system is in the refresh state, the access to the memory address may be temporarily interrupted. Therefore, in the refresh processing solution in the prior art, since the refresh operations of multiple channels are performed independently, the probability of system interruption is high, which affects the efficiency of memory access.

With higher requirements for capacity, power consumption and speed, the DDR protocol has developed from DDR3/LPDDR3 to DDR4/LPDDR4, and has been upgraded to DDR5/LPDDR5 and other protocol versions. With the larger capacity of the memory particles, the more frequent refresh is required, the smaller the tREFI value, and the longer the execution time tRFC to complete a refresh. Therefore, the impact of automatic refresh on DDR performance is becoming more and more significant, and the timing of automatic refresh and the optimization of refresh banks have also become important considerations for improving DDR performance. In some embodiments, automatic refresh can also be divided into multiple modes, for example, all bank refresh mode (All bank auto-refresh, REFab), single bank refresh mode (Per bank auto-refresh, REFpb) and same bank refresh mode ( same bank auto-refresh, REFsb).

Among them, the whole bank refresh mode may be a centralized refresh of the whole bank through a fixed cycle. As shown in Figure 1c, that is, counting the refresh time (tREFI), when the refresh time is determined to arrive, a refresh command for the whole bank refresh is issued. After the control circuit receives the refresh command, it executes all banks in sequence according to the bank order. refresh. In this method, all banks will be closed each time the refresh is performed, and the read and write commands of the memory are easily interrupted. At this time, the DMC will not be able to schedule the read and write commands of different banks. Optionally, it can also be combined with the postpone function to avoid interrupting the normal read and write operations of the DDR by delaying the number of refreshes when there are read and write commands in the bank, and maintain the currently postponed refresh times through the counter. The refresh compensation is performed in the next set. However, due to the long operation time of the full bank refresh mode, it has a great impact on the DDR bandwidth, and also increases the waiting time of the read and write commands in the DMC, which increases the overall read and write delay of the DDR.

The single-bank refresh mode refers to the refresh at a fixed interval of tREFI specified by the protocol, and the bank sequence selection for refresh is traversed in a fixed order to complete a round of refresh operations. When it is determined that the refresh time arrives, according to the sequence of the banks, a refresh command for corresponding bank refresh is issued once, and the control circuit executes the bank refresh after receiving the refresh command for the bank refresh. In the single-bank refresh mode, its tRFC is small, and when the bank is refreshed, the normal reading and writing of other banks can not be affected.

The same bank refresh mode is based on the bank group mode, at a fixed interval of tREFI specified by the protocol, and refreshes one bank in each group at the same time, and the refreshed bank sequence selection is traversed in a fixed order to complete a round of refresh operations.

In the single-bank refresh mode and the same-bank refresh mode, although only a single bank or a single bank in multiple groups is closed at a time, the number of refreshes required is also multiplied. That is, when each bank is refreshed, a corresponding refresh command needs to be issued, and a corresponding control circuit is activated, and after the corresponding bank refresh is executed, the refresh state is terminated. Especially when using DDR chips with a large number of banks (for example, as shown in Figure 1c, the number of banks is 8), the refresh times in the single bank refresh mode and the same bank refresh mode are the refresh times in the full bank refresh mode. 8 times. The overall read and write latency of DDR is still relatively large.

In addition, because REFpb or REFsb selects the bank traversal method in a fixed order, it is easy to cause the bank that is currently executing the read and write command to need to be refreshed, thus interrupting the read and write operation and affecting the performance. At the same time, if there are other idle banks to be refreshed, it may not be able to make full use of the idle time to refresh because the previous bank has not been refreshed. At this time, combined with the postpone function, it is easy to cause a large number of delays, which makes it difficult to schedule the bank when the number of delays is reissued in a centralized manner. Therefore, the normal read and write operations of the DDR have to be interrupted, reducing the DDR bandwidth and read and write performance.

In view of this, embodiments of the present application provide a controller, a memory, and a refresh method. In this embodiment of the present application, the controller 102 may indicate to the memory 101 at least one target bank to be refreshed through the refresh indication information. Therefore, the controller 102 may control the refresh operation of the memory 101 more flexibly. It can be understood that, compared with the control circuit 1011 , the controller 102 has stronger logical judgment capability and can cope with more complex application scenarios. Compared with the current solution, the control circuit 1011 automatically determines the next row that needs to be refreshed. In this embodiment of the present application, the controller 102 directly indicates at least one bank to be refreshed, which is beneficial to make the refresh operation flexibly adapt to different application scenarios. Reduce the impact of reading and writing on storage space.

FIG. 2 exemplarily shows a schematic flowchart of a refresh method provided by an embodiment of the present application. As shown in FIG. 2 , the method mainly includes the following steps:

S201: The controller 102 determines at least one target bank to be refreshed according to the idle state of at least one bank in the storage area.

Wherein, the storage area of the memory includes at least one bank. Specifically, at least one target bank to be refreshed can be determined by the processing circuit 1021 in the controller 102 .

The controller 102 can flexibly determine the target bank to be refreshed according to the current application scenario. For example, the idle state of at least one bank in the storage area can be determined according to factors such as the access situation of the memory and the storage situation of the memory. The bank and the bank to be refreshed determine the target bank to be refreshed. The controller 102 detects the idle idle state of the bank by optimizing the bank sequence selection mechanism of REFpb, and preferentially selects an idle bank that meets the refresh conditions for refresh, thereby preventing the currently idle bank from being unable to use the idle time period to send refresh due to the fixed order. The impact of reading and writing on storage space.

It should be noted that under 8 banks in LPDDR5, the state of the paired bank should also be considered for the determination of the bank in the idle state. Only when all the banks in the paired bank are idle can it be determined that the bank in the paired bank is in an idle state.

In some embodiments, the controller 102 can maintain the refresh status of each bank through a one-hot code. When the refresh is completed, the refresh status of the bank can be marked as 1, and when the refresh is not completed, the refresh status of the bank can be marked. marked as 0. Therefore, after a full bank refresh is completed, the refresh status of all banks is marked as zero.

Taking LPDDR4 as an example, the storage area includes 8 banks, the particle capacity is 1GB, and the refresh rate is 0.5X. Its tREFI is 1.952us. According to the provisions of the DDR protocol auto-refresh, in the ideal case that the refresh operation is not interrupted by the read and write operations in the REFpb mode, the refresh time is shown in Figure 3a, and 8 single bank refreshes need to be completed within the tREFI interval. Therefore, the refresh interval of a single bank can be 1.952/8us. In the prior art, the REFpb refresh command is refreshed according to the bank sequence. For example, in the refresh command queue shown in Figure 3a, the refresh command bank0->bank1->bank2...->bank7 of REFpb is sent in the following order. Eight refreshes of REFbp are one cycle. During this process, there may be current The bank that needs to be refreshed (for example, bank2) is the same bank as the bank that needs to execute read and write commands. As a result, the controller can only schedule read and write commands of other banks except bank2. Commands are suspended, resulting in reduced read and write performance.

Example 1, the controller may determine the target bank to be refreshed according to the currently idle bank and the bank to be refreshed.

Assume that within the refresh time interval of a single bank in tREFI, banks1 to bank8 are occupied by the read and write of bank1 to bank3, that is, the currently idle banks are bank4 to bank8, and the banks to be refreshed include: bank4 to bank7. The controller can Select a bank from bank4 to bank7, for example, bank4, and perform a single-bank refresh. After performing a refresh of a single bank, the bank (eg, bank4) may be marked as refreshed. In the refresh time interval of the next single bank, the target bank to be refreshed can be determined according to the currently idle bank and the bank to be refreshed. For example, bank1 to bank8 are occupied by the read and write of bank4 to bank6. Therefore, the target bank to be refreshed can be determined according to the currently idle banks (bank1 to bank3, bank7 to bank8) and the bank to be refreshed (bank5 to bank7). for bank7.

In the bank-based idle state refresh command queue shown in Figure 3a, within each single bank refresh time interval within a tREFI cycle, the target bank to be refreshed is determined according to the idle bank and the bank to be refreshed. Therefore, the determined refresh sequence of banks is: bank2→bank5→bank6→bank0→bank3→bank7→bank1→bank4.

The following uses a specific example to illustrate the efficiency of determining the target bank to be refreshed by using a bank in an idle state.

Consider that the maximum time from the last refresh of all banks to the next refresh of all banks can be that the memory is within the time interval of 9*tREFI, and the read and write services are not interrupted, causing the memory to trigger a forced refresh, that is, the centralized reissue of all delayed REFpb refreshes The time required for the operation. In this scenario, the maximum time interval for refreshing all banks can be determined. As shown in Figure 3b. Therefore, the maximum time T_total from the moment when all banks were last completely refreshed to the moment when the forced refresh was completed satisfies:

T_total=9*tREFI+(8*bank_NUM-1)*tRFCpb=9*1952+(8*8-1)*90=23238ns

Among them, 9*tREFI represents the time required to trigger the forced refresh, and bank_NUM represents the number of banks in the storage area, where bank_NUM is 8. tRFCpb indicates the minimum delay required to refresh any other BNAK or activate itself after executing a refresh command for a bank. For example, TRFCpb may be a delay for performing a refresh operation of the next bank (for example, a refresh bank1 command) after bank0 is refreshed. For another example, TRFCpb may be a delay for the next bank activation operation (activation bank1 command) after bank1 is refreshed. Therefore, (8*bank_NUM-1)*tRFCpb represents the time required to refresh all banks in the single-bank mode. Among them, the controller sends (8*bank_NUM) single bank refresh commands.

Therefore, the time from the last refresh of all banks to the next refresh of all banks may be less than or equal to the maximum time T_total.

Considering that within the maximum time, the method of the present application can avoid that the read and write commands are interrupted by the refresh command, resulting in a delay in reading and writing. Therefore, the effective time for the memory to execute the read and write commands only needs to consider the read and write commands that send PREpb. and REFpb refresh commands take bus time. Therefore, within the maximum time T_total, the effective time T_val for the execution of read and write commands can be executed to satisfy:

T_val=9*tREFI+[(8*bank_NUM-1)*tRFCpb-(8*bank_NUM)*Tcmd_cost]*efficiency coefficient=9*1952+(63*90-63*4)*efficiency coefficient

Among them, Tcmd_cost is the bus time required to send the PREpb and REFpb commands once.

In LPDDR4, the number of channels is 4, so Tcmd_cost can be expressed as 4nCLK. The efficiency coefficient is introduced by considering the bank command scheduling efficiency in the actual scenario and additional overheads such as bank handshake. In some embodiments, the efficiency coefficient may be between 0.5 and 0.7.

Therefore, within the maximum time T_total of the refresh interval, the execution efficiency of the memory read and write commands satisfies:

Eff=T_val/T_total

When the efficiency coefficient is in the range of 0.5-0.7, the execution efficiency Eff of read and write commands within T_total is 87.25%-91.92%.

In this maximum time scenario, the impact of REFpb on the execution efficiency of read and write commands is about 8%.

Determine the efficiency of the target bank to be refreshed for the bank that represents the use of the idle state, instead of refreshing the banks in sequence.

At this time, assuming that the bank is refreshed in sequence, there is a 20% chance that the REFpb refresh will just make it impossible to schedule effective read and write commands. By the method in this application, the execution efficiency of the read and write commands can be effectively improved by 8%*20% = 1.6%. In the simulation of other scenarios, for example, based on the real read and write path, the execution efficiency of the read and write commands can be effectively improved by 1% to 2% through the method in the present application.

In example 2, the controller may also determine the target bank to be refreshed according to the currently idle bank and the bank to be refreshed in combination with the method of deferring refresh.

For example, in the normal business traffic scenario, the read and write operations of the business may cause the delay and reissue of the refresh operation.

In this application, the counter pstpnd_cnt can be used to count the under-refresh times of the bank, and the under-refresh times can be maintained by the under-refresh times of a single bank, that is, as long as the automatic refresh of one bank is delayed, the count of the counter pstpnd_cnt will be added to the count. 1. When the automatic refresh of a bank is completed, the counter is decremented by 1 accordingly. Correspondingly, when an automatic refresh of all banks is completed, the counter decreases the number of all banks accordingly. In the scenario where there are multiple bank groups, the same bank in different bank groups may be refreshed at the same time. At this time, the banks in each group can be marked according to different groups, and when a bank in a group is refreshed , the count of the counter pstpnd_cnt is decremented by 1, and when one bank in the K groups completes the refresh at the same time, the count of the counter pstpnd_cnt is decremented by K.

The under-refresh count of the target bank is used to indicate the number of times the target bank has not been refreshed within the preset refresh time. As shown in the refresh operation timing sequence of Fig. 1c, the average interval duration of refresh operations is tREFI. When the duration from the last refresh operation is equal to tREFI, if a target bank is performing data transmission, the target bank may not be refreshed first. Since the refresh mechanism needs to ensure that the average interval of refresh operations is tREFI, in this case, the target bank can be said to be under-refreshed. Specifically, the longer the interval from the last refresh operation, the more under-refresh times of the target bank.

Exemplarily, assuming that a target bank completes a refresh operation at time T0, during the time period from T0 to T0+2tREFI, since the target bank has been performing data transmission, there is no such target at the time of T0+2tREFI. The bank is refreshed, and the number of under-refreshes of the memory space is 2 at this time. Suppose a target bank completes a refresh operation at time T0, during the time period of T0~T0+5tREFI, because the target bank has been processing data Therefore, the target bank is not refreshed at the time of T0+5tREFI, and the number of under-refreshes of the target bank at this time is 5 times.

Wherein, the condition for forcibly refreshing the target bank may be: the number of under-refreshing times of the target bank is greater than or equal to the first threshold. That is, when the number of under-refreshes of the target bank is greater than or equal to the first threshold, the controller determines to forcibly refresh the target bank. The maximum interval between refresh operations is 9tREFI. When the interval between refresh operations is too long (ie, there are many under-refresh times, such as 7 or 8 times), the risk of data loss increases. Therefore, when the number of under-refreshing times of the first memory space is greater than or equal to the first threshold, the first memory space can be forcibly refreshed, thereby avoiding the occurrence of data loss. Illustratively, the first threshold may be 7 or 8.

Therefore, in this scenario, after it is determined that the bank in the storage area satisfies the refresh condition, the bank that satisfies the refresh condition may be determined as the target bank to be refreshed. The refresh conditions may include at least one of the following: the number of under-refreshes of the at least one bank reaches a first threshold, the at least one bank is in an idle state, and the at least one bank satisfies a forced refresh condition.

In some embodiments, the controller may determine at least one candidate bank whose number of under-refreshes reaches the first threshold in at least one bank in an idle state, and determine a target bank to be refreshed in the at least one candidate bank.

For example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined banks to be refreshed include bank1, bank2, bank3 and bank4. At this point, it can be determined that the candidate banks include: bank1, bank2, bank3 and bank4. And the number of under-refresh of bank1 is 5, the number of under-refresh of bank2 is 6, the number of under-refresh of bank3 is 2 and the number of under-refresh of bank4 is 3. The number of under-refreshes of the storage area is represented by the counter pstpnd_cnt.

Taking the first threshold value as 6 as an example, consider that the currently idle banks include: bank1 and bank2. In an idle bank, the under-refresh count of bank1 is less than the first threshold, and the under-refresh count of bank2 is greater than the first threshold. Therefore, the current target bank to be refreshed can be determined as bank2. After the refresh of bank2 is completed, the number of under-refreshes of bank2 may be updated to 5.

Consider the scenario where there is a bank group. At this time, for each group in multiple groups, the target bank to be refreshed can be determined according to the bank in the idle state and the bank whose number of under-refreshes reaches the first threshold.

For another example, the storage area includes 2 bank groups, and the number of banks in each bank group is 4. For example, bank group1 includes: group1-bank1, group1-bank2, group1-bank3, and group1-bank4. The currently determined banks of group1 to be refreshed include group1-bank1, group1-bank2, group1-bank3 and group1-bank4. The under-refresh count of group1-bank1 is 5, the under-refresh count of group1-bank2 is 6, the under-refresh count of group1-bank3 is 7, and the under-refresh count of group1-bank4 is 8. bank group2 includes: group2-bank1, group2-bank2, group2-bank3 and group2-bank4. The currently determined banks to be refreshed by group2 include group2-bank1, group2-bank2, group2-bank3, and group2-bank4. And the under-refresh count of group2-bank1 is 3, the under-refresh count of group2-bank2 is 4, the under-refresh count of group2-bank3 is 7, and the under-refresh count of group2-bank4 is 8.

Taking the first threshold value as 6 as an example, the target banks to be refreshed currently may be determined as group1-bank2, group2-bank3 and group2-bank4. Optionally, the priority of target banks may also be sorted according to the number of under-refreshes. For example, at this time, you can set the priority of group2-bank4 to be the highest, the priority of group2-bank3 to be medium, and the priority of group1-bank2 to be the lowest. Therefore, the bank with a higher number of under-refreshes is preferentially refreshed, thereby improving the refresh efficiency and preventing the loss of stored data.

Through the above method, combined with postpone, the refresh execution timing is optimized instead of performing the refresh operation at a fixed tREFI interval. That is, the currently delayed refresh times are maintained through the counter, and then as long as the processing idle state of the bank is detected, the refresh compensation of the bank is triggered, and the idle time is used to insert the refresh to avoid interrupting the normal read and write operations of the DDR, thereby improving the performance of the DDR. .

Consider another scenario. In the single bank refresh mode, the REFpb refresh command causes the current bank not to be refreshed due to the read and write commands, and accordingly generates the number of under-refreshes of the bank. In the idle state of the bank, the REFpb delayed by the bank is reissued. refresh command. At this time, it is still assumed that the bank reissues 20% of the REFpb refresh commands in the idle state. For example, N REFpb refresh commands are reissued. Therefore, the controller sends (8*bank_NUM-N) single bank refresh commands during refresh. . As shown in Figure 3c, the maximum refresh interval time:

T_total=9*tREFI+(8*bank_NUM-1)*0.8*tRFCpb

=9*1952+(8*8-1)*0.8*90=22068ns

The effective time T_val for the execution of read and write commands within T_total is:

T_val=9*tREFI+[(8*bank_NUM-1)*tRFCpb-(8*bank_NUM)*Tcmd_cost]*0.8*efficiency factor=9*1952+(63*90-63*4)*0.8*efficiency factor

When the efficiency coefficient is in the range of 0.5-0.7, the Eff is 89.42%-93.35%, and the efficiency can be improved by 2% compared with the method of sequentially postpond refreshing in the prior art.

S202: The controller 102 generates refresh indication information according to the at least one target bank to be refreshed.

Wherein, in some embodiments, the refresh indication information is used to control the memory to refresh the at least one target bank to be refreshed. Specifically, refresh indication information may be sent to the memory 101 through the interface circuit 1022 in the controller 102, where the refresh indication information may indicate the above at least one target bank to be refreshed.

Considering that the single bank refresh mode needs to send more refresh commands, when there are many banks to be refreshed, it is easy to cause the performance of the memory to decrease. Based on this, in other embodiments, the controller 102 may also determine whether a target bank set exists in the at least one target bank to be refreshed. Wherein, the target bank in the target bank set belongs to the at least one target bank to be refreshed. Executing the full bank refresh mode through the target bank set can effectively reduce the number of refresh commands sent, thereby improving the performance of the memory.

In this embodiment of the present application, there are at least the following three possible implementation manners for refreshing the indication information:

Mode 1: In the at least one target bank to be refreshed, when it is determined that the target bank set satisfies the full bank refresh mode, refresh indication information of the target bank set is generated; the refresh indication information is used to indicate the target bank set The refresh mode is the full bank refresh mode. Optionally, the refresh indication information of the target bank set may also be used to indicate the number of times the refresh command in the full bank refresh mode is executed.

In some embodiments, the target bank set includes all banks in the storage area. Alternatively, the target bank set includes all banks in one or more groups in the storage area.

For example, the number of banks included in the storage area is 4, including: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2, bank3 and bank4. Furthermore, the under-refresh count of bank1 is 1, the under-refresh count of bank 2 is 2, the under-refresh count of bank 3 is 2, and the under-refresh count of bank 4 is 3. The number of under-refreshes of the storage area is represented by the counter pstpnd_cnt.

Therefore, the target bank set can be determined. When it is determined that the target bank set exists, it can be determined that the target bank set can perform at least one full bank refresh mode. In some embodiments, the number of times of performing the full bank refresh mode may be determined according to the minimum value of the under-refresh times of each bank in the target bank set. In combination with the above example, considering that the number of under-refreshes of bank1 is 1, it can be determined that the target bank set can perform a full-bank refresh mode once.

Mode 2: When it is determined that in the at least one target bank to be refreshed, there is no target bank set that satisfies the full bank refresh mode, it is determined that the refresh mode of the at least one target bank to be refreshed is the single-bank refresh mode or the same bank refresh mode refresh mode. That is, the refresh indication information may be used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.

In some embodiments, the determined current target bank to be refreshed includes a part of the bank in the storage area. Alternatively, the target bank set includes a subset of banks in one or more groups in the storage area. Considering that the same bank in different groups can be refreshed at the same time, when the same bank in different groups exists in the target bank set, the target bank set does not need to perform full bank refresh. At this time, the refresh mode of the target bank to be refreshed can be changed. Determine the single bank refresh mode, or the same bank refresh mode.

For example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2 and bank4. In addition, the under-refresh count of bank1 is 1, the under-refresh count of bank 2 is 2, and the under-refresh count of bank 4 is 3.

At this time, the refresh indication information can be used to instruct bank1, bank2 and bank4 to be refreshed in the single bank refresh mode, and the number of times to be refreshed for bank1 is 1, the number of times to be refreshed for bank2 is 2, and the number of times to be refreshed for bank4 is 3. In some embodiments, the refresh indication information may include: 6 refresh commands for single bank refresh. For example, the refresh instruction information includes: 1 refresh command to refresh bank1, 2 refresh commands to refresh bank2, and 3 refresh commands to refresh bank4. Each refresh command is used to instruct the corresponding target bank to be refreshed to perform a refresh.

For another example, the storage area includes 2 bank groups, and the number of banks in each bank group is 4. For example, bank group1 includes: group1-bank1, group1-bank2, group1-bank3, and group1-bank4. The currently determined banks to be refreshed by group1 include group1-bank1 and group1-bank4. And the under-refresh count of group1-bank1 is 1 and the under-refresh count of group1-bank4 is 3. bank group2 includes: group2-bank1, group2-bank2, group2-bank3 and group2-bank4. The currently determined banks to be refreshed by group2 include group2-bank2 and group2-bank4. And the under-refresh count of group2-bank2 is 4 and the under-refresh count of group2-bank4 is 3.

At this time, the refresh indication information may be used to instruct group1-bank1 and group1-bank4, and group2-bank2 and group2-bank4 to be refreshed through the single-bank refresh mode. The under-refresh count of group1-bank1 is 1, the under-refresh count of group1-bank4 is 3, the under-refresh count of group2-bank2 is 4, and the under-refresh count of group2-bank4 is 3. For example, the refresh instruction information includes: 1 refresh command to refresh group1-bank1, 4 refresh commands to refresh group2-bank2, 3 refresh commands to refresh group1-bank4, and 3 refresh commands to refresh group2-bank4.

In some embodiments, the refresh indication information may include: 3 refresh commands for same-bank refresh and 5 refresh commands for single-bank refresh. Among them, the refresh command of the same bank refresh is used to instruct the banks 4 in different groups to perform 3 refreshes. The five refresh commands for single-bank refresh are respectively used to instruct group1-bank1 to refresh once, and to instruct group2-bank2 to refresh 4 times.

Mode 3: In determining the at least one target bank to be refreshed, when N target banks are included in addition to the target bank set mentioned in Mode 1 above, it is determined that the refresh mode of the N target banks is a single bank Refresh mode or same bank refresh mode. That is, the refresh indication information can also be used to indicate that the refresh modes of the N target banks are the single-bank refresh mode or the same-bank refresh mode.

For example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2, bank3 and bank4. Furthermore, the under-refresh count of bank1 is 1, the under-refresh count of bank 2 is 2, the under-refresh count of bank 3 is 2, and the under-refresh count of bank 4 is 3.

At this time, the refresh instruction information may be used to instruct bank1, bank2, bank3 and bank4 to be refreshed once through the full bank refresh mode. In addition, the refresh instruction information can also be used to instruct bank2, bank3 and bank4 to be refreshed in the single bank refresh mode, and the refresh count of bank2 is 1, the refresh count of bank3 is 1, and the refresh count of bank4 is 2. In some embodiments, the refresh indication information may include: 1 refresh command for full bank refresh and 4 refresh commands for single bank refresh. Among them, the refresh commands for 4 single bank refreshes include: refresh commands for bank2, 1 refresh command for bank3, and 2 refresh commands for bank4. Therefore, at least the time occupied by four refresh commands for single-bank refresh and the delay caused by executing the refresh commands are saved.

Based on this, in other embodiments, the controller 102 may determine whether the number of under-refreshes in the storage area exceeds the preset number of refreshed banks, thereby determining a target bank in the target bank set. Wherein, the preset number of refresh banks may be equal to or less than the second threshold. The refresh times of the target banks in the target bank set is equal to the preset number of refresh banks. The refresh times of the target banks in the target bank set may be less than or equal to the total number of banks in the storage area. Therefore, the refresh times of the target banks included in the refresh command corresponding to the full bank refresh mode corresponding to the target bank set may be less than the number of banks in the storage area. total number of .

According to the preset number of refresh banks, the refresh times of the target bank to be refreshed corresponding to the target bank set can be determined, so that a refresh command similar to full bank refresh is issued to the target bank in the target bank set to instruct the execution Refresh times of the corresponding target bank in the target bank set. Compared with the refresh command based on which each bank is refreshed once for a single bank, the number of refresh commands sent can be effectively reduced, thereby improving the performance of the memory.

In this embodiment, the refresh indication information is illustrated in the following manners 4 to 6:

Mode 4: In the at least one target bank to be refreshed, the number of under-refreshes of the storage area exceeds the preset number of refreshed banks, so that a target bank set can be determined, and the target bank set is refreshed in a full bank refresh mode , and generate refresh indication information of the target bank set; the refresh indication information is used to indicate that the refresh mode of the target bank set is the full bank refresh mode.

Optionally, the refresh indication information may also be used to indicate the number of times that the refresh command in the full bank refresh mode of the target bank set is executed.

In some embodiments, the target bank set is determined according to a preset number of refresh banks. The target bank set is used to indicate the target bank and the number of refreshes for each target bank.

For example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2, bank3 and bank4. Furthermore, the under-refresh count of bank1 is 1, the under-refresh count of bank 2 is 2, the under-refresh count of bank 3 is 3, and the under-refresh count of bank 4 is 4. The under-refresh count pstpnd_cnt of the storage area is 10.

The number of times to execute the refresh mode of the entire bank can be determined according to the number of under-refreshes of the storage area and the number M of banks included in the storage area. For example, the number of times of executing the refresh mode of the whole bank may satisfy: Mod(pstpnd_cnt/M)=2.

Therefore, two target bank sets can be determined. Each target bank set can generate a refresh command corresponding to a full bank refresh. For example, the first target bank set may include: bank1, bank2, bank3 and bank4. The second target bank set can include: bank2, bank3, bank3 and bank4.

Therefore, the refresh instruction information may include 2 refresh commands for full bank refresh. Among them, a refresh command of a full bank refresh is used to instruct to refresh the refresh of the target bank in the first target bank set and the corresponding refresh times. The refresh command of one full bank refresh is used to instruct the refresh of the target banks in the second target bank set and the corresponding refresh times.

For another example, the second threshold corresponding to the target bank set may be correspondingly set according to the number M of banks included in the storage area. For example, the second threshold may be set to be smaller than the number M of banks included in the storage area. At this time, the number of times to execute the refresh mode of the whole bank can be determined in the following manner.

When it is determined that Mod(pstpnd_cnt/M) is greater than the second threshold, the number of times of executing the refresh mode of the whole bank satisfies: Mod(pstpnd_cnt/M)+1.

For example, taking the second threshold value of 2 as an example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2, bank3 and bank4. In addition, the under-refresh count of bank1 is 4, the under-refresh count of bank 2 is 5, the under-refresh count of bank 3 is 6, and the under-refresh count of bank 4 is 8. The under-refresh count pstpnd_cnt of the storage area is 23. Therefore, it can be determined that Mod(pstpnd_cnt/M) is 3 after the remainder is greater than the second threshold. Therefore, the number of times of executing the refresh mode of the whole bank can be the quotient of Mod(pstpnd_cnt/M) plus 1, which can be 6.

Thus, 6 target bank sets can be determined. Each target bank set can generate a refresh command corresponding to a full bank refresh. For example, a set of 4 target banks may include: bank1, bank2, bank3 and bank4. The fifth target bank set can include: bank2, bank3, bank3 and bank4. The sixth target bank set may include: bank4, bank4, and bank4.

Optionally, the refresh indication information of the target bank set may include 6 refresh commands in the full bank refresh mode.

When it is determined that the modulo value of Mod(pstpnd_cnt/M) is less than or equal to the second threshold, the number of times of executing the refresh mode of the whole bank satisfies: the mod(pstpnd_cnt/M) value after the quotient.

way five

When it is determined that the number of under-refreshes in the storage area is less than the preset number of refreshed banks, so that it can be determined that there is no target bank set that satisfies the full-bank refresh mode, it is determined that the refresh mode of the at least one target bank to be refreshed is the single-bank refresh mode Or the same as bank refresh mode. That is, the refresh indication information is also used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.

In some embodiments, the determined current target bank to be refreshed includes a part of the bank in the storage area. Alternatively, the target bank set includes a subset of banks in one or more groups in the storage area. Therefore, it is impossible to determine the target bank set that satisfies the full-bank refresh mode. Therefore, the refresh mode of the target bank to be refreshed currently can be determined as the single-bank refresh mode, or the same-bank refresh mode.

For example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2 and bank4. In addition, the under-refresh count of bank1 is 1, the under-refresh count of bank 2 is 1, and the under-refresh count of bank 4 is 1. The preset number of refresh banks is equal to the number of banks in the storage area, that is, in this example, the preset number of refresh banks is 4. At this time, it can be determined that the number of under-refreshing times of the storage area is 3, and the number of under-refreshing times is less than the preset number of refreshed banks of 4.

Therefore, it can be determined that the refresh mode of the target bank is the single-bank refresh mode or the same-bank refresh mode. The refresh indication information may be used to instruct bank1, bank2 and bank4 to be refreshed in a single bank refresh mode, and the number of times to be refreshed for bank1 is 1, the number of times to be refreshed for bank2 is 1, and the number of times to be refreshed for bank4 is 1. In some embodiments, the refresh indication information may include: 3 refresh commands for single bank refresh. Each refresh command is used to instruct the corresponding target bank to be refreshed to perform a refresh.

For another example, the storage area includes 2 bank groups, and the number of banks in each bank group is 4. For example, bank group1 includes: group1-bank1, group1-bank2, group1-bank3, and group1-bank4. The currently determined banks to be refreshed by group1 include group1-bank1 and group1-bank4. And the under-refresh count of group1-bank1 is 1 and the under-refresh count of group1-bank4 is 1. bank group2 includes: group2-bank1, group2-bank2, group2-bank3 and group2-bank4. The currently determined banks to be refreshed by group2 include group2-bank2 and group2-bank4. And the under-refresh count of group2-bank2 is 1 and the under-refresh count of group2-bank4 is 1.

In this case, the refresh instruction information can be used to instruct group1-bank1 and group1-bank4, group2-bank2 and group2-bank4 to refresh through the single-bank refresh mode, and the number of times to be refreshed for group1-bank1 is 1, and the waiting times for group1-bank4 to be refreshed is 1. The refresh count is 1, the under-refresh count of group2-bank2 is 1, and the under-refresh count of group2-bank4 is 1. In some embodiments, the refresh indication information may include: 1 refresh command for same-bank refresh and 2 refresh commands for single-bank refresh. Among them, the refresh command of the same bank refresh is used to instruct banks 4 in different groups to perform one refresh. The two refresh commands for single-bank refresh are respectively used to instruct group1-bank1 to refresh once, and to instruct group2-bank2 to refresh once.

way six

When determining that the at least one target bank to be refreshed includes N target banks in addition to the target bank set, it is determined that the refresh mode of the N target banks is a single-bank refresh mode or a same-bank refresh mode. That is, the refresh indication information is also used to indicate that the refresh modes of the N target banks are the single-bank refresh mode or the same-bank refresh mode.

For example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2, bank3 and bank4. Furthermore, the under-refresh count of bank1 is 1, the under-refresh count of bank 2 is 2, the under-refresh count of bank 3 is 3, and the under-refresh count of bank 4 is 4.

At this point, two target bank sets can be determined. In addition to these 2 target bank sets, 2 refreshes of bank4 are also included. Therefore, the refresh instruction information may include two full bank refresh commands and two single bank refresh commands. Among them, one full bank refresh command is used to instruct bank1, bank2, bank3 and bank4 to refresh once through the full bank refresh mode, and one full bank refresh command is used to instruct bank2, bank3, bank3 and bank4 to pass the full bank refresh mode Refresh 1 time, 2 refresh commands for single bank refresh are used to instruct bank4 to refresh 2 times. Therefore, at least the time occupied by the refresh commands for 8 single-bank refresh and the delay caused by the execution of the refresh commands are saved.

It should be noted that the target bank set may be determined based on the number of all banks included in the storage area, or may be determined based on the number of partial banks included in the storage area, and the number of preset refresh banks can be set as required to control The number of refreshes of the target bank in the target bank set.

For another example, under special refresh modes for different protocols, such as REFsb or REFpb of LPDDR5, the refresh times of the target banks in the target bank set are different.

When considering the conversion from the single-bank refresh mode to the full-bank refresh mode, the number of all banks in the memory area can be considered. For example, in the scenario of 8 banks in LPDDR5, the number of banks is 8. Therefore, the refresh times of the target banks in the target bank set is at most 8. For another example, in the scenario of 4bank group4bank in LPDDR5, the number of banks in each group is 4, and the number of all banks in the storage area is 16. Therefore, the number of refreshes of target banks in the target bank set is at most 16.

When considering converting the refresh mode of the same bank to the refresh mode of the whole bank, only the number of banks in each group can be considered. For example, in the scenario of 4bank group4bank in LPDDR5, the number of banks in each group is 4. Therefore, the number of refreshes of target banks in the target bank set is at most 4.

Combined with the above postpone scenario, assuming that the mixed refresh of REFpb mode and REFab mode is adopted, M REFpb operations can be directly equivalent to one REFab operation. The following takes M as 8 as an example, as shown in Figure 3d.

It can be seen from the above that the maximum time of the refresh interval satisfies:

T_total=9*tREFI+(8-1)*tRFCab=9*1952+7*180=18828ns

Among them, the controller sends 8 full bank refresh commands.

The effective time T_val for the execution of read and write commands within the maximum refresh interval is:

T_val=9*tREFI=9*1952=17568ns

Within the maximum time T_total of the refresh interval, the execution efficiency Eff of the memory read and write commands satisfies:

Eff=T_val/T_total=17568/18828=93.3%

It can be seen that in the scenario where a large number of delayed refresh operations need to be reissued, the hybrid refresh method can effectively improve the DDR read and write efficiency compared to the efficiency of only REFpb refresh.

S203: The memory 101 refreshes at least one target bank to be refreshed according to the refresh indication information. Specifically, the control circuit 1011 can control the refresh circuit in the memory according to the refresh instruction information, so as to realize the refresh operation on the above-mentioned at least one target bank to be refreshed.

When implementing the refresh mode in the full bank refresh mode, the refresh operation of the target bank set may be initiated according to the target bank set indicated in the refresh instruction information sent by the controller. Specifically, a precharge command may be issued to a target bank in the target bank set, the target bank in the target bank set is closed, and multiple refresh operations of the target bank set are initiated according to the refresh times of the target bank set.

For example, the number of banks included in the storage area is 4, and the storage area includes: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2, bank3 and bank4. In addition, the under-refresh count of bank1 is 2, the under-refresh count of bank 2 is 2, the under-refresh count of bank 3 is 3, and the under-refresh count of bank 4 is 5. The under-refresh count pstpnd_cnt is 12.

Three target bank sets can be determined. The first and second target bank sets can respectively include: bank1, bank2, bank3 and bank4. The third target bank set can include: bank3, bank4, bank4 and bank4. Therefore, when the refresh operation of the first and second target bank sets is performed, a precharge command can be issued to bank1, bank2, bank3 and bank4 to close bank1, bank2, bank3 and bank4. According to the refresh times of the target bank set, 1. Initiate 2 full bank refresh operations of bank1, bank2, bank3 and bank4. When performing the refresh operation of the third target bank set, you can initiate a precharge command to bank3 and bank4, close bank3 and bank4, and initiate a full refresh of bank3, bank4, bank4 and bank4 according to the refresh count of the target bank set is 1. The refresh operation of the bank.

Optionally, after completing the refresh operation, the controller may update the maintenance under-refresh count pstpnd_cnt and the refresh status information of the bank.

Combining the above example, after a full bank refresh operation is completed, the number of under-refresh times pstpnd_cnt and the refresh status information of the bank can be updated. For example, after the refresh operation of the first target bank set is completed, the under-refresh count pstpnd_cnt can be updated to be 8. The under-refresh count of bank1 is 1, the under-refresh count of bank2 is 1, the under-refresh count of bank3 is 2, and the under-refresh count of bank4 is 4. After the refresh operation of the second target bank set is completed, the under-refresh count pstpnd_cnt can be updated to be 4. The under-refresh count of bank1 is 0, the under-refresh count of bank2 is 0, the under-refresh count of bank3 is 1, and the under-refresh count of bank4 is 3. After the refresh operation of the third target bank set is completed, the under-refresh count pstpnd_cnt can be updated to 0. The under-refresh count of bank1 is 0, the under-refresh count of bank2 is 0, the under-refresh count of bank3 is 0, and the under-refresh count of bank4 is 0.

It should be noted that when the number of under-refreshes pstpnd_cnt is updated through the refresh mode of the whole bank, the number of refreshes of the bank determined according to the number of refreshes of the whole-bank refresh mode may be greater than the number of under-refreshes, for example, the number of under-refreshes pstpnd_cnt may be 13～ 1 value in 16, at this time, 4 target bank sets can be determined according to the number of under-refreshes, and each target bank set includes the refresh times of 4 banks. The refresh count of the bank determined according to the refresh count of the full bank refresh mode is 16, which is greater than the under-refresh count pstpnd_cnt. Therefore, it is necessary to update the under-refresh times pstpnd_cnt according to the actual bank refresh times to ensure that pstpnd_cnt does not overflow.

When implementing the refresh mode in the single-bank refresh mode, the bank in the idle state to be refreshed can be preferentially selected through an algorithm to perform the REFpb operation. For example, when the REFpb operation is performed, a fair polling algorithm may be used to preferentially select an idle bank with an identifier of 0 to be refreshed. After the refresh of the corresponding REFpb is completed, the flag to be refreshed of the bank can be marked as 1, indicating that it has been refreshed.

Through the above method, when the automatic refresh mode is selected, the refresh mode is dynamically selected based on whether the number of delayed refreshes satisfies the refresh condition of the corresponding refresh mode. At the same time, when the specific refresh mode selection is completed, the bank selection and the number of refresh cycles are combined to avoid multiple bank shutdowns and service traffic interruptions as much as possible, thereby improving the DDR bandwidth.

The following uses a specific example to illustrate a refresh method provided by the present application. As shown in FIG. 4 , in this embodiment of the present application, the controller 102 may indicate to the memory 101 at least one target bank to be refreshed through the refresh instruction information, and the Combined with the refresh methods of REFab, REFpb and REFsb, REFab, REFpb or REFsb are dynamically selected for refresh, thereby improving the refresh efficiency and the bandwidth of the DDR. Therefore, the controller 102 can control the refresh operation of the memory 101 more flexibly. It can be understood that, compared with the control circuit 1011 , the controller 102 has stronger logical judgment capability and can cope with more complex application scenarios. Compared with the present, the control circuit 1011 sequentially determines the bank to be refreshed next. In this embodiment of the present application, the controller 102 directly instructs at least one bank to be refreshed, which is conducive to enabling the refresh operation to be flexibly adapted to different application scenarios, reducing the The impact of reading and writing on storage space. Specifically include:

Step 401: The controller determines the under-refresh count of each bank and the under-refresh count pstpnd_cnt of the storage area.

For example, when the tREFI timer reaches tREFI_pb, the under-refresh count of the memory area is incremented by 1.

When a refresh in the full refresh mode corresponding to the target bank set is completed, the under-refresh times of the refresh quantity of the target banks in the target bank set is reduced.

When a single bank refresh is completed, the number of under-refreshes is reduced by 1.

Optionally, when the under-refresh count of the bank is 0, the bank may also be marked as a refreshed state. This enables the controller to delete the refreshed bank when determining the target bank to be refreshed, thereby improving refresh efficiency.

Alternatively, after a bank has been refreshed once, the bank is marked as a refreshed state, and a bank that has not been refreshed is marked as an unrefreshed state. Therefore, the idle state bank marked as the unrefreshed state can be refreshed first, and in the scenario where there is no unrefreshed state bank, it can be further determined whether to mark the bank as the unrefreshed state according to whether the bank has under-refreshed times. This enables banks that perform single-bank refresh mode to be refreshed more evenly.

Step 402 : The controller judges whether the refresh condition is satisfied according to the under-refresh count of each bank and the under-refresh count pstpnd_cnt of the storage area.

For the refresh condition, reference may be made to the implementation in S202, which will not be repeated here.

Step 403 : the controller determines whether there is a target bank set, if yes, executes step 404 , if not, executes step 406 .

For example, determine the storage area including: bank1, bank2, bank3 and bank4. The currently determined at least one target bank to be refreshed includes bank1, bank2, bank3 and bank4. Furthermore, the under-refresh count of bank1 is 1, the under-refresh count of bank 2 is 2, the under-refresh count of bank 3 is 3, and the under-refresh count of bank 4 is 4. At this point, two target bank sets can be determined. The first target bank set may include: bank1, bank2, bank3 and bank4, and each bank in the first target bank set is refreshed once. The second target bank set includes: bank2, bank3, bank3 and bank4. Among them, through the full bank refresh mode, bank2 in the second target bank set is refreshed once, bank3 is refreshed twice, and bank4 is refreshed once.

In this step, only one target bank set may be determined, and it is not necessary to determine all possible target bank sets in the memory. Alternatively, all target bank sets of the storage area are determined, which is not limited here.

When the controller determines that the target bank set does not exist, step 406 may be executed to determine whether there is a target bank for single-bank refresh.

Step 404: The controller sends refresh indication information to the memory according to the determined target bank set and the refresh times of the target bank set.

In combination with the above example, when the controller determines that there are multiple target bank sets, it can select any target bank set from the two determined target bank sets to generate corresponding refresh indication information. For example, the first target bank set can be selected to generate corresponding refresh indication information. The refresh instruction information is used to instruct bank1, bank2, bank3 and bank4 to be refreshed once through the full bank refresh mode.

For another example, when the controller determines that there is one target bank set, it generates refresh instruction information according to the target bank set. For example, when the controller determines that there is a second target bank set, the controller generates refresh instruction information according to the second target bank set, and performs refresh in the full bank refresh mode for the second target bank set.

The refresh indication information is used to indicate that the target bank set is refreshed through the full bank refresh mode, and the refresh times of the target bank set. The memory is caused to perform a refresh operation in the full bank refresh mode on the first target set. Among them, it includes: executing the precharge instruction in full bank refresh mode on the target bank in the target bank set, stopping the read and write operations of the target bank, and executing the refresh operation on the target bank in the target bank set. The refresh times of the target bank is based on the target bank. The number of occurrences of the target bank in the bank set is determined.

In some embodiments, the refresh operations of target banks in the target bank set may be performed sequentially. For example, the target bank set includes: bank1, bank2, bank2, bank3. Then the memory can perform the refresh operations of bank1, bank2, bank2, and bank3 in sequence.

When the controller determines that the refresh of the target bank set is completed, it can update the under-refresh times of the target banks in the target bank set and the under-refresh times of the storage area.

Step 405: When the controller determines that the refresh of the target bank set is completed, it judges whether there are multiple target bank sets. If yes, go back to step 404; if not, go back to step 401.

In combination with the above example, when the controller determines that there are multiple target bank sets, it can return to step 404 and continue to perform refresh processing on other target bank sets that have not been refreshed according to the processing procedure of step 404 until all target bank sets are refreshed. . For example, when the first target bank set is selected in step 404 and the refresh is completed, when returning to step 404 for execution again, the second target bank set can be selected to generate corresponding refresh instruction information. The refresh instruction information is used to instruct bank2, bank3, bank3 and bank4 to be refreshed once through the full bank refresh mode. Step 404 is performed on the first target bank set and the second target bank set in turn, so that all target bank sets can be refreshed. 8 under-refresh count minus. At this point, the refresh of the target bank set is completed.

Step 406: The controller determines the target bank to be refreshed according to the bank in the idle state and the bank marked as the state to be refreshed.

Combining the above example, in addition to the two target bank sets, the storage area also includes two to-be-refreshed bank4. Therefore, two single-bank refresh commands can also be generated. Among them, two refresh commands for single bank refresh are used to instruct bank4 to be refreshed twice.

Step 407: The controller sends refresh instruction information to the control circuit according to the target bank to be refreshed.

Wherein, the refresh indication information is used to indicate that the target bank to be refreshed is refreshed through the single bank refresh mode.

When the controller determines that the refresh of the target bank to be refreshed is completed, the controller updates the under-refresh count of the target bank to be refreshed and the under-refresh count of the storage area.

By mixing the two refresh modes of REFab and REFpb, the two modes are dynamically selected according to the number of times to be refreshed during the refresh process, and multiple REFpbs are replaced by REFab to reduce the number of REFpb operations and avoid frequent REFpb crowding DDR bandwidth. In the scenario of data read and write, the DDR efficiency is affected. At the same time, by optimizing the selection of banks in REFpb, the refresh of idle banks is given priority to avoid normal read and write banks being forced to be closed for refresh.

Step 408: The control circuit refreshes the target bank to be refreshed according to the refresh instruction information.

Step 409 : when the controller determines that the refresh of the target bank to be refreshed is completed, the controller returns to step 401 .

When returning to step 401, according to the target bank to be refreshed that has been refreshed, the number of under-refreshes of the target bank to be refreshed can be correspondingly reduced, and the number of under-refreshes pstpnd_cnt of the storage area can be correspondingly reduced. For example, the target bank to be refreshed is bank4, and the number of times of refresh completion is 1. In this case, the number of under-refreshes in bank4 can be reduced by one time and the number of under-refreshes in the storage area pstpnd_cnt can be correspondingly reduced. For example, the target bank to be refreshed is bank4, and the number of times of refresh completion is 2. In this case, the number of under-refreshes in bank4 can be reduced twice and the number of under-refreshes in the storage area pstpnd_cnt can be reduced accordingly.

The embodiment of the present application also provides a controller. The controller can be used to implement the refresh method shown in FIG. 2 or FIG. 4 . Referring to FIG. 5 , the controller 500 includes a transceiver unit 501 and a processing unit 502 .

The processing unit 502 is configured to determine at least one target bank to be refreshed according to the idle state of at least one bank in the storage area; according to the at least one target bank to be refreshed, generate refresh indication information and send it through the transceiver unit 501 to the memory; the refresh indication information is used to control the memory to refresh the at least one target bank to be refreshed.

In a possible implementation manner, the processing unit 502 is configured to determine, in at least one bank in an idle state, at least one candidate bank whose number of under-refreshes reaches a first threshold, wherein the number of under-refreshes is used to indicate that the bank is in the pre-refresh state. The number of times that the refresh is not performed within the set refresh duration; the target bank to be refreshed is determined in the at least one candidate bank.

A possible implementation manner, the processing unit 502 is configured to, before determining the target bank to be refreshed in the at least one candidate bank, is further configured to: determine that the storage area satisfies a refresh condition; the refresh condition includes at least one of the following: Item: the under-refresh count of the at least one bank reaches the first threshold; the at least one bank is in an idle state; the at least one bank satisfies the forced refresh condition.

A possible implementation manner, the processing unit 502 is configured to generate refresh indication information of the target bank set when it is determined that there is a target bank set that satisfies the full bank refresh mode, where the refresh indication information is used to indicate the target bank The refresh mode of the set is a full bank refresh mode, and the target bank to be refreshed in the target bank set is one or more of the at least one target bank to be refreshed.

A possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the processing unit 502 is configured to determine the at least one refresh mode. In a target bank to be refreshed, when there is no target bank set satisfying the all-bank refresh mode, it is determined that the refresh mode of the at least one target bank to be refreshed is the single-bank refresh mode or the same-bank refresh mode.

A possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the processing unit 502 is used for at least one When the target banks to be refreshed include N target banks to be refreshed in addition to the target bank set, it is determined that the refresh modes of the N target banks to be refreshed are single-bank refresh mode or same-bank refresh mode.

The embodiment of the present application also provides a memory. This storage can be used to perform the refresh method shown in FIG. 2 or FIG. 4 . Referring to FIG. 6 , the memory 600 provided by this embodiment of the present application may include: a control unit 601 , a refresh unit 602 , and a storage unit 603 . Exemplarily, the memory 600 may be the memory 101 in FIG. 1a, the control unit 601 may be the control circuit 1011 in FIG. 1a, the refresh unit 602 may be at least one of the refresh circuits 1-N in FIG. 1a, the storage unit 603 It may be at least one (ie, a storage area) of banks 1 to N in FIG. 1a. Wherein: the storage unit 603 includes at least one library bank; the refresh unit 602 is used to refresh the at least one bank;

The control unit 601 is configured to receive refresh indication information sent by the controller, where the refresh indication information is used to indicate at least one target bank to be refreshed in the storage unit 603; the at least one target bank to be refreshed is a The idle state of at least one bank in the storage unit 603 of the memory is determined; and according to the refresh indication information, the refresh unit 602 is controlled to refresh the at least one target bank to be refreshed.

In a possible implementation manner, the refresh unit 602 is at least one; the control unit 601 is specifically configured to respectively control the at least one refresh unit 602 to refresh at least one target bank to be refreshed respectively.

In a possible implementation manner, the refresh indication information is used to indicate that the refresh mode of the target bank to be refreshed in the target bank set is the full bank refresh mode; the target bank to be refreshed in the target bank set is the One or more items in at least one target bank to be refreshed; the control unit 601 is specifically configured to, according to the refresh instruction information, control the refresh unit 602 corresponding to the target bank set to refresh the The target bank to be refreshed in the target bank set. In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.

The control unit 601 is specifically configured to, according to the refresh indication information, control the refresh unit 602 corresponding to the at least one target bank to be refreshed to refresh the at least one target to be refreshed through a single bank refresh mode or a same bank refresh mode. bank.

In a possible implementation manner, the control unit 601 may further determine that the at least one to-be-refreshed target bank set does not exist in the at least one to-be-refreshed target bank set satisfying the full-bank refresh mode The refresh mode of the target bank is single bank refresh mode or same bank refresh mode.

In a possible implementation manner, the refresh indication information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode; the N target banks to be refreshed In determining the at least one target bank to be refreshed, the target bank to be refreshed other than the target bank set; the control unit 601 is also used for, according to the refresh instruction information, through the single bank refresh mode or The refresh unit 602 corresponding to the at least one target bank to be refreshed is controlled in the same bank refresh mode to refresh the N target banks to be refreshed.

It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical function division, and other division methods may be used in actual implementation. Each functional unit in the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, random access memory (random access memory, RAM), read only memory (read only memory, ROM), magnetic disk or optical disk and other media that can store program codes.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

A method for refreshing a memory, characterized in that it is applied to a controller; the controller is used to control the memory; the storage area of the memory includes at least one bank; the method includes:

Determine at least one target bank to be refreshed according to the idle state of at least one bank in the storage area;

According to the at least one target bank to be refreshed, refresh indication information is generated and sent to the memory; the refresh indication information is used to control the memory to refresh the at least one target bank to be refreshed.
The method according to claim 1, wherein the determining at least one target bank to be refreshed comprises:

Determine at least one candidate bank whose under-refresh count reaches a first threshold in at least one bank in an idle state, wherein the under-refresh count is used to indicate the number of times the bank has not been refreshed within a preset refresh duration;

A target bank to be refreshed is determined in the at least one candidate bank.
The method according to claim 2, wherein before determining the target bank to be refreshed in the at least one candidate bank, the method further comprises:

determining that the storage area satisfies the refresh condition;

The refresh condition includes at least one of the following:

The under-refresh count of the at least one bank reaches a first threshold;

the at least one bank is in an idle state;

The at least one bank satisfies the forced refresh condition.
The method according to any one of claims 1-3, wherein the generating refresh indication information according to the at least one target bank to be refreshed comprises:

When it is determined that there is a target bank set that satisfies the full bank refresh mode, refresh indication information of the target bank set is generated, where the refresh indication information is used to indicate that the refresh mode of the target bank set is the full bank refresh mode, and the target bank The target bank to be refreshed in the bank set is one or more items of the at least one target bank to be refreshed.
The method according to any one of claims 1-4, wherein the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.
The method according to any one of claims 1-4, wherein the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode;

The method also includes:

When it is determined that there is no target bank set satisfying the all-bank refresh mode in the at least one target bank to be refreshed, it is determined that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.
The method according to claim 4, wherein the refresh indication information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode;

The method also includes:

When the at least one target bank to be refreshed includes N target banks to be refreshed in addition to the target bank set, it is determined that the refresh modes of the N target banks to be refreshed are single bank refresh mode or Same as bank refresh mode.
A controller, characterized in that it includes a processing circuit and an interface circuit, wherein:

The processing circuit is configured to determine at least one target bank to be refreshed according to the idle state of at least one bank in the storage area of the memory; generate refresh indication information according to the at least one target bank to be refreshed;

The interface circuit is configured to send the refresh indication information to the memory, where the refresh indication information is used to control the memory to refresh the at least one target bank to be refreshed.
The controller according to claim 8, wherein the processing circuit is specifically used for:

Determine at least one candidate bank whose under-refresh count reaches a first threshold in at least one bank in an idle state, wherein the under-refresh count is used to indicate the number of times the bank has not been refreshed within a preset refresh duration;

A target bank to be refreshed is determined in the at least one candidate bank.
The controller according to claim 9, wherein the processing circuit is specifically used for:

Before determining the target bank to be refreshed in the at least one candidate bank, determine that the storage area satisfies the refresh condition;

The refresh condition includes at least one of the following:

The under-refresh count of the at least one bank reaches a first threshold;

the at least one bank is in an idle state;

The at least one bank satisfies the forced refresh condition.
The controller according to any one of claims 8-10, wherein when generating the refresh indication information according to the at least one target bank to be refreshed, the processing circuit is specifically configured to:

When it is determined that there is a target bank set that satisfies the full bank refresh mode, refresh indication information of the target bank set is generated, where the refresh indication information is used to indicate that the refresh mode of the target bank set is the full bank refresh mode, and the target bank The target bank to be refreshed in the bank set is one or more items of the at least one target bank to be refreshed.
The controller according to any one of claims 8-11, wherein the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode .
The controller according to any one of claims 8-11, wherein the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode ;

The processing circuit is also used for:

When it is determined that there is no target bank set satisfying the all-bank refresh mode in the at least one target bank to be refreshed, it is determined that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.
The controller according to claim 11, wherein the refresh instruction information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode;

The processing circuit is also used for:

When it is determined that there are N target banks to be refreshed other than the target bank set in the at least one target bank to be refreshed, it is determined that the refresh modes of the N target banks to be refreshed are single bank refresh mode or Same as bank refresh mode.
A memory is characterized by comprising a control circuit, a refresh circuit and a storage area, wherein:

the storage area includes at least one bank;

the refresh circuit for refreshing the at least one bank;

The control circuit is configured to receive refresh indication information sent by the controller, where the refresh indication information is used to indicate at least one target bank to be refreshed in the storage area; the at least one target bank to be refreshed is based on the memory The idle state of at least one bank in the storage area is determined; and according to the refresh indication information, the refresh circuit is controlled to refresh the at least one target bank to be refreshed.
The memory according to claim 15, wherein the refresh circuit is at least one;

The control circuit is specifically configured to respectively control at least one refresh circuit to refresh at least one target bank to be refreshed respectively.
The memory according to any one of claims 15-16, wherein the refresh indication information is used to indicate that the refresh mode of the target bank to be refreshed in the target bank set is a full bank refresh mode; The target bank to be refreshed is one or more of the at least one target bank to be refreshed;

The control circuit is specifically configured to, according to the refresh instruction information, control the refresh circuit corresponding to the target bank set to refresh the target bank to be refreshed in the target bank set through a full bank refresh mode.
The memory according to any one of claims 15-17, wherein the refresh indication information is further used to indicate that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode;

The control circuit is specifically configured to control the refresh circuit corresponding to the at least one target bank to be refreshed to refresh the at least one target bank to be refreshed through the single bank refresh mode or the same bank refresh mode according to the refresh instruction information.
The memory according to claim 18, wherein the control circuit is further configured to:

When it is determined that there is no target bank set satisfying the all-bank refresh mode in the at least one target bank to be refreshed, it is determined that the refresh mode of the at least one target bank to be refreshed is a single-bank refresh mode or a same-bank refresh mode.
The memory according to claim 17, wherein the refresh indication information is further used to indicate that the refresh mode of the N target banks to be refreshed is a single-bank refresh mode or a same-bank refresh mode; The target bank to be refreshed is the target bank to be refreshed other than the set of target banks in determining the at least one target bank to be refreshed;

The control circuit is further configured to control the refresh circuit corresponding to the at least one target bank to be refreshed to the N target banks to be refreshed through a single bank refresh mode or a same bank refresh mode according to the refresh instruction information. refresh.
A storage system, characterized by comprising the controller according to any one of claims 8-14, and the memory according to any one of claims 15-20.