WO2011012032A1

WO2011012032A1 - System and method for adjusting dram operating frequency

Info

Publication number: WO2011012032A1
Application number: PCT/CN2010/074220
Authority: WO
Inventors: 林川
Original assignee: 北京中星微电子有限公司
Priority date: 2009-07-29
Filing date: 2010-06-22
Publication date: 2011-02-03
Also published as: CN101620883B; CN101620883A

Abstract

A system and a method for adjusting dynamic random access memory (DRAM) operating frequency are provided. The DRAM operating frequency adjusting system comprises: a statistics module, for counting the effective operating state of DRAM in a predetermined time interval to acquire bandwidth utilization of current DRAM operating frequency; a parameter configuration module, including a target operating frequency configuration sub-module which is used for generating a target operating frequency; a frequency switch controller, for adjusting the current DRAM operating frequency to a target operating frequency. The system adjusts the performance power consumption balance point of the DRAM so as to improve operating speed of the chip system and save power consumption effectively.

Description

DRAM operating frequency adjustment system and method

The present invention relates to the field of dynamic random access memories (DRAMs), and more particularly to a DRAM operating frequency adjustment system and method.

Background technique

DRAM (Dynamic Random-Access Memory), which is a dynamic random access memory.

DRAM can only keep data for a short time. DRAM uses capacitor storage and must be refreshed at intervals to maintain the data stored therein. This refresh is handled by the DRAM controller. The refresh operation of the DRAM consumes a relatively large amount of power, and the required battery capacity is large.

As a typical on-chip integrated system (SOC), a multimedia chip system has multiple functional modules, such as processors, hardware accelerators, and the like. These function modules operate independently and access various memory resources as needed. Since some functional modules of the multimedia chip system generally store files or temporary data in an external DRAM during data processing, the system cost is reduced. For complex multimedia chip systems, different tasks may have very large differences in memory bandwidth requirements. For example, when playing streaming media files in high-definition format, the multimedia chip system needs the processor and hardware accelerator to run at full speed, and the running frequency of DRAM is above 166MHz. When playing MP3, the computing capacity of the multimedia chip system and the required memory bandwidth are drastically reduced, DRAM Running at 50MHz will meet the requirements. As such, the power requirements of the multimedia chip are increased.

Traditional multimedia chip systems do not fully take into account the characteristics of these tasks. It is difficult to find a correct balance between performance and power consumption at a special stage, such as when the system is pre-configured with DRAM operating frequency at system startup.

Therefore, a technical problem that needs to be solved urgently by those skilled in the art is: how to creatively provide a method for adjusting the operating frequency of the DRAM to adjust the balance between the performance and the power consumption of the DRAM, thereby ensuring the chip system. While running at a high speed, it effectively improves the power consumption of the DRAM.

Summary of the invention

The technical problem to be solved by the present invention is to provide a solution capable of adjusting the operating frequency of a DRAM and a DRAM operating frequency adjustment system using the solution to adjust the DRAM. A balance of performance and power consumption.

In order to solve the above technical problem, the present invention provides a DRAM operating frequency adjustment system, which includes:

The statistics module calculates the effective working state of the DRAM in the preset time interval;

a parameter configuration module, generating a target operating frequency according to statistics of an effective working state of the DRAM; and

And a frequency switching controller that adjusts a current operating frequency of the DRAM to the target operating frequency.

The invention also provides a method for adjusting the operating frequency of a DRAM, comprising:

Count the effective working state of the DRAM in the preset time interval, and obtain the bandwidth utilization rate of the current DRAM operating frequency;

Generating a target operating frequency when the bandwidth utilization is not suitable for the running condition of the current application scenario;

The current DRAM operating frequency is adjusted to the target operating frequency.

Compared with the prior art, the present invention has the following advantages:

The invention obtains the bandwidth utilization rate of the current DRAM operating frequency by counting the effective working state of the DRAM in the preset time interval, and adjusts the current DRAM operating frequency to the appropriate when the bandwidth utilization is not suitable for the operating condition of the current application scenario. The operating frequency of the current application scenario. Specifically, in the case of low DRAM operating frequency and high bandwidth utilization, the current operating frequency of the DRAM can be improved according to the current application scenario; in the case of high DRAM operating frequency and low bandwidth utilization, the current application scenario can be reduced. Current operating frequency of DRAM. This way of dynamically adjusting the operating frequency based on bandwidth utilization is more conducive to balancing the operating efficiency and power consumption of the DRAM. DRAWINGS

1 is a structural block diagram of an embodiment of a DRAM operating frequency adjustment system;

Figure 2 is a diagram showing the operation state of the DRAM;

3 is a structural block diagram of an embodiment of a statistical module;

4 is a structural block diagram of an embodiment of a parameter configuration module;

5 is a structural block diagram of another embodiment of a DRAM operating frequency adjustment system;

Figure 6 is a timing diagram of DRAM operation; 7 is a structural block diagram of another embodiment of a parameter configuration module;

Figure 8 is a block diagram showing the structure of an embodiment of a frequency switching controller;

Figure 9 is a block diagram showing the structure of an embodiment of a DRAM controller;

Figure 10 is a flow chart of an embodiment of a DRAM operating frequency adjustment method.

detailed description

The present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

Referring to Figure 1, there is shown a block diagram of an embodiment of a DRAM operating frequency adjustment system 100 of the present invention. The DRAM operating frequency adjustment system 100 includes a statistic module 11, a parameter configuration module 12, and a frequency switching controller 13.

The statistical module 11 counts the effective working state of the DRAM, and can obtain the current bandwidth utilization of the DRAM by counting the effective working state of the DRAM, that is, the bandwidth utilization of the DRAM at the current operating frequency.

The parameter configuration module 12 generates a target operating frequency suitable for the current operating environment based on the statistics made by the statistical module.

The frequency switching controller 13 adjusts the current operating frequency of the DRAM to the target operating frequency. In an actual application, the statistics module 11 can calculate the working state of the DRAM in a preset time interval, and calculate the current DRAM in a preset time interval according to the statistical result of the working state of the DRAM in the preset time interval. Bandwidth utilization at operating frequency.

The operating state of the DRAM is determined by the data access commands of the DRAM. These commands are all generated by the finite state machine 910 in the DRAM controller 91. Referring to FIG. 2, corresponding to these data access commands, the working state of the finite state machine generally includes waiting (IDLE), pre-charging (PRE), activating (ACT), reading (READ), writing (WRIT), and the like. Therefore, the statistics module 11 can obtain the statistics of the effective working state of the DRAM by counting the non-waiting working state of the finite state machine 910. The statistic module 11 determines the real-time bandwidth utilization of the DRAM by counting the non-waiting operation state of the finite state machine 910 within a predetermined time interval, and determines whether the DRAM frequency needs to be adjusted.

The preset time interval may be configured according to a current application scenario. When the bandwidth utilization of the DRAM at the current operating frequency is not suitable for the running condition of the current application scenario, the statistics module 11 may use a certain The parameter configuration module 12 is notified by the parameter configuration module 12 to generate a target operating frequency suitable for the current application scenario according to the actual required bandwidth utilization. The frequency switching controller 13 adjusts the current operating frequency of the DRAM to the target operating frequency. In this way, by dynamically counting the bandwidth utilization and adjusting the operating frequency of the DRAM in real time, the operating efficiency and power consumption of the DRAM are at a good balance point.

Referring to FIG. 3, in a preferred embodiment of the present invention, the statistics module 11 may include an effective working status statistics sub-module 111 and an interrupt control module 112.

The valid working state statistics sub-module 111 accumulates the non-waiting working state of the finite state machine 910 in the DRAM controller 91 within the preset time interval to obtain the effective working state of the DRAM. The non-waiting operating state includes pre-charging, activating, reading, writing, and the like working states of the finite state machine 910 corresponding to various data access commands.

The interrupt control module 112 generates an interrupt signal that adjusts the operating frequency of the DRAM based on the bandwidth utilization of the DRAM at the current operating frequency. The interrupt signal includes a first interrupt signal and a second interrupt signal. At the end of the preset time interval, when the current bandwidth utilization is lower than the actually required bandwidth utilization, the interrupt control module 112 generates a first interrupt signal indicating that the operating frequency of the DRAM needs to be reduced; During the time interval, when the accumulated value of the non-waiting operating state of the finite state machine 910 exceeds the preset interrupt condition threshold, the interrupt control module 112 generates a second interrupt signal indicating that the operating frequency of the DRAM needs to be increased.

The valid working status statistics sub-module 111 may further include a statistical time interval register 1110, a time counter 1112, a status counter 1113, and a cumulative status register 1114.

The statistical time interval register 1110 configures the preset time interval.

The time counter 1112 counts during the preset time interval and automatically clears its timing value when a predetermined time interval ends.

The status counter 1113 accumulates the non-waiting operation state of the finite state machine 910 in the DRAM controller 91 in real time during the preset time interval, and the timing value of the time counter 1112 is equal to the configuration of the statistical time interval register 1110. At the time interval, the status counter 1113 copies its count value to the accumulation status register 1114 while automatically clearing its count value. That is, the count value of the status counter 1113 changes over time within the preset time interval. When the timing value of the time counter 1112 is equal to the time configured by the statistical time interval register 1110 At the time of the interval, the count value of the state counter 1113 is the cumulative result of the non-waiting operation state of the finite state machine 910 within the preset time interval.

The accumulation status register 1114 stores the count value of the status counter 1113 when the timing value of the time counter 1112 is equal to the time interval configured by the statistical time interval register 1110. The bandwidth utilization of the DRAM during the time interval can be determined based on the count value of the accumulated status register 1114.

The interrupt control module 112 can further include an interrupt condition threshold register 1121 and an interrupt control logic module 1123.

The Interrupt Condition Threshold Register 1121 configures the bandwidth utilization threshold.

The interrupt control logic module 1123 issues an interrupt signal based on the count value of the status counter 1113 within the preset time interval and the bandwidth utilization threshold, or based on the count value held by the cumulative status register 1114.

The interrupt control logic module 1123 includes a first interrupt control unit 1123a and a second interrupt control unit 1123b. The first interrupt control unit 1123a determines, at the end of the preset time interval, whether the bandwidth utilization of the DRAM at the current operating frequency is low according to the count value of the cumulative status register 1114, and the bandwidth of the DRAM at the current operating frequency. The utilization is lower than the demand value, and a first interrupt signal indicating that the operating frequency of the DRAM needs to be reduced is generated. The second interrupt control unit 1123b determines, according to the count value of the state counter 1113 and the bandwidth utilization threshold, whether the bandwidth utilization of the DRAM at the current operating frequency is high during the preset time interval, and when the DRAM is currently When the bandwidth utilization rate at the operating frequency is too high, that is, the bandwidth utilization of the DRAM at the current operating frequency exceeds the bandwidth utilization threshold, a second interrupt signal indicating that the operating frequency of the DRAM needs to be increased is generated.

Correspondingly, referring to FIG. 4, the parameter configuration module 12 includes a target operating frequency configuration sub-module 121, and the target operating frequency configuration sub-module 121 includes:

The first configuration unit 1211 generates a target operating frequency lower than the current DRAM operating frequency according to the first interrupt signal; and

The second configuration unit 1212 generates a target operating frequency higher than the current DRAM operating frequency according to the second interrupt signal.

In the present embodiment, the interrupt signal generation includes two cases. In one case, at the preset At the end of the time interval, when the bandwidth utilization of the DRAM determined according to the count value of the accumulated status register value 1114 is lower than the actual required bandwidth utilization, the interrupt control logic module 1123 may issue a first interrupt signal to the system indicating the current operation of the DRAM. The frequency is too high. In another case, the interrupt control logic module 1123 determines the real-time bandwidth utilization of the DRAM according to the count value of the state counter value in real time during a preset time interval, when the real-time bandwidth utilization exceeds the bandwidth utilization threshold. Then, the interrupt control logic module 1123 will issue a first interrupt signal indicating that the current operating frequency of the DRAM is low.

Figure 2 shows several operating states of the DRAM. In Figure 2, except for the IDLE state, the other operating states are the active operating states of the DRAM, i.e., the non-waiting state of the finite state machine 910. Assuming that the current DRAM operating frequency is 160MHz and the status counter accumulates 80M times in one second, the bandwidth utilization of the current DRAM operating frequency is (80/160) *100%=50%.

For example, the current operating frequency of DRAM is 120MHz, and the DRAM is SDRAM 16bit memory. The statistical result of bandwidth utilization obtained by the statistical module 11 is 20%, that is, the current effective bandwidth of the DRAM is 120*16*20%=384Mbps. Under the premise that the application scenario does not change, the bandwidth utilization can be considered stable. If it is considered that the bandwidth utilization is 60%, the interrupt control module 112 issues a first interrupt signal, and the parameter configuration module 12 configures the target operating frequency of the DRAM to be 384/16/60% MHz, that is, 40 MHz. The frequency switching controller 13 switches the operating frequency of the DRAM to 40 MHz. At this time, the effective bandwidth is also 40*16*60% Mbps, which is 384 Mbps, but the operating frequency of the DRAM is reduced, saving the power consumption of the DRAM.

Or, for example, the current DRAM runs at 40MHz and the DRAM is a SDRAM 16bit memory. The bandwidth utilization threshold set for the current application scenario is 60%. If the bandwidth utilization obtained by the statistic module 11 is 80% and the bandwidth utilization threshold (60%) is exceeded, the interrupt control module 112 will issue a second interrupt signal. If it is considered that the bandwidth utilization is 40% in the current application scenario, the parameter configuration module 12 configures the target operating frequency of the DRAM to be (40*16*80%) /16/40% MHz, that is, 80 MHz. The frequency switching controller 13 switches the operating frequency of the DRAM to 80 MHz. In this way, the operating efficiency of the DRAM is improved.

Referring to FIG. 5, in order to avoid data loss of the DRAM during frequency adjustment, in the embodiment of the present invention, the DRAM operating frequency adjustment system 100 may further include a clock control module 15. Clock The control module 15 is configured to control the DRAM to perform a refresh operation according to an internal clock when the frequency switching controller 13 is in operation, and to control the DRAM to perform a refresh operation according to the system clock after the frequency switching controller 13 completes the operation.

In practical applications, there are two types of DRAM refresh operations: Auto Refresh (AR) and Self Refresh (SR). Accordingly, DRAM has two modes of operation, AR mode and SR mode. In AR mode, DRAM is refreshed according to the system clock. In SR mode, DRAM no longer relies on the system clock to operate, but refreshes according to the internal clock. After the DRAM enters the SR mode, it is not necessary to provide the system clock for the DRAM, so the system clock frequency can be switched at this time, that is, the current operating frequency of the DRAM is adjusted to the target operating frequency. After exiting the SR mode, the DRAM will operate at the target operating frequency.

Referring to the DRAM operation timing chart shown in Fig. 6, CLK is the system clock supplied to the DRAM, and the frequency before the time T2 and the frequency after the time Tn+1 may be different. In the embodiment of the present invention, the system clock frequency before Τ2 is the current DRAM operating frequency, and the frequency switching operation is performed within the timing of T2~Tn+l. The system clock frequency after time Tn+1 is the target operating frequency.

Since all external signals except the clock enable signal (Clock Enable: CKE) are invalid in SR mode, there is no need to externally provide a refresh command, so that the frequency switching operation in SR mode can make DRAM efficiency and power consumption. The balance is reached and does not result in the loss of data.

To ensure that the system clock is in effect at the completion of the frequency switching, the system clock can be determined by the timing check parameters. Referring to FIG. 5, the DRAM operating frequency adjustment system 100 may further include a timing check parameter validation module 16. The timing check parameter validation module 16 is configured to obtain a corresponding timing check parameter according to the target operating frequency.

In general, the timing check parameters are linear with the system clock frequency of the DRAM. For example, assuming a DRAM refresh interval of 10μ8, then at 100 MHz, the timing check parameter needs to be configured to 1000; at 10 MHz, the timing check parameter needs to be configured to 100.

The clock control module 15 and the timing check parameter validation module 16 may be located in the DRAM controller or external to the DRAM controller.

It can be understood that the DRAM operating frequency adjustment system 100 can also include the frequency The DRAM controller 91 to which the controller is connected is switched.

Referring to FIG. 7, the parameter configuration module 12 may further include:

The frequency switching request signal configuration sub-module 122 is configured to configure a frequency switching request signal whose default value is invalid;

The handshake signal configuration sub-module 123 is configured to configure a handshake signal whose default value is invalid; and a timing check parameter configuration sub-module 124 configured to respectively configure corresponding timing check parameters for the DRAM operating frequency.

Referring to FIG. 8, the frequency switching controller 13 may include a frequency switching request generating module 131, a frequency switching module 133, and an invalid request signal setting module 135.

The frequency switching request generation module 131 is configured to generate a frequency switching request and set the frequency switching request signal to be valid.

The frequency switching module 133 is configured to switch the current DRAM operating frequency to the target operating frequency according to the valid handshake signal.

The invalid request signal setting module 135 is configured to restore the frequency switching request signal to be invalid after the frequency switching module completes the frequency switching.

Referring to FIG. 9, the DRAM controller 91 may further include a self-refresh control module 912, a handshake signal triggering module 913, a timing check parameter determining module 914, a self-refresh exiting module 915, and a handshake signal closing module 916.

The self-refresh control module 912 is configured to issue a first control command for the DRAM to refresh according to the internal clock according to the valid signal of the frequency switching request.

The handshake signal triggering module 913 is configured to assert the handshake signal after issuing the first control command.

The timing check parameter determining module 914 is configured to extract a timing check parameter corresponding to the target operating frequency when the frequency switching request signal is restored to be invalid.

The self-refresh exit module 915 is configured to determine a system clock according to the timing check parameter, and issue a second control command that the DRAM refreshes according to the system clock.

The handshake signal closing module 916 is configured to restore the handshake signal to be invalid after issuing the second control command.

More preferably, in order to avoid DRAM loss data during frequency adjustment, the DRAM control The device can further include:

The data request suspension module 917 is configured to: after receiving the valid signal of the frequency switching request, execute the received data request, and stop responding to the new data request before issuing the first control command; and the data request execution module 918, configured to: When the handshake signal is restored to be invalid, a new data request is received.

In practice, the DRAM controller 91 accepts external data access requests to the DRAM. The DRAM controller 91 can first complete all current data access requests that have entered the DRAM controller 91 prior to frequency switching without simultaneously responding to new data access requests, i.e., preventing the functional modules from accessing the DRAM. In this way, the situation of data loss during the frequency adjustment process is avoided.

In addition, in the self-refresh mode, all external signals except the clock enable signal (Clock Enable: CKE) are invalid, and no external refresh command is required, which helps to further improve power consumption.

In order to enable those skilled in the art to better understand the present invention, the operation of the DRAM operating frequency adjustment system will be described below based on the above preferred embodiments.

It is assumed that in the parameter configuration module, the target operating frequency has been generated by the target operating frequency configuration sub-module 121; the frequency switching request signal configuration sub-module 122 configures the frequency switching request signal clock_switch_request (frequency switching request signal clock_switch_request Hereinafter, the default value of csr) is used, and the default value of the frequency switching request signal csr is invalid, that is, the default value of the frequency switching request signal csr is set to binary code 0, and the handshake signal configuration sub-module configuration 123 handshake signal sdrc_lock (handshake signal sdrc_lock Hereinafter, the default value of the handshake signal si is invalid, that is, the default value of the handshake signal si is set to binary code 0. Timing Check Parameters The configuration sub-module pin 124 configures the corresponding timing check parameters for the current operating frequency of the DRAM and the target operating frequency.

In this case, the process of switching the current operating frequency of the DRAM to the target operating frequency may include the following steps:

Step S101, the frequency switching request generating module 131 generates a frequency switching request signal csr, and sets the value of the frequency switching request signal csr to an active state, that is, the value of the frequency switching request signal csr is set to binary code 1;

Step S102, after detecting that the value of csr is 1, the self-refresh control module 912 issues a DRAM. a first control command for performing a refresh operation according to an internal clock;

Step S103, the handshake signal triggering module 913 sets the value of the handshake signal si to an active state, that is, the value of the handshake signal si is set to binary code 1;

Step S104, after detecting that the value of the handshake signal si is 1, the frequency switching module 133 switches the current DRAM operating frequency to the target operating frequency;

Step S105, after completing the frequency switching, the invalid request signal setting module 135 restores the value of the frequency switching request signal csr to 0;

Step S106: After detecting that the value of the frequency switching request signal csr is 0, the timing check parameter determining module 914 extracts the timing check parameter corresponding to the target operating frequency;

Step S107: The self-refresh exit module 915 determines a system clock according to the timing check parameter, and issues a second control command that the DRAM performs a refresh operation according to the system clock.

Step S108: The handshake signal closing module 916 restores the value of the handshake signal si from 1 to 0. Of course, the above-mentioned DRAM controller 91 and the frequency switching controller 13 use the frequency switching request signal and the handshake signal interaction mode only as an example, and any interaction mode is feasible by those skilled in the art as needed.

The invention can be applied to a multimedia chip system. When a function module such as a processor or a hardware accelerator of a multimedia chip system accesses DRAM, the DRAM operating frequency can be automatically adjusted according to the characteristics of the multimedia task.

Referring to FIG. 10, a flow chart of an embodiment of a DRAM operating frequency adjustment method according to the present invention is shown, which may specifically include:

Step 401: Count the effective working state of the DRAM in the preset time interval, and obtain the bandwidth utilization ratio of the DRAM at the current operating frequency;

Step 402: Generate a target running frequency when the bandwidth utilization is not suitable for the running condition of the current application scenario.

Step 403: Adjust the current DRAM operating frequency to the target operating frequency.

The statistical step of the effective operating state of the DRAM may include the following sub-steps:

Sub-step A1, accumulating the non-waiting working state of the finite state machine in the DRAM controller during the preset time interval, and obtaining the effective working state of the DRAM;

Sub-step A2, at the end of the preset time interval, according to the effective working state of the DRAM, Determining the current bandwidth utilization of the DRAM; when the current bandwidth utilization of the DRAM is low, generating a first interrupt signal that needs to reduce the operating frequency of the DRAM; when the current bandwidth utilization of the DRAM exceeds the pre-predetermined time interval When the interrupt condition threshold is set, a second interrupt signal that increases the operating frequency of the DRAM is generated.

The generating step of the target operating frequency may include:

Generating a target operating frequency lower than a current DRAM operating frequency according to the first interrupt signal when the first interrupt signal is generated; or generating a higher than current DRAM running according to the second interrupt signal when the second interrupt signal is generated The target operating frequency of the frequency.

In a preferred embodiment of the present invention, the DRAM operating frequency adjustment method may further include:

During frequency adjustment, the DRAM is controlled to refresh according to the internal clock, and when the frequency adjustment is completed, the DRAM is controlled to refresh according to the system clock.

Preferably, the system clock is determined by a timing check parameter, and the method may further include:

Corresponding timing check parameters are obtained according to the target operating frequency.

In a preferred embodiment of the present invention, the method may further include:

The preset default value is an invalid frequency switching request signal, the default value is an invalid handshake signal, and timing check parameters corresponding to various DRAM operating frequencies;

The operating frequency adjustment step may include the following sub-steps:

Sub-step Bl, generating a frequency switching request, and setting the frequency switching request signal to be valid; sub-step B2, issuing a first control command for performing a refresh operation of the DRAM according to the internal clock according to the valid signal of the frequency switching request;

Sub-step B3, after the first control command is issued, the handshake signal is set to be valid; sub-step B4, according to the valid handshake signal, the current DRAM operating frequency is switched to the target operating frequency;

Sub-step B5, after the frequency switching is completed, the frequency switching request signal is restored to be invalid; sub-step B6, when the frequency switching request signal is restored to be invalid, the timing check parameter corresponding to the target operating frequency is extracted;

Sub-step B7, determining a system clock according to the timing check parameter, and issuing a DRAM according to Sub-step B8, after the second control command is issued, the handshake signal is restored to be invalid. In practice, in order to avoid data loss of the DRAM during frequency adjustment, the method may further include: after receiving the valid signal of the frequency switching request, executing the received data request, and stopping before issuing the first control command Respond to new data requests;

When the handshake signal is restored to be invalid, a new data request is received.

For the method embodiment, since it is basically similar to the device embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the device embodiment.

The DRAM operating frequency adjustment system and a DRAM operating frequency adjustment method provided by the present invention are described in detail. The principle and implementation manner of the present invention are described in the following. The description of the above embodiment is only The method for understanding the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in specific embodiments and application scopes. The description should not be construed as limiting the invention.

Claims

Claim

A DRAM operating frequency adjustment system, characterized in that:

a parameter configuration module that generates a target operating frequency based on statistics on the effective working state of the DRAM;

2. The system of claim 1 wherein the statistics module obtains statistics of the effective operating state of the DRAM by counting non-waiting operating states of the finite state machine in the DRAM.

3. The system according to claim 1, wherein the statistical module comprises an effective working state statistical sub-module and an interrupt control module, and the effective working state statistical sub-module accumulates the finite state machine in the DRAM in a preset time interval. The bandwidth utilization of the DRAM at the current operating frequency is obtained without waiting for the working state, and the interrupt control module generates an interrupt signal for adjusting the operating frequency of the DRAM according to the bandwidth utilization.

4. The system of claim 3, wherein the valid working status statistics sub-module comprises:

a statistical time interval register, configured with the preset time interval;

a time counter, which is timed within the preset time interval, and automatically clears its timing value at the end of a preset time interval;

a status counter that accumulates a non-waiting operating state of the finite state machine during the preset time interval, and copies the count value to another when the time counter of the time counter is equal to the time interval configured by the statistical time interval register Automatically clear its count value after a register; and

The accumulation status register stores the count value of the status counter when the time value of the time counter is equal to the time interval configured by the statistical time interval register.

5. The system of claim 3, wherein the interrupt signal comprises a first interrupt signal and a second interrupt signal; and when the bandwidth utilization is lower than an actual required bandwidth utilization, the interrupt control The module generates a first interrupt signal indicating that the operating frequency of the DRAM needs to be reduced; when the accumulated value of the non-waiting operating state of the finite state machine exceeds the preset in the preset time interval When the condition threshold is turned off, a second interrupt signal indicating that the operating frequency of the DRAM needs to be increased is generated.

6. The system of claim 4, wherein the interrupt control module comprises: an interrupt condition threshold register, configured with a bandwidth utilization threshold;

The interrupt control logic module generates an interrupt signal according to the count value of the status counter and the bandwidth utilization threshold, or according to the count value of the accumulated status register.

7. The system according to claim 6, wherein the interrupt control logic module comprises: a first interrupt control unit, when the bandwidth utilization of the DRAM at the current operating frequency is low, generating an indication that the operating frequency of the DRAM needs to be reduced First interrupt signal; and

The second interrupt control unit generates a second interrupt signal indicating that the operating frequency of the DRAM needs to be increased when the bandwidth utilization of the DRAM at the current operating frequency is high.

8. The system of claim 7, wherein the parameter configuration module comprises a target operating frequency configuration sub-module, the target operating frequency configuration sub-module comprising:

a first configuration unit, configured to generate a target operating frequency lower than a current operating frequency of the DRAM according to the first interrupt signal; and

The second configuration unit generates a target operating frequency higher than a current operating frequency of the DRAM according to the second interrupt signal.

9. The system of claim 1 further comprising:

And a clock control module, configured to: when the frequency switching controller is in operation, control the DRAM to perform a refresh operation according to the internal clock, and, when the frequency switching controller completes the work, control the DRAM to perform a refresh operation according to the system clock.

10. The system of claim 9, wherein the system clock is determined by a timing check parameter, the system further comprising:

The timing check parameter validation module is configured to obtain a corresponding timing check parameter according to the target running frequency.

The system of claim 9 or 10, wherein the clock control module and the timing check parameter validation module are located in a DRAM controller of the DRAM.

12. The system of claim 1 further comprising a DRAM controller coupled to said frequency switching controller;

The parameter configuration module further includes: a frequency switching request signal configuration submodule, configured to configure a frequency switching request signal whose default value is invalid;

The handshake signal configuration submodule is configured to configure a handshake signal whose default value is invalid;

The timing check parameter configuration sub-module is configured to respectively configure corresponding timing check parameters for the DRAM operating frequency;

The frequency switching controller includes:

a frequency switching request generating module, configured to generate a frequency switching request, and set the frequency switching request signal to be valid;

a frequency switching module, configured to switch a current operating frequency of the DRAM to a target operating frequency according to a valid handshake signal; and

The invalid request signal setting module is configured to restore the frequency switching request signal to be invalid after the frequency switching module completes the frequency switching.

The system of claim 12, wherein the DRAM controller comprises: a self-refresh control module, configured to issue a first control command for the DRAM to refresh according to an internal clock according to the valid signal of the frequency switching request;

a handshake signal triggering module, configured to: after the first control command is issued, set the handshake signal to be valid;

a timing check parameter determining module, configured to extract a timing check parameter corresponding to the target operating frequency when the frequency switching request signal is restored to be invalid;

a self-refresh exit module, configured to determine a system clock according to the timing check parameter, and issue a second control command that the DRAM refreshes according to the system clock; and

The handshake signal closing module is configured to restore the handshake signal to be invalid after issuing the second control command.

14. The system of claim 13 wherein the DRAM controller further comprises:

The data request suspension module is configured to: after receiving the valid signal of the frequency switching request, execute the received data request before issuing the first control command, and stop responding to the new data request;

The data request execution module is configured to receive a new data request when the handshake signal is restored to be invalid.

15. A method for adjusting a DRAM operating frequency, comprising:

16. The method of claim 15 wherein the step of counting the effective operating state of the DRAM comprises:

Sub-step A1, accumulating the non-waiting operation state of the finite state machine of the DRAM in the preset time interval, and obtaining the effective working state of the DRAM;

Sub-step A2, determining, at the end of the preset time interval, the current bandwidth utilization of the DRAM according to the effective working state of the DRAM; when the current bandwidth utilization of the DRAM is low, generating the first need to reduce the operating frequency of the DRAM The interrupt signal; when the current bandwidth utilization of the DRAM exceeds the preset interrupt condition threshold within the preset time interval, generating a second interrupt signal that increases the operating frequency of the DRAM.

17. The method according to claim 16, wherein the generating step of the target operating frequency comprises:

Generating, according to the first interrupt signal, a target operating frequency lower than a current operating frequency of the DRAM when the first interrupt signal is generated; or generating a higher than current DRAM according to the second interrupt signal when the second interrupt signal is generated The target operating frequency of the running frequency.

18. The method of claim 15, further comprising:

The method of claim 18, wherein the system clock is determined by a timing check parameter, the method further comprising:

20. The method of claim 15, further comprising:

The preset default value is an invalid frequency switching request signal, and the default value is an invalid handshake signal, and a timing check parameter corresponding to various DRAM operating frequencies; Generating a frequency switching request, and setting the frequency switching request signal to be valid; and issuing a first control command for performing a refresh operation of the DRAM according to the internal clock according to the valid signal of the frequency switching request;

After the first control command is issued, the handshake signal is set to be valid;

Switching the current DRAM operating frequency to the target operating frequency according to the effective handshake signal; after completing the frequency switching, restoring the frequency switching request signal to be invalid;

When the frequency switching request signal is restored to be invalid, extracting a timing check parameter corresponding to the target operating frequency;

Determining a system clock according to the timing check parameter, and issuing a second control command for the DRAM to perform a refresh operation according to the system clock;

After the second control command is issued, the handshake signal is restored to be invalid.

The method according to claim 20, further comprising:

After receiving the valid signal of the frequency switching request, executing the received data request and issuing a response to the new data request before issuing the first control command;

22. The method of claim 18, wherein the statistical step of the effective operating state of the DRAM comprises:

Accumulating the non-waiting working state of the finite state machine in the DRAM controller within the preset time interval, and obtaining the effective working state of the DRAM;

And when the preset time interval arrives, generating a first middle or a lower limit of the operating frequency of the DRAM, wherein the accumulated value of the non-waiting working state of the finite state machine satisfies a preset interrupt condition threshold And generating a second interrupt signal that increases an operating frequency of the DRAM; and the generating step of the target operating frequency includes:

Generating a target operating frequency lower than a current DRAM operating frequency according to the first interrupt signal when the first interrupt signal is generated;

Alternatively, when the second interrupt signal is generated, a target operating frequency higher than a current DRAM operating frequency is generated according to the second interrupt signal.