CN103632708B - The self refresh control apparatus of synchronous DRAM and method - Google Patents
The self refresh control apparatus of synchronous DRAM and method Download PDFInfo
- Publication number
- CN103632708B CN103632708B CN201210311491.2A CN201210311491A CN103632708B CN 103632708 B CN103632708 B CN 103632708B CN 201210311491 A CN201210311491 A CN 201210311491A CN 103632708 B CN103632708 B CN 103632708B
- Authority
- CN
- China
- Prior art keywords
- synchronous dram
- frequency modulation
- controller
- frequency
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Dram (AREA)
Abstract
The self refresh control apparatus of a kind of synchronous DRAM disclosed by the invention and method, wherein method includes: synchronous DRAM frequency modulation control unit is received the control instruction that sent by bus of CPU and starts；The state of inquiry Real time capable module, after judging that frequency modulation control time inter-sync dynamic RAM allows all to be not responding to the read-write requests of all Real time capable modules, transmission pause instruction, to controller of synchronous dynamic random storage, controls described controller and suspends all to synchronous DRAM read-write requests；Send to update and instruct controller, make controller control synchronous DRAM and enter self-refresh mode；Transmission is transferred instruction and is arrived clock control cell, transfers target frequency frequency modulated information, and the clock signal of target frequency is sent to controller by clock control cell, and finally, the frequency modulation of synchronous DRAM is operated by controller.The method that the present invention provides can realize controlling synchronous DRAM self-refresh by hardware chip.
Description
Technical field
The present invention relates to semiconductor integrated circuit technical field, particularly relate to a kind of synchronous dynamic random storage
The self refresh control apparatus of device and method.
Background technology
The power consumption of digital circuit is divided into dynamic power consumption and quiescent dissipation, in special process and the situation of Circuits System
Under, dynamic power consumption is directly proportional to frequency, therefore typically reduces dynamic power consumption by reduction voltage and frequency.
In the prior art, the storage medium of mass storage generally uses synchronous dynamic random-access to store
Device (Synchronous Dynamic Random Access Memory, SDRAM), i.e. synchronous dynamic random
Access memorizer, the most also includes Double Data Rate synchronous DRAM (Double Data Rate
SDRAM, DDR SDRAM), it is at sdram memory that people's custom is referred to as DDR, DDR internal memory
On the basis of develop, still continue to use SDRAM production system, therefore for internal memory manufacturer, only
The equipment manufacturing common SDRAM need to be improved a little, the production of DDR internal memory can be realized.
The frequency of Synchronous Dynamic Random Access Memory is determined by the bandwidth demand of Circuits System, and Circuits System
Bandwidth demand therefore according to the bandwidth demand of system, can dynamically revise synchronization with application scenarios acute variation
The frequency of dynamic random access memory, it is possible to achieve reduce the purpose of power consumption in the case of meeting performance.
Under normal circumstances, Synchronous Dynamic Random Access Memory uses and automatically refreshes (Auto refresh) pattern,
This pattern needs controller timing to send refreshing instruction to SDRAM.In such a mode, SDRAM chip can
Carry out data access operation, but power consumption is bigger.But sdram controller also has another kind of refresh mode,
I.e. self-refresh (self refresh) pattern, this pattern need not outside instruction, SDRAM core are periodically flushed
Sheet oneself will produce refresh pulse internal, and in such a mode, the power consumption of SDRAM chip refreshes the most automatically
Pattern greatly reduces, but simultaneously SDRAM chip will be unable to make an immediate response the accessing operation of data, is only capable of
Available data is enough kept not lose.According to joint electron device engineering council (Joint Electron Device
Engineering Council, JEDEC) relevant criterion formulated, only Synchronous Dynamic Random Access Memory
It is under self-refresh mode, the adjustment of frequency can be carried out.But, during frequency adjusts, necessarily cause
Synchronous Dynamic Random Access Memory cannot normally access within a period of time.
In prior art, when the self-refresh realizing synchronous DRAM controls, it is all to pass through software
Be controlled and frequency modulation instruction transmission and data transmission, often there is a lot of technological deficiency in this method；Its
In, the problem of major embodiment three aspect.One, CPU is when processing frequency modulation program, owing to software controls from brush
New control process occupies the substantial amounts of frequency modulation control time, and the SDRAM of off-chip can not be accessed again simultaneously,
So CPU will read RAM or Cache in sheet when processing frequency modulation programmed instruction, but so
Cpu performance will be greatly reduced.Two, use software frequency modulation time, CPU may outage program, this
Time off-chip SDRAM can not be accessed, so CPU by wait interrupt instruction reading, due to software control
Self-refresh processed controls process and occupies the substantial amounts of frequency modulation control time, and SDRAM also needs to waiting for CPU simultaneously
The frequency modulation instruction sent, is so easy to system mistake.Three, when using software self-refresh frequency modulation, because
Software controls self-refresh and controls process and occupy the substantial amounts of frequency modulation control time, and the SDRAM of off-chip can not be by
Accessing, in software control system, multiple Real time capable modules need substantial amounts of buffer register (Buffer), and this will increase
Add more cost.
In a word, this method makes systematic function greatly reduce, simultaneously software control to need to grow very much time
Between frequency modulation removal control and response, this will badly influence the performance of synchronous DRAM, also be easy to
Cause system mistake；It addition, use software to control all processes of self-refresh, it has to use more
Buffer register, this will occupy substantial amounts of CPU and use resource, reduce the memory system speed of service and too increase
Production cost.
Therefore, in prior art, how to overcome in prior art and lacked by the technology of software control self refresh operation
Fall into and realize the self-refresh of synchronous DRAM more at high speed and control to be the most scabrous individual problem.
Summary of the invention
Based on the problems referred to above, the invention provides self-refresh control method and the dress of synchronous DRAM
Putting, the self-refresh being realized synchronous DRAM by hardware chip device at high speed controls operation,
Thus overcome the technological deficiency being controlled self refresh operation in prior art by software.
The invention provides the self refresh control apparatus of a kind of synchronous DRAM, including main control list
Unit and synchronous DRAM, described main control unit includes clock control cell, one or more reality
Time module, synchronous DRAM frequency modulation control unit and controller of synchronous dynamic random storage；Institute
State synchronous DRAM frequency modulation control unit respectively with described clock control cell, described Real time capable module
Electrically connect with described controller of synchronous dynamic random storage；Described controller of synchronous dynamic random storage with
Synchronous DRAM is connected by external interface；
Described clock control cell includes clock generator, wherein:
Described clock generator, for, after receiving frequency modulation instruction, producing the synchronous dynamic random of target frequency
Memory clock signal, and it is sent to controller of synchronous dynamic random storage；
Described Real time capable module, for carrying out data interaction with synchronous DRAM；
Described synchronous DRAM frequency modulation control unit includes receiver module, enquiry module, time-out mould
Block, more new module and FM module, wherein:
Described receiver module, after receiving control instruction that CPU sends by bus and performing to start execution
Continuous operation；
Described enquiry module, for inquiring about the state judging all Real time capable modules, and when judging frequency modulation control
Between after inter-sync dynamic RAM allows all to be not responding to the read-write requests of all Real time capable modules, jump to
Described time-out module performs corresponding operating；
Described time-out module, is used for sending pause instruction to controller of synchronous dynamic random storage, control with
Step dynamic RAM controller suspends all to synchronous DRAM read-write requests；
Described more new module, is used for sending renewal instruction and arrives controller of synchronous dynamic random storage, make synchronization
Dynamic RAM controller controls synchronous DRAM and enters self-refresh mode；
Described FM module, transfers instruction for transmission and arrives clock control cell, transfer in clock control cell
Target frequency frequency modulated information, the clock signal of target frequency is sent to synchronous dynamic random by clock control cell
Memory Controller, described controller of synchronous dynamic random storage controls synchronous DRAM and starts
Frequency modulation operates；
Described controller of synchronous dynamic random storage, for directly adjusting synchronous DRAM
Frequency operation.
It is preferred that as a kind of embodiment.Described clock control cell also includes the first buffer register,
First sends subelement, the second buffer register, and second sends subelement, wherein:
Described first buffer register, for receiving, at clock control cell, the target that CPU is sent by bus
After frequency frequency modulated information, preserve target frequency frequency modulated information；
Described first sends subelement, for when frequency modulation, by the first buffer register internal object frequency frequency modulation
Information is sent in described second buffer register；
Described second buffer register, for before non-frequency modulation, keeps former clock frequency control synchronous dynamic
The frequency of random access memory；
Described second sends subelement, for when frequency modulation, receives the target frequency from the first buffer register
After rate frequency modulated information, frequency modulation instruction is sent to described clock generator.
It is preferred that as a kind of embodiment.Described FM module includes transferring submodule, wherein:
Described transfer submodule, transfer instruction for transmission and start to clock control cell, clock control cell
Presetting extract operation.
It is preferred that as a kind of embodiment.Described controller of synchronous dynamic random storage also includes moving back
Go out module, recover module and terminate module, wherein:
Described exit module, after terminating in frequency modulation operation, send exit instruction and deposit to synchronous dynamic random
Memory controller, makes controller of synchronous dynamic random storage control synchronous DRAM and exits from brush
New state；
Described recovery module, is used for sending recovery instruction and arrives controller of synchronous dynamic random storage, control same
Step dynamic RAM controller recovers all and responds synchronous DRAM read-write requests；
Described end module, controls operation for terminating the self-refresh of synchronous DRAM.
It is preferred that as a kind of embodiment.The plurality of Real time capable module also includes the multiple 3rd of correspondence
Buffer register；Described Real time capable module and the 3rd buffer register one_to_one corresponding；
The plurality of 3rd buffer register, within the frequency modulation control time, is carried out with multiple Real time capable modules
Reading and writing data.
It is preferred that as a kind of embodiment.Described enquiry module includes judging submodule and returning submodule
Block, wherein:
Described judgement submodule, be used for judging whether all of Real time capable module within the frequency modulation control time to its institute
The data volume of the 3rd corresponding buffer register pre-read is both less than the data that the 3rd buffer register is stored
Amount；Or the 3rd buffer register that the most all of Real time capable module is corresponding to it within the frequency modulation control time
The data volume of pre-write is both less than the 3rd buffer register residual memory space；The most then redirect described time-out
Module performs corresponding operating；If it is not, then redirect return submodule to perform corresponding operation；
Described return submodule, is used for returning described judgement submodule and performing corresponding operating in next sequential.
Accordingly, as a kind of embodiment.Present invention also offers a kind of synchronous DRAM
Self-refresh control method, described method comprises the steps:
Step A, synchronous DRAM frequency modulation control unit receive the control that CPU is sent by bus
Instruct and perform to start subsequent operation；
The inquiry of step B, synchronous DRAM frequency modulation control unit judges the state of all Real time capable modules,
And judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules all
Step C is performed after being not responding to；
Step C, synchronous DRAM frequency modulation control unit send pause instruction and deposit to synchronous dynamic random
Memory controller, controls controller of synchronous dynamic random storage and suspends all to synchronous DRAM
Read-write requests；
Step D, synchronous DRAM frequency modulation control unit send and update instruction to synchronous dynamic random
Memory Controller, makes controller of synchronous dynamic random storage control synchronous DRAM and enters certainly
Refresh mode；
Step E, synchronous DRAM frequency modulation control unit send to transfer and instruct clock control cell,
Transferring clock control cell internal object frequency frequency modulated information, clock control cell is by the clock signal of target frequency
Being sent to controller of synchronous dynamic random storage, described controller of synchronous dynamic random storage controls to synchronize
Dynamic RAM carries out frequency modulation operation.
It is preferred that as a kind of embodiment.Described step A comprises the steps:
Step a1, clock control cell receive the target frequency frequency modulated information that CPU is sent by bus, preserve
In the first buffer register in clock control cell；
Step a2, described second buffer register keep former clock frequency control synchronous DRAM
Frequency.
It is preferred that as a kind of embodiment.Described step E specifically includes following steps:
Step e1, synchronous DRAM frequency modulation control unit send to transfer and instruct clock control cell,
Clock control cell starts presetting extract operation；
Step e2, presetting extract operation start after, described first send subelement by target frequency frequency modulated information
It is sent in described second buffer register；Described second sends subelement receives from the first buffer register
Target frequency frequency modulated information after frequency modulation instruction is sent to described clock generator；
Step e3, described clock generator, after receiving frequency modulation instruction, produce the clock signal of target frequency,
And it being sent to controller of synchronous dynamic random storage, described controller of synchronous dynamic random storage controls same
Step dynamic RAM carries out frequency modulation operation.
It is preferred that as a kind of embodiment.Also include after described step E that following steps is rapid:
Step F, frequency modulation operation terminate after, synchronous DRAM frequency modulation control unit send exit finger
Order, to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous dynamic
Random access memory exits self-refresh state；
Step G, synchronous DRAM frequency modulation control unit send and recover instruction to synchronous dynamic random
Memory Controller, controls controller of synchronous dynamic random storage and recovers all to synchronous dynamic random storage
Device read-write requests responds；
Step H, the self-refresh of end synchronous DRAM control operation.
It is preferred that as a kind of embodiment.Within the frequency modulated clock cycle, the plurality of Real time capable module with
Its corresponding multiple 3rd buffer registers carry out reading and writing data.
It is preferred that as a kind of embodiment.In described step B, the storage of described synchronous dynamic random
The concrete operation step of the state of the device frequency modulation control unit inquiry all Real time capable modules of judgement:
Step b1, judge whether that it the corresponding 3rd was delayed within the frequency modulation control time by all of Real time capable module
The data volume rushing depositor pre-read is both less than the data volume that the 3rd buffer register is stored；Or whether institute
The data volume of the 3rd buffer register pre-write that some Real time capable modules are corresponding to it within the frequency modulation control time
Both less than the 3rd buffer register residual memory space；
Step b2, the most then judge that the permission of frequency modulation control time inter-sync dynamic RAM is all in real time
The read-write requests of module is all not responding to；If it is not, return step b1 and wait that next sequential carries out performing judgement again
Operation.
The beneficial effect comprise that
The self refresh control apparatus of a kind of synchronous DRAM that the present invention provides and method, Qi Zhongfang
Method comprises the following steps: synchronous DRAM frequency modulation control unit receives what CPU was sent by bus
Control instruction also performs to start operation；Inquiry judges the state of all Real time capable modules, it is determined that the frequency modulation control time
After inter-sync dynamic RAM allows all to be not responding to the read-write requests of all Real time capable modules, send and suspend
Instruction, to controller of synchronous dynamic random storage, controls described controller and suspends all to synchronous dynamic random
Memory read/write is asked；Send to update and instruct controller, make controller control synchronous DRAM
Enter self-refresh mode；Transmission is transferred instruction and is arrived clock control cell, transfers clock control cell internal object frequency
Rate frequency modulated information, the clock signal of target frequency is sent to controller by clock control cell, finally, controls
Device realizes the frequency modulation to synchronous DRAM and operates.The method that the present invention provides can pass through hardware chip
Realize synchronous DRAM self-refresh is controlled.
The self refresh control apparatus of the synchronous DRAM that the present invention provides, all control operations
Association's reconciliation process all Hardwares, reach prestissimo and complete frequency modulation, it is not necessary to software intervention frequency-modulating process.Examine
Consider in frequency-modulating process, be synchronous DRAM cannot to be carried out data read-write operation, therefore subtract
Few whole frequency modulation control time, beneficially improving performance.
Accompanying drawing explanation
Fig. 1 is the structure of self refresh control apparatus one specific embodiment of synchronous DRAM of the present invention
Schematic diagram；
Fig. 2 is the flow process of self-refresh control method one specific embodiment of synchronous DRAM of the present invention
Schematic diagram.
Detailed description of the invention
Below in conjunction with Figure of description, to the self refresh control apparatus of synchronous DRAM of the present invention and
The detailed description of the invention of method illustrates.
Embodiments provide the self refresh control apparatus of a kind of synchronous DRAM, such as Fig. 1
Shown in, including main control unit 10 and synchronous DRAM 20, described main control unit 10 includes
Clock control cell 101, also include Real time capable module 102, synchronous DRAM frequency modulation control unit 103
With controller of synchronous dynamic random storage 104；Described clock control cell 101 includes clock generator
1011, described synchronous DRAM frequency modulation control unit 103 respectively with described clock control cell 101,
Described Real time capable module 102 and described controller of synchronous dynamic random storage 104 electrically connect；Described synchronization is moved
State ram controller 104 is connected by external interface with synchronous DRAM 20；Described reality
Time module can be one or more, wherein:
Described clock control cell 101 includes clock generator 1011, wherein:
Described clock generator 1011, for, after receiving frequency modulation instruction, producing the synchronous dynamic of target frequency
Random access memory clock signal, and it is sent to controller of synchronous dynamic random storage；
Described Real time capable module 102, for carrying out data interaction with synchronous DRAM；
Described synchronous DRAM frequency modulation control unit 103 includes receiver module 1031, enquiry module
1032, module 1033, more new module 1034 and FM module 1035 are suspended, wherein:
Described receiver module 1031, for receiving control instruction that CPU sent by bus and performing startup and hold
Row subsequent operation；
Described enquiry module 1032, for inquiring about the state judging all Real time capable modules, and is judging frequency modulation control
After time inter-sync dynamic RAM processed allows all to be not responding to the read-write requests of all Real time capable modules, jump
Forward described time-out module to and perform corresponding operating；
Described time-out module 1033, is used for sending pause instruction to controller of synchronous dynamic random storage, control
Controller of synchronous dynamic random storage processed suspends all to synchronous DRAM read-write requests；
Described more new module 1034, is used for sending renewal instruction and arrives controller of synchronous dynamic random storage, make
Controller of synchronous dynamic random storage controls synchronous DRAM and enters self-refresh mode；
Described FM module 1035, transfers instruction for transmission and arrives clock control cell, transfer clock control list
Unit's internal object frequency frequency modulated information, the clock signal of target frequency is sent to synchronous dynamic by clock control cell
Ram controller, described controller of synchronous dynamic random storage controls synchronous DRAM
Start frequency modulation operation；
Described controller of synchronous dynamic random storage 104, for directly carrying out synchronous DRAM
Frequency modulation operates.
In embodiments of the present invention, self refresh control apparatus includes main control unit and off-chip SDRAM, described
Synchronous DRAM frequency modulation control unit respectively with described clock control cell, described Real time capable module and
Described controller of synchronous dynamic random storage electrically connects；Described synchronous DRAM frequency modulation control list
Unit directly controls controller of synchronous dynamic random storage, and controller of synchronous dynamic random storage is for directly
Control off-chip SDRAM.
It is preferred that as a kind of embodiment.
Described clock control cell 101 also includes the first buffer register 1012, and first sends subelement 1013,
Second buffer register 1014, second sends subelement 1015, wherein:
Described first buffer register 1012, for receiving what CPU was sent by bus at clock control cell
After target frequency frequency modulated information, preserve target frequency frequency modulated information；
Described first sends subelement 1013, for when frequency modulation, by the first buffer register internal object frequency
Frequency modulated information is sent in described second buffer register；
Described second buffer register 1014, for before non-frequency modulation, keeps former clock frequency control to synchronize
The frequency of dynamic RAM；
Described second sends subelement 1015, for when frequency modulation, receives the mesh from the first buffer register
After mark frequency frequency modulated information, frequency modulation instruction is sent to described clock generator.
It is preferred that as a kind of embodiment.Described FM module 1035 specifically includes transfers submodule,
Wherein:
Described transfer submodule, transfer instruction for transmission and start to clock control cell, clock control cell
Presetting extract operation.
First, (now do not start to perform frequency modulation operation) when self-refresh controls initial, in clock control cell
The first buffer register receive the target frequency frequency modulated information that sent by bus of CPU and preserve；Meanwhile,
The receiver module of synchronous DRAM frequency modulation control unit, receives the control that CPU is sent by bus
Instruct and perform to start and prepare operation.At this moment self-refresh device is in frequency modulation incubation period, needs through pre-place
Reason process, could perform frequency modulation control operation.
Described preprocessing process includes: inquiry judges the state of all Real time capable modules；Described time-out module, sends out
Send pause instruction to arrive controller of synchronous dynamic random storage, control controller of synchronous dynamic random storage temporary
Stop all to the response of synchronous DRAM read-write requests；Described more new module, send update instruction to
Controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous dynamic random
Memorizer enters self-refresh mode.After process to be pre-treated terminates, at this moment ensure that self refresh control apparatus exists
When being under self-refresh mode, the interference that the SDRAM of off-chip will not be read and write.Meanwhile, each in real time
Module has all been correspondingly arranged Buffer(the 3rd buffer register of a reasonable memory space), so protecting
When barrier self refresh control apparatus processes self-refresh mode, the data in sheet normally read and write, it is to avoid loss of data,
Both reduce the power consumption of system, the most do not affect normal reading and writing data.
Then, self refresh control apparatus perform frequency modulation operation time, described in transfer submodule, first send transfer
Instruction starts presetting extract operation to clock control cell, clock control cell.After presetting extract operation starts,
Because the target frequency frequency modulated information that CPU sends is in the first buffer register, described first sends subelement
Target frequency frequency modulated information in first buffer register is sent in described second buffer register；Described
Second sends subelement receives frequency modulation instruction after the target frequency frequency modulated information of the first buffer register
Deliver to described clock generator；Described clock generator can according to the transmission of the change target frequency set more
The clock frequency changed.Target frequency clock signal is sent to synchronous DRAM control by clock generator
Device processed, described controller of synchronous dynamic random storage is directly realized by the operation of the frequency modulation to off-chip SDRAM.
Described clock signal include clock enable signal (CKE), row address signal (Row Address Strobe,
RAS), column address signal (Column Address Strobe, CAS) etc., and by said external interface
Transmission.
Clock generator only needs technical staff's direct compilation program.Input and output clock frequency can be completed
Set.Sdram controller exports the corresponding signal phase of control signal and SDRAM chip granule
Connect, it is achieved for the logic control of SDRAM chip granule.
It is preferred that as a kind of embodiment.Described synchronous DRAM unit 103 also includes
Exit module 1036, recover module 1037 and terminate module 1038, wherein:
Described exit module 1036, after terminating in frequency modulation operation, send exit instruction to synchronous dynamic with
Machine Memory Controller, makes controller of synchronous dynamic random storage control synchronous DRAM and exits
Self-refresh state；
Described recovery module 1037, is used for sending recovery instruction to controller of synchronous dynamic random storage, control
Controller of synchronous dynamic random storage processed recovers all and responds synchronous DRAM read-write requests；
Described end module 1038, controls operation for terminating the self-refresh of synchronous DRAM.
Finally, after frequency modulation operation terminates, self-refresh device needs enter recovery process and terminate self-refresh control
System operation.
It is preferred that as a kind of embodiment.The plurality of Real time capable module also includes the multiple 3rd of correspondence
Buffer register；Described Real time capable module and the 3rd buffer register one_to_one corresponding；Described each Real time capable module 102
Also include a 3rd corresponding buffer register 1021, wherein:
The plurality of 3rd buffer register 1021, within the frequency modulation control time, with multiple Real time capable modules
102 carry out reading and writing data.
It is preferred that as a kind of embodiment.Described enquiry module includes judging submodule and returning submodule
Block, wherein:
Described judgement submodule, be used for judging whether all of Real time capable module within the frequency modulation control time to its institute
The data volume of the 3rd corresponding buffer register pre-read is both less than the data that the 3rd buffer register is stored
Amount；Or the 3rd buffer register that the most all of Real time capable module is corresponding to it within the frequency modulation control time
The data volume of pre-write is both less than the 3rd buffer register residual memory space；The most then redirect described time-out
Module performs corresponding operating；If it is not, then redirect return submodule to perform corresponding operation；
Described return submodule, is used for returning described judgement submodule and performing corresponding operating in next sequential.
Described judgement submodule, for judging the state of Real time capable module, illustrates, enters with certain Real time capable module
As a example by row data write the 3rd buffer register, the frequency modulation control time is that T(hardware chip calculates at the beginning of design
Obtain), the 3rd buffer register memory space that integrates sufficiently large (hardware chip at the beginning of design
Configure), when at this moment certain Real time capable module carries out data pre-write, described judgement submodule needs to judge this
Whether the data volume of Real time capable module pre-write is less than the 3rd buffer register (the transmission speed of the 3rd buffer register
Rate is V) residual memory space (M).Calculate the value of V × T whether less than residual memory space M, and
After all Real time capable modules all meet V × T M, just judging to meet all Real time capable modules can be in synchronous dynamic
The condition of reading and writing data is not carried out in the random access memory frequency modulation control time.Described judgement Real time capable module pre-read
Operating similar with above-mentioned pre-write, this is repeated by the embodiment of the present invention the most one by one.
It will be understood by those skilled in the art that the synchronous dynamic random storage that the embodiment of the present invention is provided
The self refresh control apparatus of device is because significantly reducing the frequency modulation control time, it is possible to overcome institute in prior art
Insoluble three problems.One, in embodiments of the present invention, when performing frequency modulation operation by hardware chip
Realize the control to synchronous DRAM, so CPU will not be used to process frequency modulation program, so will
Ensure cpu performance.Two, same, in embodiments of the present invention, CPU may outage program, this
Time off-chip SDRAM can not be accessed, CPU will wait interrupt instruction reading, but without waiting for very
The long frequency modulation control time, after self-refresh controls to terminate, CPU will quickly can read from the SDRAM of off-chip
Take interrupt instruction.Three, same, in embodiments of the present invention, because hardware chip controls self-refresh and controlled
Journey occupies the minimal amount of frequency modulation control time, although the SDRAM of off-chip can not be accessed, but self-refresh
Control multiple Real time capable modules in device, without substantial amounts of buffer register (Buffer), just can ensure in real time
The reading and writing data of module.
As a kind of embodiment, the embodiment of the present invention not only protects Synchronous Dynamic Random Access Memory
Self-refresh controls process, is applied equally to the modified version DDR SDRAM of SDRAM, therefore simultaneously
For internal memory manufacturer, only the synchronous DRAM self-refresh of the embodiment of the present invention need to be controlled dress
Putting and improve a little, the production that can realize Double Data Rate synchronous DRAM self refresh control apparatus sets
Meter is implemented.
The self refresh control apparatus of the synchronous DRAM that embodiments of the invention are provided can be by meter
Calculation machine program realizes.Those skilled in the art are it should be appreciated that described Module Division mode is only numerous
One in Module Division, if being divided into other modules or not dividing module, as long as device has above-mentioned
Function, all should be within the protection domain of the application.
Based on same inventive concept, the embodiment of the present invention additionally provides oneself of a kind of synchronous DRAM
Refresh control method, owing to the method solves the principle of problem and aforementioned a kind of synchronous DRAM
The various functions of self refresh control apparatus is similar, and therefore, the enforcement of the method can be concrete by aforementioned means
Functional realiey, repeats no more in place of repetition.
Accordingly, as a kind of embodiment.The synchronous DRAM that the embodiment of the present invention provides
Self-refresh control method, as in figure 2 it is shown, described method comprises the steps:
Step A, synchronous DRAM frequency modulation control unit receive the control that CPU is sent by bus
Instruct and perform to start subsequent operation；
The inquiry of step B, synchronous DRAM frequency modulation control unit judges the state of all Real time capable modules,
And judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules all
Step C is performed after being not responding to；
Step C, synchronous DRAM frequency modulation control unit send pause instruction and deposit to synchronous dynamic random
Memory controller, controls controller of synchronous dynamic random storage and suspends all to synchronous DRAM
Read-write requests；
Step D, synchronous DRAM frequency modulation control unit send and update instruction to synchronous dynamic random
Memory Controller, makes controller of synchronous dynamic random storage control synchronous DRAM and enters certainly
Refresh mode；
Step E, synchronous DRAM frequency modulation control unit send to transfer and instruct clock control cell,
Transferring clock control cell internal object frequency frequency modulated information, clock control cell is by the clock signal of target frequency
Being sent to controller of synchronous dynamic random storage, described controller of synchronous dynamic random storage controls to synchronize
Dynamic RAM carries out frequency modulation operation.
It is preferred that as a kind of embodiment.Described step A comprises the steps:
Step a1, clock control cell receive the target frequency frequency modulated information that CPU is sent by bus, preserve
In the first buffer register in clock control cell；
Step a2, described second buffer register keep former clock frequency control synchronous DRAM
Frequency.
It is preferred that as a kind of embodiment.Described step E specifically includes following steps:
Step e1, synchronous DRAM frequency modulation control unit send to transfer and instruct clock control cell,
Clock control cell starts presetting extract operation；
Step e2, presetting extract operation start after, described first send subelement by target frequency frequency modulated information
It is sent in described second buffer register；Described second sends subelement receives from the first buffer register
Target frequency frequency modulated information after frequency modulation instruction is sent to described clock generator；
Step e3, described clock generator, after receiving frequency modulation instruction, produce the clock signal of target frequency,
And it being sent to controller of synchronous dynamic random storage, described controller of synchronous dynamic random storage controls same
Step dynamic RAM carries out frequency modulation operation.
It is preferred that as a kind of embodiment.Also include after described step E that following steps is rapid:
Step F, frequency modulation operation terminate after, synchronous DRAM frequency modulation control unit send exit finger
Order, to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous dynamic
Random access memory exits self-refresh state；
Step G, synchronous DRAM frequency modulation control unit send and recover instruction to synchronous dynamic random
Memory Controller, controls controller of synchronous dynamic random storage and recovers all to synchronous dynamic random storage
Device read-write requests responds；
Step H, the self-refresh of end synchronous DRAM control operation.
It is preferred that as a kind of embodiment.Within the frequency modulated clock cycle, the plurality of Real time capable module with
Its corresponding multiple 3rd buffer registers carry out reading and writing data.
It is preferred that as a kind of embodiment.In described step B, the storage of described synchronous dynamic random
The concrete operation step of the state of the device frequency modulation control unit inquiry all Real time capable modules of judgement:
Step b1, judge whether that it the corresponding 3rd was delayed within the frequency modulation control time by all of Real time capable module
The data volume rushing depositor pre-read is both less than the data volume that the 3rd buffer register is stored；Or whether institute
The data volume of the 3rd buffer register pre-write that some Real time capable modules are corresponding to it within the frequency modulation control time
Both less than the 3rd buffer register residual memory space；
Step b2, the most then judge that the permission of frequency modulation control time inter-sync dynamic RAM is all in real time
The read-write requests of module is all not responding to；If it is not, return step b1 and wait that next sequential carries out performing judgement again
Operation.
The self refresh control apparatus of a kind of synchronous DRAM that the embodiment of the present invention provides and method,
Wherein method comprises the following steps: synchronous DRAM frequency modulation control unit receives CPU and passes through bus
Send control instruction and perform start operation；Inquiry judges the state of all Real time capable modules, it is determined that frequency modulation control
After time inter-sync dynamic RAM processed allows all to be not responding to the read-write requests of all Real time capable modules, send out
Send pause instruction to arrive controller of synchronous dynamic random storage, control described controller and suspend all dynamic to synchronizing
State random access memory read-write requests；Send to update and instruct controller, make controller control synchronous dynamic random
Memorizer enters self-refresh mode；Transmission is transferred instruction and is arrived clock control cell, transfers in clock control cell
Target frequency frequency modulated information, the clock signal of target frequency is sent to controller by clock control cell, finally,
Controller realizes the frequency modulation to synchronous DRAM and operates.The method that the embodiment of the present invention provides can be led to
Cross hardware chip to realize synchronous DRAM self-refresh is controlled.
The self refresh control apparatus of the synchronous DRAM that the embodiment of the present invention provides, all controls
Association's reconciliation process all Hardwares of operation, reach prestissimo and complete frequency modulation, it is not necessary to software intervention frequency modulation mistake
Journey.In view of in frequency-modulating process, it is synchronous DRAM cannot to be carried out data read-write operation,
Therefore reduce the whole frequency modulation control time, be conducive to promoting the performance of memory system.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed,
But therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for this area
Those of ordinary skill for, without departing from the inventive concept of the premise, it is also possible to make some deformation and
Improving, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended
Claim is as the criterion.
Claims (12)
1. the self refresh control apparatus of a synchronous DRAM, it is characterised in that include main control
Unit and synchronous DRAM, described main control unit includes clock control cell, one or more
Real time capable module, synchronous DRAM frequency modulation control unit and controller of synchronous dynamic random storage；
Described synchronous DRAM frequency modulation control unit respectively with described clock control cell, described real-time mould
Block and the electrical connection of described controller of synchronous dynamic random storage；Described controller of synchronous dynamic random storage
It is connected by external interface with synchronous DRAM；
Described clock control cell includes clock generator, wherein:
Described clock generator, for, after receiving frequency modulation instruction, producing the synchronous dynamic random of target frequency
Memory clock signal, and it is sent to controller of synchronous dynamic random storage；
Described Real time capable module, for carrying out data interaction with synchronous DRAM；
Described synchronous DRAM frequency modulation control unit includes receiver module, enquiry module, time-out mould
Block, more new module and FM module, wherein:
Described receiver module, after receiving control instruction that CPU sends by bus and performing to start execution
Continuous operation；
Described enquiry module, for inquiring about the state judging all Real time capable modules, and when judging frequency modulation control
Between after inter-sync dynamic RAM allows all to be not responding to the read-write requests of all Real time capable modules, jump to
Described time-out module performs corresponding operating；
Described time-out module, is used for sending pause instruction to controller of synchronous dynamic random storage, control with
Step dynamic RAM controller suspends all to synchronous DRAM read-write requests；
Described more new module, is used for sending renewal instruction and arrives controller of synchronous dynamic random storage, make synchronization
Dynamic RAM controller controls synchronous DRAM and enters self-refresh mode；
Described FM module, transfers instruction for transmission and arrives clock control cell, transfer in clock control cell
Target frequency frequency modulated information, the clock signal of target frequency is sent to synchronous dynamic random by clock control cell
Memory Controller, described controller of synchronous dynamic random storage controls synchronous DRAM and starts
Frequency modulation operates；
Described controller of synchronous dynamic random storage, for directly adjusting synchronous DRAM
Frequency operation.
The self refresh control apparatus of synchronous DRAM the most according to claim 1, its feature
Being, described clock control cell also includes the first buffer register, and first sends subelement, the second buffering
Depositor, second sends subelement, wherein:
Described first buffer register, for receiving, at clock control cell, the target that CPU is sent by bus
After frequency frequency modulated information, preserve target frequency frequency modulated information；
Described first sends subelement, for when frequency modulation, by the first buffer register internal object frequency frequency modulation
Information is sent in described second buffer register；
Described second buffer register, for before non-frequency modulation, keeps former clock frequency control synchronous dynamic
The frequency of random access memory；
Described second sends subelement, for when frequency modulation, receives the target frequency from the first buffer register
After rate frequency modulated information, frequency modulation instruction is sent to described clock generator.
The self refresh control apparatus of synchronous DRAM the most according to claim 1 and 2, its
Being characterised by, described FM module includes transferring submodule, wherein:
Described transfer submodule, transfer instruction for transmission and start to clock control cell, clock control cell
Presetting extract operation.
The self refresh control apparatus of synchronous DRAM the most according to claim 1, its feature
Being, described controller of synchronous dynamic random storage also includes exiting module, recovering module and terminate module,
Wherein:
Described exit module, after terminating in frequency modulation operation, send exit instruction and deposit to synchronous dynamic random
Memory controller, makes controller of synchronous dynamic random storage control synchronous DRAM and exits from brush
New state；
Described recovery module, is used for sending recovery instruction and arrives controller of synchronous dynamic random storage, control same
Step dynamic RAM controller recovers all and responds synchronous DRAM read-write requests；
Described end module, controls operation for terminating the self-refresh of synchronous DRAM.
The self refresh control apparatus of synchronous DRAM the most according to claim 1, its feature
Being, the plurality of Real time capable module also includes multiple 3rd buffer registers of correspondence；Described Real time capable module with
3rd buffer register one_to_one corresponding；
The plurality of 3rd buffer register, within the frequency modulation control time, is carried out with multiple Real time capable modules
Reading and writing data.
The self refresh control apparatus of synchronous DRAM the most according to claim 1 or 5, its
Being characterised by, described enquiry module includes judging submodule and returning submodule, wherein:
Described judgement submodule, be used for judging whether all of Real time capable module within the frequency modulation control time to its institute
The data volume of the 3rd corresponding buffer register pre-read is both less than the data that the 3rd buffer register is stored
Amount；Or the 3rd buffer register that the most all of Real time capable module is corresponding to it within the frequency modulation control time
The data volume of pre-write is both less than the 3rd buffer register residual memory space；The most then redirect described time-out
Module performs corresponding operating；If it is not, then redirect return submodule to perform corresponding operation；
Described return submodule, is used for returning described judgement submodule and performing corresponding operating in next sequential.
7. the self-refresh control method of a synchronous DRAM, it is characterised in that include walking as follows
Rapid:
Step A, synchronous DRAM frequency modulation control unit receive the control that CPU is sent by bus
Instruct and perform to start subsequent operation；
The inquiry of step B, synchronous DRAM frequency modulation control unit judges the state of all Real time capable modules,
And judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules all
Step C is performed after being not responding to；
Step C, synchronous DRAM frequency modulation control unit send pause instruction and deposit to synchronous dynamic random
Memory controller, controls controller of synchronous dynamic random storage and suspends all to synchronous DRAM
Read-write requests；
Step D, synchronous DRAM frequency modulation control unit send and update instruction to synchronous dynamic random
Memory Controller, makes controller of synchronous dynamic random storage control synchronous DRAM and enters certainly
Refresh mode；
Step E, synchronous DRAM frequency modulation control unit send to transfer and instruct clock control cell,
Transferring clock control cell internal object frequency frequency modulated information, clock control cell is by the clock signal of target frequency
Being sent to controller of synchronous dynamic random storage, described controller of synchronous dynamic random storage controls to synchronize
Dynamic RAM carries out frequency modulation operation.
The self-refresh control method of synchronous DRAM the most according to claim 7, its feature
Being, described step A comprises the steps:
Step a1, clock control cell receive the target frequency frequency modulated information that CPU is sent by bus, preserve
In the first buffer register in clock control cell；
The second buffer register in step a2, described clock control cell keeps former clock frequency control to synchronize
The frequency of dynamic RAM.
9. according to the self-refresh control method of the synchronous DRAM described in claim 7 or 8, its
Being characterised by, described step E specifically includes following steps:
Step e1, synchronous DRAM frequency modulation control unit send to transfer and instruct clock control cell,
Clock control cell starts presetting extract operation；
Step e2, presetting extract operation start after, in described clock control cell first transmission subelement will
Target frequency frequency modulated information is sent in the second buffer register in described clock control cell；Described clock
The second transmission subelement in control unit receives after the target frequency frequency modulated information of the first buffer register
Frequency modulation instruction is sent to described clock generator；
Step e3, described clock generator, after receiving frequency modulation instruction, produce the clock signal of target frequency,
And it being sent to controller of synchronous dynamic random storage, described controller of synchronous dynamic random storage controls same
Step dynamic RAM carries out frequency modulation operation.
The self-refresh control method of synchronous DRAM the most according to claim 7, it is special
Levy and be, after described step E, also include that following steps is rapid:
Step F, frequency modulation operation terminate after, synchronous DRAM frequency modulation control unit send exit finger
Order, to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous dynamic
Random access memory exits self-refresh state；
Step G, synchronous DRAM frequency modulation control unit send and recover instruction to synchronous dynamic random
Memory Controller, controls controller of synchronous dynamic random storage and recovers all to synchronous dynamic random storage
Device read-write requests responds；
Step H, the self-refresh of end synchronous DRAM control operation.
The self-refresh control method of 11. synchronous DRAMs according to claim 7, it is special
Levy and be, within the frequency modulation control time, also comprise the steps:
Multiple described Real time capable modules carry out reading and writing data to multiple 3rd buffer registers corresponding thereto.
12. according to the self-refresh control method of the synchronous DRAM described in claim 7 or 11,
It is characterized in that, in described step B, the inquiry of described synchronous DRAM frequency modulation control unit is sentenced
The state of fixed all Real time capable modules, comprises the steps:
Step b1, judge whether that it the corresponding 3rd was delayed within the frequency modulation control time by all of Real time capable module
The data volume rushing depositor pre-read is both less than the data volume that the 3rd buffer register is stored；Or whether institute
The data volume of the 3rd buffer register pre-write that some Real time capable modules are corresponding to it within the frequency modulation control time
Both less than the 3rd buffer register residual memory space；
Step b2, the most then judge that the permission of frequency modulation control time inter-sync dynamic RAM is all in real time
The read-write requests of module is all not responding to；If it is not, return step b1 and wait that next sequential carries out performing judgement again
Operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210311491.2A CN103632708B (en) | 2012-08-28 | 2012-08-28 | The self refresh control apparatus of synchronous DRAM and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210311491.2A CN103632708B (en) | 2012-08-28 | 2012-08-28 | The self refresh control apparatus of synchronous DRAM and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103632708A CN103632708A (en) | 2014-03-12 |
| CN103632708B true CN103632708B (en) | 2016-08-10 |
Family
ID=50213669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210311491.2A Active CN103632708B (en) | 2012-08-28 | 2012-08-28 | The self refresh control apparatus of synchronous DRAM and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103632708B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105632546A (en) * | 2015-07-21 | 2016-06-01 | 上海磁宇信息科技有限公司 | MRAM (Magnetic Random Access Memory) chip and self-refreshing operation method thereof |
| CN105609130B (en) * | 2015-07-21 | 2020-04-07 | 上海磁宇信息科技有限公司 | MRAM chip with content addressing function and content addressing method |
| CN107132904B (en) * | 2016-02-29 | 2020-12-15 | 华为技术有限公司 | Control system and control method of DDR system |
| CN106155949A (en) * | 2016-06-30 | 2016-11-23 | 联想(北京)有限公司 | A kind of control method and device |
| CN111782027B (en) * | 2020-07-28 | 2022-10-25 | 珠海全志科技股份有限公司 | DDR memory operation frequency adjusting method and device |
| CN113037413B (en) * | 2021-03-11 | 2023-04-21 | 成都德芯数字科技股份有限公司 | Frequency modulation synchronization method, device, system, equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1232266A (en) * | 1998-03-30 | 1999-10-20 | 西门子公司 | Recoded autorefresh mode in DRAM |
| US6266282B1 (en) * | 1998-08-13 | 2001-07-24 | Samsung Electronics Co., Ltd. | Write method of synchronous flash memory device sharing a system bus with a synchronous random access memory device |
| CN1446358A (en) * | 2000-07-07 | 2003-10-01 | 睦塞德技术公司 | Dynamic radom access memory, memory device and read command execution method thereof |
| CN1627441A (en) * | 2003-11-25 | 2005-06-15 | 尔必达存储器株式会社 | Latch circuit and synchronous memory including the same |
-
2012
- 2012-08-28 CN CN201210311491.2A patent/CN103632708B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1232266A (en) * | 1998-03-30 | 1999-10-20 | 西门子公司 | Recoded autorefresh mode in DRAM |
| US6266282B1 (en) * | 1998-08-13 | 2001-07-24 | Samsung Electronics Co., Ltd. | Write method of synchronous flash memory device sharing a system bus with a synchronous random access memory device |
| CN1446358A (en) * | 2000-07-07 | 2003-10-01 | 睦塞德技术公司 | Dynamic radom access memory, memory device and read command execution method thereof |
| CN1627441A (en) * | 2003-11-25 | 2005-06-15 | 尔必达存储器株式会社 | Latch circuit and synchronous memory including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103632708A (en) | 2014-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103632708B (en) | The self refresh control apparatus of synchronous DRAM and method | |
| US6073223A (en) | Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory | |
| JP2003308246A (en) | Unit and method for clock control over memory controller | |
| JP2018137034A (en) | Directed automatic refresh synchronization | |
| EP2600253B1 (en) | Semiconductor device and data processing system | |
| JP5893632B2 (en) | Memory controller, system, and method for applying page management policy based on stream transaction information | |
| CN101331464A (en) | Storage region allocation system, method, and control device | |
| JP2002007200A (en) | Memory controller and operation switching method and interface device and semiconductor integrated chip and recording medium | |
| JP2006512717A (en) | Dynamic memory refresh port | |
| US9697145B2 (en) | Memory interface system | |
| WO2023066391A1 (en) | Memory controller, internet-of-things chip, and electronic device | |
| US6728157B2 (en) | Semiconductor memory | |
| WO2020155074A1 (en) | Processing apparatus, method, and related device | |
| JP2002109882A (en) | Semiconductor memory device, memory system, and memory data access method | |
| JP3728468B2 (en) | Memory control device | |
| US8015459B2 (en) | Semiconductor memory device and method of performing a memory operation | |
| CN102566655B (en) | Dynamic bus frequency modulation method of off-chip memory and system thereof | |
| JP2001035158A (en) | Method and system for accessing memory | |
| CN102243526B (en) | Double date rate internal memory controller and control method thereof | |
| US20110314197A1 (en) | Data processing system | |
| JP2000020451A (en) | Device and method for processing information and provision method | |
| CN102279801A (en) | Memory sharing system and method | |
| US20220139448A1 (en) | Interactive Memory Self-Refresh Control | |
| US20100138578A1 (en) | Memory access controller, system, and method | |
| JPH09237492A (en) | Memory control device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |