CN100580804C - Dynamic RAM device with data-handling capacity - Google Patents
Dynamic RAM device with data-handling capacity Download PDFInfo
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- CN100580804C CN100580804C CN200810046723A CN200810046723A CN100580804C CN 100580804 C CN100580804 C CN 100580804C CN 200810046723 A CN200810046723 A CN 200810046723A CN 200810046723 A CN200810046723 A CN 200810046723A CN 100580804 C CN100580804 C CN 100580804C
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Abstract
The invention relates to a DRAM storage device provided with data processing ability, comprising a storage interface, a processing unit, a control interface of the processing unit, an internal storage, a communication network and an internal DRAM storage controller, wherein the storage interface is used to interact data with an external storage bus, and is connected with the internal DRAM controller in the device and the control interface of the processing unit, the processing unit and the internal DRAM controller are connected with each other by the communication network, and the DRAM controller is also connected with the internal DRAM storage. The invention can apply the device to a variety of data processing systems under the condition of unchanging any hardware, and the invention not only can provide storage abilities of procedures and data for common storages, but also provide the ability of processing the data in the storages. Further, the device has the advantages of high performance, low power consumption and convenient application.
Description
Technical field
Patent of the present invention relates to the storer of data handling system, relates in particular to DRAM (dynamic RAM) device with data-handling capacity.
Background technology
In the past few decades, performance of processors promotes with the surprising speed of doubling in per 18 months according to Moore's Law always.This all has benefited from the huge raising of integrated circuit fabrication process and architecture technology.But people have also come to realise increasing factor and hamper performance of processors and further promote.Wherein " storage wall " is exactly insoluble problem in existing Feng's Von Neumann architecture.During former design was produced, processor and storer all were independent design and optimizations.The manufacturing process of processor is that logic is a target to produce fast; And the manufacturing process of DRAM memory is to be purpose to obtain storage density.Therefore adopt different manufacture methods to obtain processor and inexpensive high-density storage fast.But this method also produces a very serious negative effect, and that is exactly because processor performance is at a high speed shielded by at a slow speed DRAM main memory, thereby does not reach its performance boost desired to total system.
At storage wall problem, be that people use the level storage system under the framework at center with the processor in tradition, and adopted a large amount of methods to reduce or the access delay of concealing memory.These technology comprise that improving high-capacity cache memory (Cache), software and hardware looks ahead, infers and carry out and multithreading etc.But these methods are also inevitable must introduce more restriction.As the access delay of storer under the meeting increase failure conditions, the some of them technology also more is subjected to the restriction of bandwidth of memory.
In order can to start with from architecture from solving the problem of storage wall in essence.Existing a solution is exactly PIM (Processor In Memory) architecture.It is the progress along with technology, and processor and DRAM storer can integrate and produce.Thereby avoided the storage wall performance bottleneck of traditional Feng's Neumann structure.The PIM technology directly is integrated into logical device in the storer, has characteristics such as low delay, high bandwidth and low-power consumption, and use PIM technology can be from alleviating storage wall problem in essence.In more than ten years in the past, the whole world has many universities or research institution hand starting to study this technology, comprise ActivePage, IRAM, HTMT, DIVA, FlexRAM, Blue GeneBG/C, Pim-Lite and Gilgamesh etc.Can be divided into two classes according to these PIM chips role in computer system.One class is processor chips, and method is that handle is with high capacity DRAM and the status that suitable processor is integrated into a chip and serves as processor.Another kind of is the storage chip of band computing power, and it is that the PIM chip is replaced original memory chip, thus for the original computer system provides stronger computing power, as IRAM, FlexRAM.Yet these memory chips all can not effectively not be integrated in the existing data processing system owing to satisfy the sequential agreement of existing storer.
In sum, be badly in need of a kind of storage arrangement that is easy to be integrated into the band data-handling capacity in the available data disposal system at present, replenish or replace the external storage in the available data disposal system.By the ability of data processing is provided, solve serious day by day " storage wall " problem in the available data disposal system in storer.
Summary of the invention
The objective of the invention is on the prior art basis, do not have the deficiency of processing power, a kind of DRAM storage arrangement with data-handling capacity is provided at having storer now.The interface of this device is consistent with existing memory interface, changes without any hardware just can effectively be integrated in the available data disposal system.This device can provide simple program and data storage function, can in memory inside data be handled under the use scheduling of application program and operating system again, effectively solves " storage wall " problem, reaches the purpose that promotes performance, reduces power consumption.
Purpose of the present invention is achieved through the following technical solutions:
Design a kind of new structure that has, make DRAM have powerful calculation function, be used for the calculating of expedited data disposal system and memory function is provided, this device comprises: memory interface, processing unit, the processing unit control interface, inner DRAM storer, communication network and inner DRAM memory controller, memory interface is used for and the external memory bus interaction data, be connected simultaneously with inside DRAM memory controller and processing unit control interface in the device, processing unit is connected by communication network with inner DRAM memory controller, and inner DRAM memory controller also connects inner DRAM storer simultaneously.
Described memory interface, the main various memory access orders of being responsible for handling outside DRAM memory controller, by the state and the control register of DRAM storer or processing unit in the decoding selecting arrangement, also receive outside operational order to DRAM device simultaneously to send DRAM storer in the corresponding device thereof to data-handling capacity.Described processing unit as the parts with data-handling capacity in the storage arrangement, is used for the various application of expedited data disposal system.Described processing unit control interface receives each processing unit and memory interface to the control of each processing unit and the visit of status register.The inner DRAM storer of described device in order to the data and the program of storage data handling system, can adopt embedded DRAM (eDRAM) technology or other memory technology to realize.Described inner DRAM memory controller receives memory access order and operational order from memory interface, is responsible for simultaneously handling from the memory access request on the communication network.Described communication network is born the memory access path of data processing unit to inner DRAM storer, and finishes the protocol conversion with inner DRAM memory controller.
Described data handling system Main Processor Unit and the passage with exchange message between the DRAM storage arrangement of data-handling capacity are flash memory (FLASH), static RAM (SRAM), synchronous DRAM (SDRAM), Double Data Rate synchronous DRAM (DDR), second generation Double Data Rate synchronous DRAM (DDR2), third generation Double Data Rate synchronous DRAM (DDR3), the sequential of special-purpose Double Data Rate synchronous DRAM (GDDR2) of second generation figure or special-purpose Double Data Rate synchronous DRAM (GDDR3) the interface standard regulation of third generation figure.
The inner integrated processing unit more than or two of DRAM storage arrangement, described processing unit is general purpose microprocessor, risc processor or dsp processor.
Described processing unit is for quickening the application specific processor that certain class is used.
The inner integrated inside DRAM storer more than or two of DRAM storage arrangement.
The present invention can be under the situation of not carrying out any hardware change, this device is applied to various data handling systems, both can be used as normal memory the storage capacity of program and data was provided, can provide the ability that data in the storer are handled again, to improve the performance of data handling system.This device have the performance height, low in energy consumption, use advantages such as convenient.
Description of drawings
Fig. 1 is a hardware structure synoptic diagram of the present invention;
Fig. 2 is the framework synoptic diagram of memory interface;
Fig. 3 is the framework synoptic diagram of processing unit control interface;
Fig. 4 is a moderator parallel organization synoptic diagram;
Fig. 5 is a processing unit operation register synoptic diagram;
Fig. 6 is a processing unit status register synoptic diagram;
Fig. 7 is a processing unit data transfer request register synoptic diagram;
Fig. 8 is a data transmission state register synoptic diagram;
Fig. 9 is a processing unit control interface signal graph;
Figure 10 is a Stamp Interface status transition diagram;
Figure 11 is inner DRAM memory controller framework synoptic diagram;
Embodiment
Realization, the functional characteristics of the object of the invention will be in conjunction with the embodiments, are described further with reference to accompanying drawing.
Originally the DRAM storage arrangement that has data-handling capacity divides from functional module, comprises memory interface, processing unit, processing unit control interface, communication network, inner DRAM storer, inner DRAM memory controller composition.Memory interface is used for and the external memory bus interaction data, be connected with interior dram controller of device and processing unit control interface simultaneously, processing unit is connected by communication network with the interior dram controller of device, and dram controller also connects inner DRAM storer simultaneously.In most preferred embodiment, we adopt standard DDR2 interface and standard, the eDRAM on-chip memory of integrated 4 each 64KByte sizes and 4 processing units.But the present invention is not limited to adopt above-mentioned interface specification and configuration.
The major function of this device each several part is:
Memory interface, be responsible for accepting and resolving read-write and the operational order that defines by general DRAM storage arrangement transmission specification, on the basis of the sequential operation that guarantees the transmission specification definition, provide the internal storage of the DRAM device of primary processor and the access path of data processing unit to having data-handling capacity.Described memory interface is connected with chip pin, processing unit control interface and inner DRAM memory controller respectively, and distinguishes storage space by row address.If visit to processing unit, by memory interface the row, column address is spliced, and the accessing time sequence of general DRAM storage arrangement normalized definition is converted into the required SRAM storer sequential in access process unit, to realize the startup and the inquiry of processing unit; If visit to inner DRAM storer, select a certain inner DRAM storer by memory interface, and the input end that the operational order and the data of interface are directly delivered to this inside DRAM, with realize to the internal storage of device activation, preliminary filling, reading and writing, operation such as refresh.
Most preferred embodiment adopts general DDR2 standard as interface and transmission specification with DRAM storage arrangement of data-handling capacity.In other embodiments, also can adopt FLASH (flash memory), SRAM (static RAM), SDRAM (synchronous DRAM), DDR (Double Data Rate dynamic RAM), DDR2 (second generation Double Data Rate synchronous DRAM), DDR3 (third generation Double Data Rate dynamic RAM), GDDR2 (the special-purpose Double Data Rate synchronous DRAM of second generation figure), GDDR3 general DRAM memory device interface and transmission specifications such as (the special-purpose Double Data Rate synchronous DRAMs of third generation figure).
Adopt the DRAM memory device interface signal with data-handling capacity of DDR2 standard and describe as shown in table 1.Memory interface one end connects interface signal as shown in table 1, and an end connects inner DRAM memory interface and processing unit control interface, and its concrete module map as shown in Figure 2.Data-signal Data among the figure comprises DQ, DQS, DM, and control signal Ctrl comprises CKE, ODT, CS#, RAS#, CAS#, WE#.
Table 1DDR2 standard interface signal and description
| Title | Direction | Describe |
| CK, CK# | Input | Clock signal: CK and CK# are the clock signal of difference.The input data also are that the negative edge of CK# is sampled all at the rising edge of CK; Output data is all exported at the rising edge of CK and CK#. |
| CKE | Input | Clock enables: activate (for high) or close (for low) sheet internal clock circuit. |
| ODT | Input | Terminal enables on the sheet: internal resistance is connected to pin DQ, DQS and DM when high.If EMR (1) register is programmed for calcellation ODT, then ignore this signal. |
| CS# | Input | Sheet choosing: enable (for low) or close (for high) storage arrangement. |
| RAS#, CAS#, WE# | Input | Order input: RAS#, the different input command of combination definition that CAS# is different with WE#. |
| DM | Input | Input data mask: to writing the signal that data shield.If the DM signal is high when write command, then shield this and write data, it is not write |
| Storer. | ||
| BA0～BA2 | Input | The body address: definition to which body is operated. |
| A0～A15 | Input | Address: row address is provided when activation command; When read write command, provide column address and preliminary filling control bit.A10 is as the preliminary filling control bit, if low, preliminary filling is by the body of BA0～BA2 definition; If high, all bodies of preliminary filling. |
| DQ | Two-way | Data input and output: two-way data bus. |
| DQS | Two-way | Data strobe pulse: when read data as output, when write data as input.Align with lower edge on the sense data, and write the data stage casing and align. |
| VDDQ | Power supply | The input of DQ power supply |
| VSSQ | Power supply | The input of DQ ground |
| VDLL | Power supply | The input of DLL power supply |
| VSSDL | Power supply | The input of DLL ground |
| VSS | Power supply | The power supply input |
| VDD | Power supply | The ground input |
| VREF | Power supply | The reference power source input |
Adopt the DRAM memory device interface protocol command truth table with data-handling capacity of DDR2 standard as shown in table 2.Memory interface is responsible for receiving and resolving various command as shown in table 2, is at inner DRAM storer or processing unit by state machine (State Machine) according to current order, the control store interface enters internal memory operations pattern or processing unit operation pattern, and current operator scheme is retained to always and receives the order that next changes current operator scheme.The Data of memory interface, Ctrl, address signal directly link to each other with inner DRAM memory interface, under the internal memory operations mode state, determine the value of CS0～CS3 by the current command, operate to select one or more internal storages.Because the processing unit interface adopts the SRAM interface, so under the processing unit operation pattern, realize the sequential conversion of DRAM to SRAM by sequential conversion (Timing Transfer) module.
Table 2DDR2 standard agreement order truth table
Memory interface is as follows to the concrete processing of various memory access orders:
1, mode register is set: enter the internal memory operations pattern under the mode register command being provided with, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, be provided with the mode register of realization to all internal storages.
2, refresh: under refresh command, enter the internal memory operations pattern, by refresh counter (Refresh Counter) refresh command is carried out cycle count from 0～3, if the current i that count down to, gating CSi then is to realize the refresh operation to a certain internal storage.
3, enter self-refresh mode: enter the internal memory operations pattern under the self-refresh mode order entering, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, control all internal storages and enter self-refresh mode.
4, go out self-refresh mode: going out to enter the internal memory operations pattern under the self-refresh mode order, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, control all internal storages and withdraw from self-refresh mode.
5, preliminary filling monomer: under the order of preliminary filling monomer, enter the internal memory operations pattern,,, control all internal storages certain one is carried out preliminary filling with the whole gatings of CS0～CS3 by state machine (State Machine) control decoding unit (Decoder).
6, all bodies of preliminary filling: under all body orders of preliminary filling, enter the internal memory operations pattern,,, control all internal storages all bodies are carried out preliminary filling with the whole gatings of CS0～CS3 by state machine (State Machine) control decoding unit (Decoder).
7, activate: determine that according to the value of row address A15 this activation manipulation is at internal storage or processing unit.If A15 is high, enter the processing unit operation pattern, sequential conversion (Timing Transfer) module is sent in row address and body address carry out buffer memory, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3; If A15 is low, enter the internal storage unit operator scheme, (Decoder) deciphers address signal A14, A13 by decoding unit, operates with one among gating CS0～CS3.
8, write: if current for the processing unit operation pattern, column address is sent into sequential conversion (TimingTransfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that processing unit is carried out write operation; If current be the on-chip memory operator scheme, and control decoding unit (Decoder) by state machine (State Machine), when keeping last activation manipulation among the CS0～CS3 of gating one is so that carry out write operation to a certain internal storage.
9, write the back preliminary filling: if current for the processing unit operation pattern, column address is sent into sequential conversion (Timing Transfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that the data processing unit is carried out write operation; If current be the internal memory operations pattern, and by state machine (StateMachine) control decoding unit (Decoder), when keeping last activation manipulation among the CS0～CS3 of gating one operates so that a certain internal storage is write the back preliminary filling.
10, read: if current for the processing unit operation pattern, column address is sent into sequential conversion (TimingTransfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that processing unit is carried out read operation; If current be the on-chip memory operator scheme, and control decoding unit (Decoder) by state machine (State Machine), when keeping last activation manipulation among the CS0～CS3 of gating one is so that carry out read operation to a certain internal storage.
11, read the back preliminary filling: if current for the data processing unit operator scheme, column address is sent into sequential conversion (Timing Transfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that the data processing unit is carried out read operation; If current be the internal memory operations pattern, and by state machine (StateMachine) control decoding unit (Decoder), when keeping last activation manipulation among the CS0～CS3 of gating one operates so that a certain internal storage is read the back preliminary filling.
12, there is not operation: keep current operator scheme, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3.
13, the cancellation device is chosen: keep current operator scheme, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3.
14, enter low-power consumption mode: enter the on-chip memory operator scheme under the low-power consumption mode order entering, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, control all internal storages and enter low-power consumption mode.
15, go out low-power consumption mode: going out to enter the on-chip memory operator scheme under the low-power consumption mode order, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, control all internal storages and withdraw from low-power consumption mode.
Processing unit is responsible in device inside data being handled, to realize this locality acceleration to the data intensive applications.Processing unit can be one or more general purpose microprocessors, risc processor, dsp processor or be to quicken the application specific processor that certain class is used.
In most preferred embodiment, we have adopted 4 dedicated data processor as data processing unit.Be not limited to adopt this processor and this configuration in other embodiments.Memory interface is operated processing unit internal state register by the processing unit control interface, and these registers include but not limited to processing unit general-purpose register, processing unit control and status register, processing unit TLB registers group, request of data register etc.By to these operation registers, the primary processor in the data handling system can start these processing units and carry out data processing, query processing location mode, upgrades processing unit TLB.
The processing unit control interface is responsible for receiving trap inter-process unit and memory interface to the control of each processing unit and the visit of status register.Can have access to the state and the control register of other processing units by this interface processing unit, thereby the interoperability between the processing unit is provided; In addition, primary processor also can be by the state and the control register of memory interface access process unit and control interface, thereby control ability and the communicating by letter of processing unit and primary processor of primary processor to processing unit is provided.
The framed structure of processing unit control interface as shown in Figure 3.It mainly is made up of moderator, code translator, control and three modules of status register, and moderator is responsible for receiving to the control of processing unit and control interface and the visit order of status register, and arbitrates according to priority policy.Code translator is used for the visit order of moderator output is carried out address decoding, to send read write command.The control of control interface and status register are mainly used to preserve the communications command of processing unit and primary processor.
In main interface that the processing unit control interface is connected, with the state and the control register that are used for main processor accesses processing unit and processing unit control interface being connected of memory interface; Be mainly used in control and the status register that processing unit is visited other processing unit and processing unit control interface with the connecting interface of processing unit.Have only the interface with processing unit from interface, it is used for the data access of processing unit control interface to processing unit.
Described moderator is that a priority is selected arbitration modules.There are two kinds of schemes can realize this moderator.Fig. 3 has described a kind of comparatively simple proposal.Promptly at every turn from request signal according to priority or policy selection read write command in advance, send to code translator and decipher.A kind of comparatively complexity but performance be high moderator structure as shown in Figure 4.Because the different processing unit states and the state and the control register of control register and processing unit control interface are separate, the read and write access that they are carried out can be walked abreast fully.Moderator is at first deciphered, so long as just can concurrent access in different registers group visits.When running into plural read-write and visit same registers group, then select according to priority policy.
Described code translator is mainly deciphered to determine being which registers group of visit according to the reference address of read write command.Because the state of a control register of processing unit and control interface thereof is to distribute during by operating system, thereby described code translator at first need read the conduct interviews decoding of address of configuration information.
Described control and status register can be distributed in the internal register of processing unit, also can concentrate to be placed in the processing unit control interface module.Concentrating the benefit that is placed in the processing unit control interface is to reduce the access times of primary processor to the processing unit register.Described control and status register be mainly used between the processing unit and with primary processor between communicate by letter, comprise processing unit operation register, processing unit duty register, processing unit data transfer request register and data transmission state register.
The processing unit operation registers group is 4 64 bit registers as shown in Figure 5, and it also can be realized by 32 bit registers.Each register comprises 32 enabling addresses and 1 startup zone bit, all the other 31 reservations.
Processing unit duty register is 32 bit registers as shown in Figure 6, and wherein each processing unit takies two, other 24 reservations.In two, whether a bit representation calculates is finished, and whether a bit representation has request of data.
Processing unit request of data registers group is 4 128 bit registers as shown in Figure 7, and it also can be realized by 32 bit registers.Each register comprises 32 source address, 32 destination address, and 32 data transfer request register, and other has 32 reservations.
The data transmission state register is 32 for register as shown in Figure 8, and wherein each processing unit takies 2, other 24 reservations.These two are used for representing that primary processor responds the result phase of the data transfer request of processing unit: 00 expression is not finished, and 11 expressions are finished, and mistake appears in 01 expression transmission, 10 reservations.
The signal of processing unit control interface all is that the access mode according to similar SRAM realizes.But increased the GRANT signal at processing unit in the conducting interviews of processing unit, when not replying, processing unit should resend visit order.Since the highest from memory interface visit order priority, the situation that read write command does not respond can not take place, therefore do not need the GRANT signal.Concrete interface signal as shown in Figure 9.
Inner DRAM storer is responsible for storing the data and the program of data handling system.DRAM storer in the eDRAM sheet of integrated 4 each 64KByte sizes in this most preferred embodiment.But the size of DRAM storer, configuration and realization technology are not limited to this in the sheet.
Communication network mainly is responsible for bearing the memory access path of processing unit to inner DRAM storer, mainly is responsible for the conversion of network communication protocol and inner DRAM memory access agreement by the stamp interface.It should be noted that interface accessing on the DRAM memory controller can block the access to netwoks on the same bank, but the access to netwoks on other memory bank is not exerted an influence.With the data reading operation is example, and its workflow is:
A, processing unit by communication network will read request or the write request Stamp interface that is sent to target DRAM storer;
B, Stamp interface are responsible for a read request or write request converts DRAM memory access order to, is dealt into the DRAM memory controller.
The read request of processing unit comprises memory access address, memory access size and read request; The write request of processing unit comprises memory access address, memory access data, memory access size and write request.
Figure 10 is the state transition graph that the Stamp interface is responsible for the microprocessing unit command conversion is become the DRAM memory controller.The duty of Stamp interface is divided into idle condition, state of activation, read-write state, normal charging condition, shifts to an earlier date charged state, retry state.The workflow of Stamp interface is:
A, Stamp interface are in idle condition, receive read request or write request from processing unit, if the processing unit request effectively and not monitors the ACTIVE order from memory interface, enter state of activation;
B, Stamp interface are in state of activation, if do not monitor ACTIVE order from memory interface, send the DRAM activation command so, activate the DRAM storage line that processing unit is about to visit, enter read-write state,, do not send any order so if monitor ACTIVE order from memory interface, the read-write requests of expression microprocessing unit is not finished, and enters retry state;
C, Stamp interface are in read-write state, if do not monitor ACTIVE order from memory interface, send the DRAM read write command, enter normal charging condition, if monitor ACTIVE order from memory interface, operated storage line is charged, enter charged state in advance;
D, Stamp interface are in normal charging condition, send the DRAM charge command, and C operated storage line of step is charged, and the read-write requests end of operation of microprocessing unit enters idle condition;
E, Stamp interface are in charge mode in advance, show that the read-write requests of microprocessing unit is not finished, and wait to be charged finishing, and enter retry state;
F, Stamp interface are in retry state, wait for that the PRECHARGE command execution that monitors from memory interface finishes, and the read-write requests that is ready to not be finished just now enters state of activation.
Inner DRAM memory controller is responsible for handling the DRAM operational order from the Stamp interface, and is responsible for handling the DRAM operational order from memory interface.Inner DRAM memory controller needs to be treated differently two types request of access, and the access privileges of memory interface requires to be higher than the request of access that interconnection network send by the Stamp interface.Therefore, when memory interface conducts interviews, if there is request of access to inner DRAM the internet, then the request of access of internet is blocked and be cached in the order buffer memory, so that after the memory interface visit, send the request of access of internet by inner DRAM memory controller.And when inner DRAM storer is being visited in the internet, if memory interface has request of access, the internet request of access of then cancelling current, and send the preliminary filling order to inner DRAM storer, close the row that has activated by the internet request of access.Because the operating frequency of inner DRAM memory controller is far above the access frequency of memory interface, therefore this preliminary filling order of inserting can't influence the accessing time sequence of memory interface.After the memory interface visit is finished, carry out the previous internet visit order that cancels once more.
Figure 11 is the schematic diagram that dram controller is handled two class orders.Described order buffer memory is used for buffer memory from the memory interface order, and the degree of depth of buffer memory is 2 or 3.Described command interpretation unit is used for directly the logical and operation being carried out in storage request that comes from the Stamp interface and the order that comes from the order buffer memory, and will be used to control the DRAM memory bank with operating result.
The present invention has the DRAM storage arrangement of data-handling capacity, provide data-handling capacity in the DRAM memory inside, adopt existing DRAM memory interface and agreement, can on the basis of not carrying out any hardware change, be integrated into the available data disposal system.General program and data storage capacities can be provided, can provide this locality that data are handled to quicken again, have the performance height, low in energy consumption, use advantages such as convenient.
Claims (5)
1, the DRAM device that has data-handling capacity, comprise: memory interface, processing unit, processing unit control interface, inner DRAM storer, communication network, inner DRAM memory controller, memory interface is used for and the external memory bus interaction data, be connected with inner DRAM memory controller of device and processing unit control interface simultaneously, processing unit is connected by communication network with the inner DRAM memory controller of device, and inner DRAM memory controller also connects inner DRAM storer simultaneously;
Memory interface is used to handle the various memory access orders of outside DRAM memory controller, state and control register by decoding inner DRAM storer of selection or processing unit also receive outside DRAM operational order simultaneously and send corresponding inner DRAM storer to;
Processing unit is used for the effect of the various application of expedited data disposal system;
The processing unit control interface is used to receive each processing unit and memory interface to the control of each processing unit and the visit of status register;
Data and program that inner DRAM storer is used to store data processing unit;
Communication network is used to bear the memory access path of each processing unit to inner DRAM storer, and finishes the protocol conversion with inner DRAM memory controller;
Inner DRAM memory controller is used to receive memory access order and the operational order from memory interface, is responsible for simultaneously handling from the memory access request on the communication network.
2, according to the described DRAM device with data-handling capacity of claim 1, it is characterized in that: the Main Processor Unit of described data handling system and the passage with exchange message between the DRAM device of data-handling capacity are flash memory (FLASH), static RAM (SRAM), synchronous DRAM (SDRAM), second generation Double Data Rate synchronous DRAM (DDR2), Double Data Rate synchronous DRAM (DDR), third generation Double Data Rate synchronous DRAM (DDR3), the sequential of special-purpose Double Data Rate synchronous DRAM (GDDR2) of second generation figure or special-purpose Double Data Rate synchronous DRAM (GDDR3) the interface standard regulation of third generation figure.
3, the DRAM device with data-handling capacity according to claim 1 is characterized in that: the inner integrated processing unit more than or two of DRAM device, described processing unit is general purpose microprocessor, risc processor or dsp processor.
4, the DRAM device with data-handling capacity according to claim 1 is characterized in that: the application specific processor of described processing unit for quickening to use.
5, the DRAM device with data-handling capacity according to claim 1 is characterized in that: the inner integrated inside DRAM storer more than or two of DRAM device.
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| CN200810046723A Expired - Fee Related CN100580804C (en) | 2008-01-21 | 2008-01-21 | Dynamic RAM device with data-handling capacity |
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| US9477636B2 (en) * | 2009-10-21 | 2016-10-25 | Micron Technology, Inc. | Memory having internal processors and data communication methods in memory |
| CN102736997B (en) * | 2011-04-01 | 2017-05-03 | 中兴通讯股份有限公司 | Method and system for on-chip interconnection bus arbitration |
| US9317212B2 (en) * | 2012-12-18 | 2016-04-19 | Intel Corporation | Method and apparatus for controlling a storage device |
| CN110908491B (en) * | 2018-08-28 | 2023-08-08 | 上海忆芯实业有限公司 | Power consumption control method, control part and electronic system thereof |
| WO2020155074A1 (en) * | 2019-01-31 | 2020-08-06 | 华为技术有限公司 | Processing apparatus, method, and related device |
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