SU1408439A1 - Addressing device for automatic configuration of computer memory - Google Patents

Abstract

The invention relates to computing and can be used for continuous addressing of computer memory modules. The aim of the invention is to expand the functionality of the device by schematically implementing automatic shutdown of failed modules of the module and setting up continuous addressing for healthy memory modules, with the information about the disabled (failed) memory modules being visually presented to the operator on the display unit -, katsii. This goal is achieved due to the fact that a device containing a register of physical addresses, a register of conditional addresses, a block of conversion registers are additionally entered with a register of commands, two multiplexers, an indication register, an element NOT, and an element I. 2 Il. g (O

Description

The invention relates to computing and can be used in the continuous addressing of computer memory modules.

The operational memory of high-powered computing machines consists of Separate modules that can be switched on if there are inconsistencies in them, and the serviceable modules should be continuously addressed in this case.

I The assignment operations to disconnected continuous addressing memory modules are performed by memory configuration devices.

i The purpose of the invention is to expand the functionality due to the circuit implementation of the automatic shutdown of faulty memory modules | and establishing continuous addressing | for healthy memory modules: FIG. 1 shows the structure of the processor, the addressing device (RAM) {in figure 2 - the functional diagram of the device {{device.

I The connection scheme includes a process I sor 1, an addressing device 2, and a one-memory memory 3.

The addressing device contains a register of 4 commands, a register of 5 physical addresses, a register of 6 conditional addresses, I block 7 of address conversion registers, first 8 and second 9 multiplexers, register 10 of indication, block 11 of indication, element 12 and element NOT 13.

Outputs F, P, Q, A2, A1, Fj processor I 1 are respectively an information recording output, in memory 3, an output of memory access 3, an information output, an address output in memory modules, an output of address modules memory, device control output 2.

The outputs of device 2A and F are, respectively, the outputs of the physical address of the memory modules and the control output, the latter being used to transmit a signal to processor 1 An invalid address if processor 1 accesses a disabled memory module and a signal, End configuration required for signaling the end in device 2 of the memory configuration mode.

The modes of operation of the device are determined by the codes set on the register of 4 commands, the first and second outputs

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the ports of which are connected to the control inputs of the registers of physical 5 and conditional 6 addresses, respectively. With a single value at any output of the register of 4 commands, the corresponding register of physical 5 or conditional 6 addresses operates in the mode of recording information on information inputs, otherwise these registers operate in counter mode, and the modes of the registers of conditional 6 and physical 5 addresses are implemented if there are single signals on their sync inputs.

Depending on the codes set at the outputs of the register of 4 commands, the device can operate in the following modes: memory configuration (code 00 on register 4), memory access by physical addresses (code 01 on register 4), memory access by conditional addresses (code 10 on register 4), memory configuration changes (code 11 on register 4).

The memory configuration mode is as follows. The control signal Reset sets all the registers of device 2 to the zero state, using the control signal Control. - setting the Configuration command code (code 00) on the command register 4, verifies the test information of the memory module 3, whose address corresponds to the code set on register 5, which runs in the counter (at the address input of multiplexer 9, in this case , allowing the signal from the output element NOT 13). In the case of a positive test of the memory module 3, the device 2 generates a single signal from the processor 1 Record and a single signal to the first input of the mode assignment and the code set on register 5 is entered into the register of block 7 defined by code on register 6, in display register register 1Q, corresponding to the code on register 6, a single value is set. Signals Sync. FA and Sync UA, accessed from processor 1, the codes change by +1 in registers 6 and 5.

In the event of a negative result when testing with the test control of the memory module fl memory 3, the signals Record and Sync, A / V are not generated, i.e.

Writing the code of register 5 to the corresponding register of block 7 is not made, and the state in the corresponding register register 10 does not change.

If register 5 overflows, processor 1 signals the end of memory configuration mode. End of configuration. Thus, in the configuration mode, the registers of the block 7 are sequentially recorded with the codes of the physical addresses of the healthy memory modules, and in the display block 11, the indicators corresponding to the healthy memory modules are set to Off.

The mode of accessing memory 3 by physical addresses is carried out by setting code 01 on register 4, followed by setting the code of physical addresses in register 5. In this case, the codes of physical addresses of memory modules set on register 5 enter memory 3 through the second the information input of the multiplexer 9, since the address and the low-order bit of the second information input is excited by a single signal from the output of the NOT 13 element. This mode is mainly used when searching for faults in the memory modules.

The memory access mode by conditional addresses is made by setting the signal Ex. Code 10 on the register 4 teams and signals Sync. UA is the installation of codes | conditional addresses in register 6. In this case, the outputs of multiplexer 8 appear codes of physical addresses corresponding to the codes of conditional addresses that excite the address inputs of the multiplexer. The physical address codes from the output of multiplexer 8 are transmitted through multiplexer 9 to memory 3, and if the inverse-lower order bit of the output of multiplexer 9 results in a single signal, then the physical address at the outputs of this multiplexer will be invalid.

The memory configuration change mode is the mode of assigning the corresponding conventional address to the physical address of this memory module. This mode is used in some cases when the memory module is out of order during the execution by processor 1 of the computational process. In this mode, the signals Control.

Sync FA and Sync. UA production 1T- with the installation of codes on registers 4-6. The Recording Signal records the physical address code in block 7, and if there is a single signal at the first input of the mode setting, then the physical address recorded in the corresponding registers of block 7 is valid, otherwise the physical address is invalid and The deregister 10 of the indication is set to a zero code, i.e. the corresponding indicator in the display unit 11 is set to the Enabled state.

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Claims (1)

Invention Formula An addressing device for automatic configuration of a computer memory containing registers of physical and conditional addresses, a block of address translation registers, wherein the information and address inputs of the block of address conversion registers are connected respectively to the outputs of the registers of physical and conditional addresses, in order to extend the functionality due to the circuit implementation of the automatic shutdown of faulty memory modules and the establishment of continuous addressing for healthy memory modules, in it contains a register of commands, two multiplexers, a display register, an element NOT and an element AND, the information inputs of the registers of conditional and physical addresses and commands are connected to the inputs of the register of the conditional and physical addresses and commands of the registers of physical and physical addresses with the corresponding synchronization input scaffolds, the mode control inputs of the conditional and physical address registers are connected to the forward and inverse inputs of the And element and to the first and second outputs of the command register, respectively, the junior times rows registers ka address conversion registers are connected to a first input specifying device mode and to data inputs of the display register, the outputs of which are the outputs of feature fault module memory device, the clock indication registers connected to the recorder input with the clock address conversion registers block address inputs which are connected to the address inputs of the first multiplexer, the address inputs of the display register are connected to the outputs of the register of physical addresses and to the higher bits of the second information input of the second multiplexer, the low order of the second information input and the address input of which is connected to the output of the element NOT whose input is connected to the second output command register, the first information input of the second multiplexer is connected to the output of the first multiplexer, whose information inputs are connected to the outputs of the block the address translation registers, the zero setting inputs of all the registers are connected to the device reset input, the inverse output of the AND element is the output of the device’s memory test completing output, the outputs of the second multiplexer are the device address setting outputs, the output of the configuration end flag device memory. fi S At A1 D s mm w t sh } At Nyaaya A1 figure 1