SU1381503A1 - Microprogram controller - Google Patents

Abstract

The invention relates to computing and can be used in computing devices and systems. The aim of the invention is to reduce the equipment by reducing the size of the address part of micro-instructions. The device contains n + 1 blocks I of forming the address n + 1 of blocks 2 of memory of micro-instructions, switch 3, register 4 of micro-commands, block 5 of checking the conditions, block 6 of forming the zone address. This set of features makes it possible to achieve the goal of the invention. 1 hp ff, 6 ill. in Q (L

Description

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The invention relates to computing and can be used in computing devices and systems.

The aim of the invention is to reduce the amount of equipment used by reducing the size of the address part of micro-instructions.

Figure 1 shows a block diagram of a firmware control device; Fig. 2 is a functional diagram of the unit for generating the zone address; FIG. 3 is a block diagram of the formation of an address; Fig. 4. shows a circuit for checking the conditions: in Figs. 5 and 6, an example of a graph diagram of a microprogram and the principle of its placement in the device memory blocks for a case.

The microprogram control unit (FIG. 1) contains n + 1 blocks ivti forming address n + 1 blocks 2, -2 microinstructions memory, switch 3, register 4 microinstructions, condition checking unit 5 and zone address generating unit 6, output 7 micro-operation codes and a group of 8 inputs logical device conditions.

Unit 6 of forming the address of the zone (FIG. 2) contains n + 2 switches 9 1 - 9 10 and register 11.

The address generation unit (FIG. 3) contains a combinational adder 12, a switch 13, a register 14, a transfer input 15 of the adder 12, to which a signal of a logical unit is applied. The condition checking unit 5 (FIG. 4) contains an output of 16, n decipherors, n groups 18, -18g, elements AND and n elements OR 19, - 19, an encoder 20 and an element OR-NOT 21.

The operation of the device will be considered for the case when the firmware is executed, the graph-diagram of which is shown in FIG. The placement of the firmware in question in the memory blocks of the device microinstructions is shown in FIG. The addresses of the memory cells in which microcommands are placed (Figs. 3 and 6) are depicted as senior and minor bits. The higher bits form the zone address for all blocks of 2 memory and are denoted by 3.1 (1 li3), and the lower bits are denoted by Agf A, B .. and Cj for the first, second and third blocks, the memory of micro instructions, respectively. It is assumed

0

five

five

five

0

0

that the difference between the values 3.1 and 3., AM from A ,, B from B ,, and C, from C, (O m i 2) is one. The codes of micro-operations are indicated through, and cf. t d - codes of logical conditions of the corresponding microinstructions. When microinstructions are placed in the memory blocks of the proposed device, it is assumed that the zones of these blocks consist of four cells and that the previously placed microprogram occupied three memory cells in each block 2-2. memory

The address of the next micro-command can be obtained in two ways. When forming the address by the first method, it is necessary that the next microinstruction be in the same zone as the previous one. Therefore, the zone address does not change, while the code in the zone address change field must be zero. An address within the next microcommand area can be obtained either by incrementing the address inside the previous microcommand area, if this next microcommand is located in the same memory block as the previous one, or directly by specifying the address of the previous microcommand in the corresponding code field if The following microinstruction is located in another memory block. When generating the address in the second way, the next microinstruction can be in any other zone in relation to the previous one. In this case, the address of the corresponding zone is specified in certain address fields of the previous microcommand, and a single code is set in the change address field of the zone address. The address within the zone is configured in the same way as in the first way. It should be noted that when generating the address using the second method, the previous microinstruction should not contain logical conditions check. The device works as follows.

Suppose that in the initial state of discharge the field of micro-operations is zeroed out, and the bits of the logic conditions are set to one state, in

e register, first block 1 formov0

No address is entered. Address A

3

and in

Register of the zone address generation unit - zone 3.1 address of the first micro3

commands of the executable firmware (the chain of entering the initial addresses and setting the zero and one states of the corresponding bits of the register of 4 microcommands, as well as the synchronization circuit are not shown). Since the input of the first decoder 17 of the condition checker 5 is a single code, the additional output is set to a signal 1, which is fed through the first element OR 19 to the first input of the encoder 20. Since this input has the highest priority, the first output 16 of the block 5, the condition check is set to signal 1, and the O signals are set at the remaining outputs. Therefore, the switch 3 is configured to fetch information from the output of the first memory block 2, from which the microcommand is read at address 3.1 A; the switch 10 of the zone address generation unit is configured to fetch information from the output of the first switch I9, to the first input of which from the second output of the output address code group of the first memory block 2 receives address C, and to the second input from the first output of the output code group of the address of the first block 2 the memory is the address of the new zone 3.2, which is transmitted to the output of the switch 9., because Signal 1 is received at its control input from the third output of the output code group of the address of the first memory block 2 (in Figure 6, a single code is set in the code for controlling the formation of the zone address of the readable micro-command); the switches of the first, second and third blocks 1-1, the address formations are configured to sample information respectively from the output of the adder. the first address generation unit and the first and second outputs of the output code group of the address code of the first unit 2, the memory. The sync signal, which completes the first cycle of the device, registers 4 with a micro-operation code Y and zero codes of the first and second logical conditions (in Fig. 6 are marked O), and the registers of the first, second and third address formation units 3 are respectively A. ,, 3.2 and GO, since the input to the write enable register of block 6 from the second output of the switch

815034

3, signal 1 is received (in FIG. 6, the zone address change code is set to one in the readable microcommand), then the new address of zone 3.2 is written to register 11.

Simultaneously with the execution of the Y-operations of Y from the memory blocks, the information is read, respectively, at addresses 3.2 A, 3.2 3.2 and 3.2 Cf. But since the inputs of the first and second decoders 17 and 17 of the condition check block 5 receive zero codes, then the output 16 of the block

g 5 us The signal 1 is set, and on the remaining outputs 16, -16 signals O. Consequently, the switch 3 is configured to fetch information from the output of the third memory block 2, the comm Q mutator 10 of the zone address generation unit - from the third switch 9 ", but since from the second output of the switch 3, the signal O (to

25, in the readable microinstruction Y, the zone address change code is set to the zero state), then the clock information in this register does not change. Switches first,

2Q of the second and third blocks I-I of the formation of the address- are configured to sample information from the first and second outputs of the output code group of the address of the third block respectively

3

memory and adder third

J-. GO block address formation. So,

according to the sync signal that completes the second cycle of the device operation, the micro-operation code Y and the codes, Ы, -, are recorded in register 4

The first and second logical conditions in the register 11 of the block for forming the zone address remain the same address of the zone 3.2, in the registers of the first, second and third blocks 1 -1. the address formations are written respectively to addresses A, B, and C.

Simultaneously with the execution of micro-operations Y., possible next microcommands from blocks are read

 memory, respectively, at addresses 3.2A, 3..2C. Depending on the fulfillment or non-fulfillment of condition s and o (l when the current microcommand is executed at the outputs

 The condition test block sets the following signals. If the first logical condition d is fulfilled, then signal 1 appears at the first output 16 of the condition check block, and O signals appear at the remaining outputs 16–16. Therefore, the micro-operations code Y is written to register 4 by the clock signal completing the third device operation cycle. „And codes

oi, d, respectively, of the first and logical conditions, into registers

the first, second and third blocks 1 | -C of the formation of the address are entered from respectively the addresses A, Bj and C and in the register I1 of the block for forming the zone’s address the former address of zone 3.2 remains, since in the considered microcommand the code for changing the address of the zone is set to zero (Fig.6). If the first logical condition ot is not fulfilled, but the second logical condition of is satisfied, then the signal 1 is outputted at the output of the second element OR 192. Since the first higher priority input of the encoder 20 has an O signal, the second output 6u of the conditioner is set signal 1, and on its remaining outputs 16 and 16 - signal O. Therefore, the micro-operations code Y, the ck-code of the first logic condition and the unit code of the second logic condition are written to register 4 on the clock signal that completes the third cycle of the device operation G. 6 is represented as, in the registers of the first, second and third blocks 1 Ij of the formation of the address, the addresses of AL, B and O are written, in the register I1 of the block of the formation of the zone’s address, the former address of zone 3.2 remains, as in this readable micro-command zone is set to zero. If the second logical condition is about (, | is not satisfied, then the signals O are set up at the outputs of the first and second elements 19 ,, 192 of the condition check. Consequently, the signal I is set at the output 16 a of the condition checker on the left The output signals 16, -16 of which are installed by the signals O. On the clock signal that completes the third cycle of operation of the device, microgroups Yg, zero code of the first logical condition and unit code of the second logical condition are written to register 4, into registers of the first, second and third blocks 15 address formations are recorded

respectively, addresses 3.1, V.i.C "in the register I1 of the block for forming the zone address is recorded the new address of zone 3.1, because

For the microcommand, the zone address change code is set to one and the zone 3.1 address is specified in the first address field. In this case, in

the next cycle of operation of the device simultaneously with the execution of micro-operations YJ from the second memory block 2.2, the next micro-command is found at 3.1 V. Then the device

works the same way.

In case of zero control code for the formation of the zone address, the value of the address of the new zone of the next microcommand is written in the second field of the address code.

parts of micro-instructions, the first field can be used as the lower-order bits of the address of this next micro-instruction (for example, Fig. 5 and 6 of the micro-command). With a single

In the control code for the formation of the zone address, the value of the address of the zone of the next microcommand is recorded in the first field of the address part of the microcommand;

to be used as the lower bits of the address of this next micro-instruction (for example, in Figures 5, 6, null, third and eighth micro-instructions).

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Claims (2)

1. A microprogrammed control device containing n + 1 (where n is the number of simultaneously scanned in the microcommand logical conditions) address formation blocks, n + 1 microcommand memory blocks, switch, microinstructions register and condition checker, the microcode register code output of the microcommand register is the device output of the same name, the group of microomand register logic output outputs are connected to the first group of block inputs condition test, the second group of inputs of which is a group of inputs of the logical conditions of the device, the output of the condition test block is connected to the control inputs of the first through () th form blocks address and switch, output K-th (1 f K p + O of the address generation unit is connected to the lower bits of the address inputs of the K-th microcommand memory block, i-th (1 b) 7I the output of the output group of the address code of which is connected to the Kth information input (i + I) -ro of the address generation unit (for all values) and with (K-1) -th information input i-ro of the address generation unit (for all values ii K), the first output of the switch is connected to the information input of the microinstruction register, characterized in that, in order to reduce the number of equipment by reducing the bit size of the address part of the microcommands, the device contains a zone address generation unit, and the output of the zone address generation unit is connected to the older ones as the address inputs from the first to (n + 1) -th microcommand memory blocks, the output of microoperation codes, logical conditions and signs of a change in the zone address of the Kth microcommand memory block are connected to the Km information input of the switch, the second output of which is connected with the first control input of the zone address generation unit, the second control input of which is connected to the output of the condition check block, n + 1 outputs of the goat output group 15038 Yes, the addresses of the K-th block of memory of micro-instructions are connected respectively to the (n- | -1) -th inputs of the K-th group of information inputs of the block that forms the zone address. 2. The device according to claim 1, characterized in that the block for forming the zone address contains switches and a register, and the output of the K-th (1 i K i P-I) switch is connected to the K-th information input of the (n + 2) -th switch whose output connected to the information input of the register, the output of which is the output of the block, i- (I 6 i p) group of information inputs of the K-th switch is connected to all inputs of the K-th group of information inputs of the block, except i-ro and (n + l ) th, the control input of the K-th switch is connected to (n + O th input of the K-th group of information inputs of the block, the register write enable input is connected to the first control input of the block, the second control input of which is connected to the control input of the (n + 2) -th switch. gjus.Z :  D- l it, J.Lj QATSJ :  D- FIG Memory block I t uKpoMHand Memory block 2 microinstructions 5 blocks of memory 3 microinstructions