SU1659983A1 - Programmable controller - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in distributed fault-tolerant control systems of a program-controlled process control system that can be expanded while expanding the number of functions performed. The purpose of the invention is improving the reliability and expanding the field of application of the device. The goal is achieved in that a known device containing a microcommand memory block, address registers and microoperations, address multiplexers and logic conditions, trigger trigger, additionally shift and idle shift registers, standby multiplexer , transmission multiplexer, tag decoder, wait counter, comparison unit, first and second elements OR, first to fourth elements I. Introduction of new elements by It allows, on the basis of the device, to provide the possibility of building an expandable flexible distributed control system, tunable in the event of failures, based on the configurations each with each. 4 silt, 1 tab. (L

Description

The invention relates to the field of automation and computer technology and can be used in distributed fault-tolerant control systems of a program-controlled process control system that can be expanded while expanding the number of functions performed.

The purpose of the invention is to increase the reliability and expand the field of application of the device.

FIG. 1 is a functional block diagram of a programmable control device; Fig. 2 is a functional diagram of a fault-tolerant control system built on the basis of programmable control devices; FIG. 3 is a flowchart of a programmable control device; 4 shows timing diagrams of the operation of two programmable control devices of a distributed fault-tolerant control system.

The device (Fig. 1) contains a micro-command memory block 1, address register 2, micro-operation register 3, transfer shift register 4, sleep shift register 5, address multiplexer 6, logical condition multiplexer 7, sleep multiplexer 8, transfer demultiplexer 9, decoder 10 feature, wait counter 11, comparison block 12, start trigger 13, first 14 and second 15 elements OR, first 16 - fourth 19 elements AND, information inputs 20 of the operation code, first

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21 — the third 23 synchronization inputs, information inputs 24 of logic conditions, information outputs 25 of microoperations, control output of state 26, information outputs of transmission 27, information inputs of wait 28, clock generator 29.

The purpose of the main functional elements of the programmable control unit.

Block 1 of the memory of micro-commands is intended for storing MK codes and has four outputs. From output 1.1, the sign field MK reads the sign code MK, which is decoded by the decoder 10 sign. From the output of field 1.2, the micro-operation code is read in control mode. In the AKU transmission mode, output 1.2 is read by an ACU, which is written to the shift register 4 of the transmission, or the wait code, which is fed to the second information input of the comparison block 12. Only the wait code is read out by the AKU standby state, at output 1.2.

From the output of field 1.3, a logical conditions code is read that controls the multiplexer 7 logical conditions. In the transfer mode (standby) AKU L-th (from N-ro) module from the output of field 1.3 reads the code of L-ro (N-ro) module, From the output of the field 1.4 address-reads the address of the next MC in the MP, the least significant bit of which may further be modified.

The address register 2 is intended for storing the address of the next MC during its reading from the memory 1 of micro-instructions. This address is fed to the information inputs of the register 2 addresses from the output of the multiplexer 6 address. Writing to register 2 is performed at the falling edge of the clock pulse from the output of the element 16, which forms it as a combination of the clock from the output 29.1 of the generator 29 of clock pulses (figure 4) and the signal from the output of the trigger 13.

Register 3 of micro-operations is intended for storage in the control mode of signals of micro-operations arriving at the information inputs from the output of field 1.2 of micro-operations of memory block 1 of micro-instructions. Microoperations are recorded in register 3 of microoperations on the falling edge of a clock pulse arriving at the microsurgical register 3 input from the output of element I 17. This pulse is formed as a conjunction of the clock pulse from the second output 29.2 of the clock generator 29 and the signal from the trigger 13 output. In addition, for writing to register 3 it is necessary that

the inverse control input of register 3 did not contain a single signal from the output of the third bit of field 1.1 of memory block 1 of micro-instructions. From the output of the register 3, the micro-operation code enters the outputs 25 of the device.

Shift transfer register 4 is designed to store, in the AKU transmission mode, the address control code received

0 from the outputs of the field 1.2 of the memory block 1 micro-commands. The ACU is recorded in the transfer shift register 4 on the falling edge of the clock pulse arriving at the second synchronization input of the shift register 4

5 transmissions from the output of the element 17, In addition, to write the ACC to the register 4, it is necessary that the second control input of the register 4 contains a single signal from the third output of the decoder 10. The register

0 4 on the trailing edge of the clock pulse arriving at the first synchronization input from the output of the third element And 18, shifts the information by one bit to the right. Thus, AKU is converted from a parallel code to a serial code. To convert the ACC to a serial code, it is necessary that the first control input contains a single signal from the output of the And 19 element.

0 AKU bitwise enters the information input of the register 5 from the output of the multiplexer 8. Record the next bit of AKU in register 5 is carried out on the falling edge of the clock pulse from the output of the element And 18, the same sync pulse from the output of the element And 18 all information recorded in register 5 is shifted to the right by one bit.

The address multiplexer performs

0 transmission to its output from its first, second, third information inputs, respectively, either AKU (AKU) from the output of register 5, or a new operation code (Akop) from information input 20 of the operation code,

5 or the addresses of the next MK (Ao) from the output of field 1.4 of the address of the memory block 1 of microinstructions and the element OR 15. The first and second address inputs of the multiplexer 6 are received respectively: AKU transfer signal (yi) from output 5.1 of the register 5, micro standby signal the code of the next MP (y2) from the second output of the decoder of 10 states. The function implemented by address multiplexer 5 is described by the expression

Avyh U1 AKU + U2 Akop + U1 U2 Ao.

The multiplexer 7 logical conditions transmits the logical condition value from the input 24 logic levels to the output from its information inputs (in the case of reading the MC, branching the lower bit from the output of field 1.4 of the address of the memory block 1 micro-instructions). The multiplexer 7 logical conditions is controlled by the code of logical conditions (in linear MK it is zero), coming from the output of field 1.3 of memory 1 of microcommands. In addition, a zero signal is generated at the output of the multiplexer 7 if there is a single signal from the seventh output of the decoder 10 at its inverse control input.

The multiplexer 8 transmits to its output from its information input AKU from the input 28 of the waiting module. Multiplexer 8 is controlled by the module code, coming from the output of field 1.3 of memory 1 of micro-instructions. In addition, a zero signal is generated at the output of the multiplexer 8 in the absence of a single signal from the seventh output of the decoder 10 at the control input of the multiplexer 8.

The transmission demultiplexer 9 transfers to one of its outputs from its information input AKU from the register 4 output. The demultiplexer 9 is controlled by a code from the output of field 1.3 of memory 1 of microcommands.

The decoder 10 is designed to convert a three-bit code from the output of field 1.1 of memory 1 of micro-instructions into a unitary control code. From the second output of the decoder 10, the next MP code wait signal is read, which controls the operation of multiplexer 6. From the third output, the ACU transmission micro-operation signal is read, which is used to write the ACU to register 4. The ACU transmission wait signal is read from the fifth output. At the seventh output of the decoder 10, an ACU wait signal is generated. This signal goes to output 26.

The counter 11 is designed to count the number of cycles during which the module waits for either the Lth module to transmit an ACU to it, or a module to receive an ACU from it. Counter 11 increases its content by one on the falling edge of the clock pulse arriving at the counting input of counter 11c of the output of the second element And 17. If there is a signal at the control input of counter 11 from the output of the first discharge of field 1.1 of memory 1 of microcommands, counter 11 is set to the initial state of a single signal from the output of the lower bit of the register 2 addresses.

Comparison unit 12 is designed to compare the wait code from the field 1.2 of the microcommand memory 1 and the number of sleep cycles from the output of the counter 11 when the control input of the comparison block 12 contains a single signal from the first field 1.1 block 1 memory microinstructions. 5 The trigger trigger 13 controls the synchronization of the module. It is set to one by the start signal from input 20.1 of the device. A single signal from the output of the flip-flop 13 is fed to the first inputs of the elements AND 16, 18, allowing the passage of clock pulses through them from the corresponding outputs of the generator 29.

Trigger trigger 13 is set to zero (initial) state when it is received5 or to its R input of a single signal from input 20.2 of the device.

The device works as follows.

In the initial state, the generator 29 generates a sequence of clock pulses at the outputs 29.1, 29.2 and 29.3, and the pulse repetition period from the outputs 29.1 and 29.2 is k times longer than the pulse repetition period from the output 29.3 (Fig. 4).

5In the initial state, all elements of the device are in the standby mode of the operation code of the program level from the upper level control device. In this case, all memory elements are set to zero. The contents of the zero cell (with a zero address) are read from the memory block in accordance with the table - this is an E type MC. In its 1.1 field, a code is written (010), which is decoded by the decoder

5 10 signs as a signal of waiting for the code of the next MP. This single signal arrives at the second control input of the address multiplexer 6, which, according to the described operation algorithm, passes from its output to the information input of the address register 2 address operation code from input 20 of the module operation. In the field x 1.2, 1.3, 1.4 zero cells, zero codes are written. At the same time multiplexer 7 logical

5 conditions on the zero code of logical conditions from output 1.3 of the memory block 1 micro-instructions skip to its output the value of the low order from the output field 1.4 of the address of the block 1 memory micro-instructions. Zero ADD is constantly fed to the third information input of the multiplexer 6 address. In such an initial state, the control structure (Fig. 2) will be located before the arrival of the MP code from the upper level control device to the input 20.

Each device can operate in the following modes.

1. Standby code of the next MP. 2. Control mode. 3. AKU transfer mode. 4. Standby mode AKU.

The transition of the module from the initial state to the standby mode of the code of the next MP is carried out by the Start signal, which arrives at the device start input 20.1. From input 20.1, the Start signal is fed to the S-trigger input 13 of the trigger. A single signal from the direct output of the 13 start trigger opens the first 16, second 17 and third 18 elements AND, allowing the passage of clock pulses from the first 21, second 22 and third 23 inputs of the device, respectively. If at the time of occurrence on the synchronization path of register 2 the address of the considered device of the trailing edge of the first clock pulse from the output of the first element AND 16 at the input 20, the operation code has not yet been received, then the register 2 will be assigned a zero address and from memory unit 1 microinstruction read EK type E again. Since the zero code is written in its field 1.2 micro-operations, then on the falling edge of the clock pulse from the output of the second element I 17 the register 3 micro-operations will not change the state. From the second output of the decoder 10, the single signal of waiting for the code of the next MP will still be read. Thus, the device will indefinitely wait for the MP code at its input 20.

When an MP code appears at the device inputs 20, this code is written via the address multiplexer 6 on the falling edge of g 1 to the address register 2 and the module enters the control mode. From the memory block 1 of the micro-instructions, the first MC of the desired MP is read.

On the falling edge of the clock pulse G2 from the output of the second element I 17, the microoperation code of the first MC of the microprogram is recorded in the register 3 of the micro-operations (in the table MKTIPS).

On the falling edge of the next clock pulse from the output of the first element AND 16 into the register 2 from the output of the multiplexer 6 of the address, the address of the next MC of the microprogram is recorded. This address goes to the third information input of the multiplexer 6 addresses from the high-order bits of the field 1.4 of the microcommand memory block 1 (unmodifiable part) and the output of the OR 15 element (modified part).

In this mode, either linear MK or branching MK is read from microcomputer memory 1. In linear MK, the low-order bit of the next MK address in the MP is determined by the low-order value of the field 1.4 of the address of the memory block

1 microinstructions. In the field 1.3 of the logical conditions of linear MK recorded zero code. Under this code, the multiplexer 7 logic conditions skips to its output, according to

the algorithm of its operation, the value of the signal from the lower bit of the output of field 1.4 of the microinstructions memory block 1. In the BR of branching in field 1.3 of the memory of microcommands 1, a logical condition code is written, the value of which is analyzed when generating the address of the next MC. According to this code, multiplexer 7 passes from the input 24 logical conditions of the device to its output the value of the desired logical condition. AT

5, in the control mode, a single signal does not appear at the output of the comparison unit 12. Thus, in MK branching, the lower order bit of the address of the next MK in the MP will be completely determined by the value of the signal at the output of the multiplexer 7 logical conditions. The next linear MK or MK branching is read from the address recorded in register 2 from the memory 1 of micro-instructions. Similarly device

5 implements in the required sequence MK performed by the MP (operation).

From the control mode, the device can switch to any other mode.

When entering standby code

0 the next MP in the field 1.2 of the logical conditions code and the field 1.4 of the address of the format of the last MC executed; the MP is written down the zero code and in the next clock from the memory 1 of the microcommands is read zero

5 MK (MK type E), i.e. the device enters the previously described state of waiting for the code of the next MP. If it is necessary to transfer information to another system device, the device in question is from

0 control mode enters AKU transmission mode.

On the falling edge of the next clock pulse from the output of the AND 16 element (Fig. 4), the address MK is written to the address register 2.

5 of type A. At the third output of the decoder 10 of the feature, a single signal is generated, which is fed to the second control input of shift register 4, allowing ACU recording from the output of field 1.2 of the block

0 memory 1 microinstructions. The same signal from the third output of the tag decoder 10 through the first element OR 14 is fed to the first input of the fourth element AND 19. The logical condition code of the L-ro module arrives at the address input of the multiplexer 7 of the logic conditions. In case the L-th module is in the AKU standby state, then at the output of the multiplexer 7 logical conditions a single signal is formed, which is fed to the second input of the fourth

element And 19. A single signal from the output of the fourth element And 19 is fed to the first control input of shift-transfer register 4 and enables the conversion of AKY from a parallel code to a serial one. On the trailing edge of each clock pulse from the output of the third element And 18 there is a shift of the information recorded in the transfer shift register 4 by one bit. Thus, before the next clock pulse from the output of the first element AND 16, ACU is converted from a parallel code to a serial one.

The ACU in the serial code enters the information input of the transmission demultiplexer 9 and passes to the output that corresponds to the code L-ro of the module, which arrives at the address input of the transmission demultiplexer 9 from the output 1.3 of the logical conditions of the memory 1 microcommand.

Also, a single signal from the output of the multiplexer 7 logical conditions modifies the low-order bit of the address code field 1.4 of the memory block 1 of the micro-instructions, which is fed to the third input of the multiplexer 6 address. In addition, a single signal from the output of the third bit of field 1.1 of the microcommand memory unit is fed to the inverse control input of register 3 of the microoperation. Therefore, the ACU recorded in field 1.2 of the microinstructions memory block 1 in the Type A MC will not be recorded in register 3 of the micro ops. If the 1st module is not ready to receive an ACU, a zero signal is generated at the output of the multiplexer 7 logical conditions, which arrives at the second input of the fourth element And 19 and prevents the ACU conversion signal from passing through it from the parallel to serial code.

The zero signal from the output of the multiplexer 7 logical conditions arrives at the first input of the second element OR 15. In a Type A MC, the signal arriving at the second input of the second OR 15 element is always zero, therefore the low-order bit value of the next MC address is completely determined by the signal value at the first the input of the second element OR 15, therefore, the low-order code of the address code from the output of field 1.4 of the address of the memory block 1 of the micro-instructions 11 is not modified. As a result, at the third input of the multiplexer of address 6, an address of the type B MK is formed, which is written to the address register 2 from the output of multiplexer 6 by the next clock pulse from the output of the first element I 16.

In type K M, a single signal is generated at the output of the tag decoder 10, which is fed through the first

element OR 14 to the first input of the fourth element AND 19, a single signal from the output of the first bit of field 1.1 of the microcommand memory block 1 is fed to the control inputs of counter 11 and comparator unit 12. This signal allows writing to the standby counter 11 and the next the clock pulse from the output of the AND-element 17 by its falling edge increases by one the contents of the counter 10 of the chase 11. The code from the output of the counter 11 goes to the first information input of the comparison unit 12, the second information input of which contains the wait code from the output of the field 1.2 of the memory block 1 micro 5 mand.

If the L-th module still does not go into ACU standby mode, then at the output of the multiplexer 7 logical conditions there is a zero signal that inhibits the passage of a single signal through the fourth element And 19 and does not allow the ACU to be converted to a serial code in the transfer shift register 4 . Also a zero signal from the output of the multiplexer 7

5 logical conditions arrive at the first input of the second element OR 15. Thus, the low-order bit value of the address code of the next MC from the output of field 1.4 of memory 1 of micro-instructions completely depends

0 from the value of the signal at the output of the comparison block 12.

If the code from the output of the wait counter 11 does not coincide with the wait code from the output of field 1.2 of memory block 1 of microinstructions, then

5, the comparison unit 12 generates at its output a zero signal, which is fed to the second input of the first element OR 15.

The lowest bit of the next MK address from the output 1.4 of the microcommand memory block will not be modified, and the next time pulse from the output of the first element 16 will also register the address type MK in the address register 2, i.e. waiting for the L-ro module to transmit the ACU to it, At the same time

5 each time a type B MC is read, a single signal from the output of the first bit of field 1.1 of the microcommand memory block 1 allows writing to counter 11 and the next clock pulse from the output of the AND 17 element

0 with its falling edge increases by one the contents of the standby counter 11. Type B MC will continue reading until either the Lth module enters ACU standby mode, or the code from output 5 and counter 11 does not match the wait code at the output floor 1.2 memory block 1 microinstructions.

In the first case, if the L-th module went into ACU standby mode, then at the output of the multiplexer 7 logical conditions will be

a single signal has been generated that will allow the passage of a single signal from the output of the first element OR 14 and the conversion of the ACU recorded in transfer shift register 4 to a serial code. ACU in the serial code from the output of the transfer shift register 4 is fed to the information input of the transmission demultiplexer 9, which passes it to the output corresponding to the code received from the output of field 1.3 of microcommand memory 1 to the address input of the transfer demultiplexer 9.

Also, a single signal from the output of the multiplexer 7 logical conditions modifies the low-order code of the address code from the output of field 1.4 of the microinstructions memory block

I and the next clock pulse from the output of the first element And 16 in the address register 2 will write the address of the next MC. The wait counter 11 is zeroed by the low-order output of register 2 addresses.

In case the L-th module did not go into ACU standby mode, and the number of wait cycles of the L-ro module for transmitting ACU to it, i.e. exit counter code

If the code recorded in field 1.2 of memory 1 of the microinstructions of the N-ro module, then a single signal is generated at the output of the comparison block 12, which modifies the low-order code of the address of the next MC.

On the next clock pulse from the output of the element And 16 in the register 2 addresses will be recorded the address code of the next MC.

The wait counter 11 is set to the zero state by a single signal from the low-order output of register 2 addresses.

When reading type B MCs, the third bit of field 11 of memory 1 of microcommands contains a single signal that arrives at the inverse control input of register 3 of micro-operations and prohibits writing a wait code from field 1.2 of memory 1 of microcommands to register 3 of microoperations.

If it is necessary to obtain information from another device of the system, i.e. the transition to the ACU standby mode, in the field 1.1 of the format of the last MC (table, MC of type D) the code MP (III) is written, according to which the decoder 10 generates a signal at its seventh output micro-operation of waiting AKU.

This signal arrives at the output 26 of the device state and at the corresponding input bits of the 24 logical conditions of all devices in the system. In addition, a single signal from the seventh output of the decoder 10

the feature is fed to the control input of the multiplexer 8 and allows transmission to the output of the multiplexer 8 of the ACC in the serial code. The KODU device, from which AKU is expected, is recorded in field 1.3 of memory block 1 of microinstructions and arrives at the address output of a wait multiplexer 8.

Also, the signal from the seventh output of the decoder 10 of the feature is fed to the inverse control input of the multiplexer 7 logic conditions and prohibits the passage of signals from the input of 24 devices and the low-order field 1.4 of the microcircuit memory at the output of the multiplexer 7 logic conditions, i.e. at the output of the multiplexer 7 logical conditions, a zero signal is generated, t, o, in M-type D, the low-order bit of the address code of the next MC depends

0 only from the signal from the output of the comparison block 12.

A single signal from the output of the first bit of field 1.1 of memory block 1 of micro-instructions is fed to the control inputs

5 wait counter 11 and compare block 12 and allow writing to the wait counter 11. Another clock pulse from the output of the second element I 17 increases the content of the wait counter 11 by one. The single signal from the third bit output of field 1.1 of the microcommand memory It prohibits the recording into the register 3 of the micro-operations of the wait code that enters the information input of the register 5 of the micro-operations 3 from the output of field 1.2 of the memory block 1 of the micro-instructions.

The number of cycles of operation of the device during which it waits for ACU, determines the waiting code, which is recorded in field 1.2

0 MK type 0, and is fed to the second information input of the comparison unit 12. The first input of the comparison unit 12 receives the code from the output of the wait counter 11.

If the code from the output of the counter 11 wait

5 did not coincide with the code from the output of field 1.2 of memory block 1 of microinstructions, then the output of the comparison block 12 contains a zero signal that does not modify the low-order code of the address code from the output of field 1.4 of the memory block

0 microinstructions that arrive at the third information input of the address 6 multiplexer. In case if the next clock pulse ri arrives at the synchronization input of the register 2 addresses at the first input of the multiplexer 6, there is no single signal from the output 5.1 of the register 5 (i.e. Ne the device in this cycle of operation did not transmit ACU), then on the falling edge of n the address register G2 again will write the address

MK type D, i.e. the ACC wait cycle is repeated from the N-ro device. In this case, each time a type D MC is read, a single signal from the output of the first bit of field 1.1 of memory 1 of microcommands allows writing to the wait counter 11. The next clock pulse T2 with its falling edge increases by one the content of the wait counter 11.

If the code from the output of the wait counter 11 coincided with the wait code from the output of field 1.2 of the microinstructor memory, a single signal is generated at the output of the comparator unit 12, which modifies the low-order code of the address of the next MC from the output of field 1.4 of the microcommand memory, which is received to the third multiplex information input b. If by the arrival of the next sync pulse n at the input of the record of the address register 2 there is no single signal at the first input of the multiplexer 6 of the address, then on the falling edge of the sync pulse the address of the special micro subprogram (WFP) will be written into the address register 2.

The introduction of a special WFP into the system's device operation program is done to determine (if necessary) the reasons for the absence of AKU transmission by the Nth device to this device (failure of the N-ro device, Ne device performs a program section that does not provide for the transmission of AKU to this device, and .P.). If there is no need for the introduction of a special WFP, then the address of the next MC will be entered in register 2 addresses.

When reading from the register of the address of the special MSP or the address of the next MC, a single signal will be received at the input of the installation of the zero state of the wait counter 11 from the low register output of the 2 address register, setting the wait counter 11 to the zero state.

If Ne device transmits ACU to this device, AKU in serial code is fed to device input 28 corresponding to the Nth device, and through wait multiplexer 8 it arrives at information input of register 5, in which on the falling edges of clock pulses Hz, arriving from the output of the third element I 18 to the synchronization input of register 5, a bit is written to the AKU. To eliminate the distortion of the last bit of ACU, the register width 5 is one more than the ACU bit. The senior and minor bits of the ACU are always single. The occurrence of a single value at output 5.1 of register 5 indicates that the ACU is fully recorded in register 5 and converted from a serial code to a parallel one. This single signal from the output 5.1 of the register 5 5 goes to the first control input of the multiplexer 6 of the address, which, according to the functioning algorithm, passes to its output AKU from the first information input.

0 By the next clock pulse TIB

Claims (1)

the address register 2 from the output of the multiplexer of address 6 will be recorded by the ACU, according to which, from the memory of micro-instructions 1, the MC is considered necessary. In the same operation cycle, a single signal from the low-order output of the address registers is set to the zero state of the wait counter 11. The invention is a programmable control unit containing a microinstructions memory block, address registers and microoperations, address multiplexers and logic conditions, and a trigger trigger, the group of information inputs of the operation code being 5, the first group of information inputs of the multiplexer of the address, the first and second bits of the group of information inputs of the operation code of the multiplexer of the address are connected respectively to the installation and 0 by the trigger trigger inputs, the third bit of the first group of information outputs of the microinstructions memory block is connected to the inverse of the enable register of the microoperations, the outputs of which are 5 by the group of information outputs of the device micro-operations, the second group of information outputs of the microcommand memory block is connected to the information inputs of the register of micro-operations, 0 one third group of information outputs of the microinstructions memory block is connected to the address inputs of the multiplexer logical conditions, the fourth group of information outputs of the memory blocks 5 micro-instructions are connected to the second group of information inputs of the address multiplexer; the low bit of the fourth group of information outputs of the micro-memory block is the low-order bit 0 groups of information inputs of logical conditions of a device, which are connected to information inputs of a multiplexer of logical conditions, information outputs of an address multiplexer are connected 5 with the information inputs of the address register, the higher bits of the information outputs of which are connected to the address inputs of the microcommand memory block, characterized in that, in order to increase the reliability and expand the field of application of the device, the transmission shift and idle shift registers are added, the multiplexer , transmission multiplexer, attribute decoder, wait counter, comparison unit, first and second elements OR, first, second, third and fourth elements AND, the output of the last connected to the first input The resolution of the transfer shift register, the output of which is connected to the information input of the transmission demultiplexer, the outputs of which are information outputs of the device transmission, the first group of information outputs of the microcommand memory block is connected to the information inputs of the attribute decoder, the first output of which is connected to the first address input of the multiplexer addresses, the first bit of the first group of information outputs of the microcommand memory block is connected to the information inputs of the tag decoder, the first output D which is connected to the first address input of the address multiplexer, the first bit of the first group of information outputs of the microinstructions memory block is connected to the inputs of the idle counter and the comparison block, the output of which is connected to the first input of the second OR element, the output of which is connected to the lower bit the second group of information inputs of the address multiplexer, the second group of information outputs of the microcommand memory block connected to the second group of information inputs of the comparison block and the group of information inputs in the shift shift register, the third group of information outputs of the microcommand memory block is connected to the address inputs of the transfer demultiplexer and the wait multiplexer, the output of which is connected to the information input of the standby shift register, the higher bits of the information outputs of which are connected to the third group of information inputs of the address multiplexer, and the youngest the bit of the information register of the register of the shift of waiting is connected to the second address input of the address multiplexer, the first, second and third inputs of synchronization device are connected respectively with the first inputs of the first, second and third elements And, the output of the start trigger is connected to the second inputs of the first, second and third elements And, the output of the first element And is connected to the input of the address register, the lower bit of the information outputs of which is connected to the input reset the wait counter, the information outputs of which are connected to the first group of information inputs of the comparison unit, the output of the second element I is connected to the input of the direct count of the wait counter, to the write input p the micro-operation gistra and the read register of the shift register, the output of the third element I are connected to the inputs of the write register of the shift shift and the register of the transfer shift, the output of the logic condition multiplexer is connected to the first input of the fourth element AND and the second input of the second element OR, the second output of the attribute decoder is connected to the inputs permit multiplexers and logic conditions and is the control output of the device state, the third output of the attribute decoder is connected to the second input of the resolution reg The shift source and the first input of the first OR element, the output of which is connected to the second input of the fourth AND element, the fourth output of the attribute decoder, is connected to the second input of the first OR element, the information inputs of the wait multiplexer are device information inputs. Object Uprabsh BUT C Start j To fig.Z