SU1649539A1 - Device of microprogramm control - Google Patents

Abstract

The invention relates to automation and computer technology and can be used as an ACS controller for technological processes. The aim of the invention is to increase the reliability of the operation of the device by monitoring the correctness of the sequence of logical conditions. The proposed device provides microprogram control of computing systems. This ensures reliable control of the initial state of the control device and the use of control results in the further operation of the device, increases the control efficiency and reduces the memory size of the control device. The device contains a block of permanent memory, address registers, micro-operations, start trigger, switch, first multiplexer, clock generator, element OR, demultiplexer, register of logical conditions, second multiplexer, unit adders modulo two, element And, first and second triggers control, error trigger. 2 Il. (Ls

Description

The invention relates to automation and computer technology and can be used as an ACS controller for technological processes.

The aim of the invention is to increase the reliability of the operation of the device by monitoring the correctness of the sequence of logical conditions.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - an example of the algorithm is presented.

The device contains a block of 1 constant memory, address registers 2 and 3 micro-operations, trigger 4 start, switch 5, the first

multiplexer 6, clock generator 7, element OR 8, demultiplexer 9, register 10 of logic conditions, second multiplexer 11, unit 12 modulo-two adders, element 13, first 14 and second 15 control triggers, error trigger 16, code input 17 operations, output 18 micro-operations, input 19 external stop, input 20 start the device, output 21 errors.

The device can operate in three modes: Training, Control and Management.

Training mode is intended for recording in accordance with the firmware.

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information in the memory (register of logical conditions) about the initial state of the device with that. in order to be able to use this information in the course of the implementation of subsequent micro programs.

The control mode is designed to verify that the recorded information in the register of logical conditions is consistent with logical conditions at the input of the device. The Control mode firmware can either repeat the firmware Tutorial (instead of feature ai, feature 32 is used, see Fig. 1), or it can be different. By this is meant that the order of execution of micro-commands in the firmware of the Control program may not coincide with the order in the firmware of the Training program, and also the correctness of the recording of not all logical conditions, but only some of them, can be controlled. However, it should not be addressed to logical conditions not used in the Training firmware, since this can lead to an erroneous device shutdown and an Error signal being issued. The Control mode must follow the Training mode, because over time the values of the logical conditions change and a large time gap between these modes may also lead to an erroneous device shutdown and an Error signal, or in the Control mode logical conditions must be used. occurs much slower than the operating time of the device. The Monitoring mode also provides indirect information about the correct functioning of the control device as a whole,

Control mode - the basic mode of the device is designed to control an object using micro-operations sent in accordance with the firmware stored in the device's memory.

In the Operation mode, the Control in microcommands of the branch can use the sign 32 (control) if the monitored logical condition was used in the Training mode and its value in comparison with the device operation time changes slowly. This increases the reliability of the device and does not affect its operating time.

8, the initial state, all the memory elements are set to O. In the single state, there is only one trigger register 3, which corresponds to the output

micro-operations of the End of a command, (The setting circuit of the initial and similar states is conventionally not shown).

The operation of the device begins after the arrival at the input 20 of the Start signal, by which the trigger 4 start is set to one.

On the first clock pulse from output 7.1 of generator 7, the code from input 17 is entered into register 2. This code is written to register 2 via switch 5, to the control input of which a single signal is output from register 3 of micro-operations

In memory block 1, a micro-command is formed that corresponds to the incoming address, in field 1 2 of which the sign ai of the mode Learning trigger 14 is set to one and the register 10 is ready to receive information

Then, a micro-operation code is entered into the register 3 by the clock pulse from the output 7.2 of the generator 7. A single signal at the output of the end of the register command 3 disappears at the falling edge of this pulse and the second information input is read from the next clock pulse by the next microcommand read from the output 1 5 block 1 (non-modifiable part of the address), and output 1 4 through multiplexer 6 (the modified part) is written to register 2 addresses

On the second clock pulse, micro-operation codes are entered into register 3 and then the device continues to work as described.

In branch microcommands, the code of logical conditions comes from the field 1 3 of block 1 to multiplexer 6 and modifies the lower address bit according to the value of the logical condition

Also, the logical condition code goes to the address input of the demultiplexer 9, which passes the sync pulse 7 1 to those outputs of the demultiplexer whose number is specified in the logic conditions code. Since the outputs of the demultiplexer 9 are connected to the synchronous inputs of the register 10, then the register 10 will record all values of the logical conditions used by this firmware. The data arriving at the second information input of the multiplexer 6 informs about the initial state of the control unit. In the last microprogram command there is a command end sign that sets the corresponding trigger of micro-register 3 to the single state, a single signal goes to the control

switch input 5 and prepares it to receive a new opcode.

Thus, in this mode, the initial state of the object is fixed (identified) before the start of all operations. In this mode, the Control at output 1.2 of block 1 of memory forms symptom 32. With this sign, control trigger 15 is set to one and allows information to pass through multiplexer 11. In the branch micro-commands, the code of logical conditions from field 1.3 of block 1. enters the address of the multiplexer 11, forms the value from the output of that adder modulo two, the number of which corresponds to the received code. Therefore, during the execution of the firmware, all and only modulo adders will be polled, the numbers of which correspond to the addresses of the logic conditions used in this firmware. If the output of the multiplexer 11 is Vits one, which corresponds to an error, then the error trigger 16 is set to one and an error signal appears at output 21, then a single signal passing through the OR element 8. The start trigger 4 is set to O, the generator 7 clock pulses stop working. If the values of the logic conditions match during the firmware control repetition process, the switch 5 is set to be ready to receive the next opcode by a sign of the end of the command.

Mode of operation The control is the main mode of operation of the device. In this mode, signs ai and 32 are not generated, and therefore the recording of logical conditions in register 10 and their passage through multiplexer 11 does not occur.

The rest of the algorithm of the device is similar to that described in the Training mode.

Upon the arrival of the last microcommand of the latest microprogram, at the output of the end of operation trigger in register 3, a unit is formed that passes through the OR element 8, enters the zero input of trigger 4, and the device stops working.

Claims (1)

Invention Formula A firmware control device containing a block of permanent memory, address registers and micro-operations, a switchboard, a first multiplexer, a start trigger, an error trigger, a clock generator, an OR element, and the device start input is connected to a setup input of 1 trigger trigger, the output of which connected to the trigger input of the clock generator, the first and second outputs of which are connected respectively to the synchronization inputs of the address register and micro-operations register, the input of the operation code of the device and the sign output. The end of the micro-operations register command is respectively connected to the first information control inputs of the switch, output 0 which is connected to the information input of the address register, the output of which is connected to the address input of the block of permanent memory, the outputs of the fields of micro-operations, the logic condition code, modified The 5 bits of the address and the unmodifiable bits of the address are respectively connected to the information input of the register of microoperations, the control and the first information input of the first 0 multiplexer, high bits of the second information input of the switch, the output of the first multiplexer is connected to the low-order bit of the second information input of the switch, register output 5 microoperations is the output of the device microoperations, the sign output. The end of the operation of the microoperation register and the device stop input are connected respectively to the first and second inputs of the OR element, the output of which is connected to the installation input in the Start trigger input, the logical conditions input of the device is connected to the second information input The first multiplexer, characterized by 5 that, in order to increase the reliability of the operation by checking the correctness of the sequence of logical conditions, the device further comprises a demultiplexer, a register of logical 0 conditions, modulo-two adders, second multiplexer, first and second control triggers, AND element, the output field of the logic code of the constant memory block is connected to the control inputs of the demultiplexer and the second multiplexer, the first and second outputs of the operation mode The fixed memory unit is connected to the installation inputs in G of the first and second control flip-flops, the output of the first control flip-flop is connected to the write enable input of the register of logical conditions, the output of which is connected to the first input m block adders modulo two and third 5 by the information input of the first multiplexer, the first output of the clock generator is connected to the first input of the element AND and the information input of the demultiplexer, the outputs of the higher bits of the demultiplexer are connected bit by bit with synchronization inputs of the register of logical conditions, the input of the logical conditions of the device is connected to the information input of the register of logical conditions and the second input of the modulo adders block, the output of which is connected to the information input of the second multiplexer, the output of the second multiplexer is connected to the installation input of 1 error trigger, the output of which P connected to the output of the device error and the third input of the OR element, the output of the output. The end of the micro-register register command is connected to the second input of the AND element, the output of which is connected to the installation inputs O of the first and second control triggers, the output of the second control trigger is connected to the gate input of the second multiplexer. to go nom  and .4.1 M