JP2583056B2 - IC test system - Google Patents

Description

The present invention relates to an IC test system having a distributed architecture having a hierarchical structure.

[Prior Art] FIG. 4 is a diagram showing a configuration example of a conventional IC test system. In the IC test system, a program in which a test sequence for testing a device under test is described is stored in a storage device (not shown), and the central processing unit 11 reads out the test program from the storage device and sequentially executes the test program. The central processing unit 11 controls all test operations for testing a semiconductor memory device, for example.

The hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 through control lines 12, and the control signals output as the central processing unit 12 decodes and executes the test program are those hardware signals. Module 13A,
13B, 13C to 13N.

The control signal is, for example, a control signal for supplying a DC signal of 5.25 V to a predetermined input terminal of the device under test, and when the control signal is supplied, for example, the hardware module 13A operates at a 5.25 V Is supplied to a designated input terminal of the device under test.

The control signal output from the central processing unit 11 is, for example, a control signal for instructing to measure a signal, and is, for example, a hardware module 13B for measuring a DC voltage.
When this control signal is supplied, it is connected to the designated output terminal of the device under test and measures its signal voltage.

The hardware modules 13A, 13B, 13C to 13N may incorporate the microprocessor 14. Even if a large number of logic elements are required when a test circuit is assembled using only general-purpose logic elements, the circuit board can be made compact by assembling many parts of the logic circuit with the microprocessor 14. In this case, the microprocessor 14 is merely a substitute for a logic element, performs only a predetermined sequence control, and is not generally used in a manner that requires a complicated judgment function.

"Problems to be Solved by the Invention" The central processing unit decodes and executes a program, that is, outputs a control signal for performing a test of the device under test to a hardware module and the like, and a signal output by the device under test. It is necessary to perform all kinds of arithmetic and control required for the operation of the IC test system, such as measurement of the measurement and judgment of the quality of the measurement result.

For example, when a voltage signal described in a test program is supplied to a device under test, the central processing unit supplies the digital data value to a hardware module or measures an output signal of the device under test. In some cases, the obtained measured value is corrected and converted as necessary, and may be compared with a predetermined judgment table to judge the quality or rank.

Therefore, the arithmetic processing time required by the central processing unit becomes longer, and the test speed of the test system cannot be easily increased.

When special processing is temporarily performed during execution of a predetermined program stored in the storage device, the temporary processing program is written into the storage device, and the written temporary program is added to the central processing unit. Special processing can be performed by shifting the execution of. However, such extraordinary processing requires complicated control steps, and the processing efficiency is poor.

Also, in an IC test system, if all system control is assigned to one central processing unit, the test speed becomes slow. Therefore, a distributed processing system configured using a plurality of processing units can be considered. In such a distributed processing device system, when a certain processing device, for example, a main processing device causes another processing device to execute a temporary program, the temporary program is stored in a shared storage device or a storage device attached to the target processing device. And the target processing apparatus can read and execute the written program. Even in this case, the temporary program is written in an empty area of the storage device, the execution of the target processing device is shifted to the written program, and when the execution ends, the process returns to the original control program. However, there is a problem that it is necessary to go through complicated control steps, and the execution efficiency of the temporary processing is reduced.

"Means for Solving the Problems" The IC test system of the present invention includes an instruction for setting a control signal to an input terminal of a device under test and an instruction for measuring an output signal from an output terminal of the device under test. A higher-level processing unit that reads a test program recorded in units of lines and sends the read instruction to a plurality of lower-level processing units, and is required to execute the instructions sent from the higher-level processing unit. A plurality of lower processing units that perform various controls and processes on a plurality of hardware modules by reading a program corresponding to the instruction; and a device under test according to the controls and processes from the lower processing units. The plurality of hardware modules for connecting a test signal to or measuring output signals of a plurality of devices, and the plurality of lower-level processing devices send the instructions. In addition to having a general-purpose storage device in which a program required for execution is stored, an auxiliary storage device which has a smaller capacity than the general-purpose storage device, is always written from a specific address, and is executed from the specific address is provided. Have.

According to the configuration of the present invention, the higher-level processing device controls the execution of the test program on a line-by-line basis, and the actual decoding and execution of the program line are distributed by a plurality of dedicated processing devices. Done.

Further, according to the configuration of the present invention, it is possible to efficiently change the execution of the predetermined control program to the temporary or temporary execution of the program while the lower processing apparatus is executing the predetermined control program.

Embodiment FIG. 1 is a block diagram showing a configuration example of an IC test system according to the present invention. In this example, the IC test system is configured to control the execution of a test program stored in a storage device by a higher-level processing device 21, and to execute a program line under the control of the higher-level processing device 21 via a control bus 22. A plurality of lower processing units 23A, 23B, 23C to 23N that actually execute
And control lines 24 to these lower processing units 23A, 23B, 23C to 23N.
Hardware modules 25A, 25B, 25C to 25N controlled through A, 24B, 24C to 24N are hierarchically configured.

That is, in the test program for testing the device under test, the procedure of the test is described in units of rows, and the host processor 21 sequentially reads the test programs from the storage device in units of rows and controls execution of the read program lines. .

The upper processing device 21 includes a plurality of lower processing devices 23A,
23B, 23C to 23N are connected, and the host processor 21 determines whether to execute the read program line while observing the test state of the device under test, and the actual execution of the program line determined to be executed is lower. Processing units 23A, 23B, 23 connected to
C to 23N.

Each of the lower processing units 23A, 23B, 23C to 23N is a dedicated processing unit suitable for controlling a test signal for the device under test, and a hardware module connected thereto.
It has a command language system that is convenient for accessing any of 25A, 25B, 25C to 25N, and changing the test status (terminal connection and measuring instrument status), and is converted into a macro command. Therefore, the host processor 21 is configured so as to obtain a processing speed several tens of times faster than directly performing the same processing on the hardware modules 25A, 25B, 25C to 25N by using its own instruction word system.

Each lower processing unit 23A, 23B, 23C to 23N is a higher processing unit
When the execution of the program line is commissioned from 21, the program line is decrypted and the program line is executed. That is,
Each of the processing units 23A, 23B, 23C to 23N holds a control program in which a procedure for inputting / outputting a test signal to / from the device under test is stored in the storage device 27, and controls the control program based on a decoding result of a given program line. The program is read from the storage device 27 and the procedure for controlling the input / output of the signal described in the program row is executed.

Further, each of the processing devices 23A, 23B, 23C to 23N is a higher-order processing device.
Not only the program line for which execution has been commissioned from 21 is executed as it is, but also the program line is deciphered, and the deciphered result is given to the function condition in which information is given in advance to the device under test, for example, Check the clock width, input conditions, timing relations, prohibition conditions, etc., and make judgments so as not to give an incorrect input signal or to put into a signal state that may cause damage to the device under test. It also controls to output a test signal to the test element or measure the output signal.

On the other hand, each hardware module 25A, 25B, 25C to 25N is supplied with a control signal accompanying the execution of a program line of each of the lower processing units 23A, 23B, 23C to 23N, and is supplied to a designated input terminal of the device under test. To output a test signal or measure a signal from a specified output terminal of the device under test.

The hardware modules 25A, 25B, 25C to 25N may include a microprocessor 26. The microprocessor 26 replaces a large number of logic elements and performs a predetermined sequence that does not require complicated judgment. As the microprocessor 26, a general-purpose processor is used, the operation of which is programmed in advance, and the input / output of signals to / from the device under test can be controlled by instructions from the processing units 23A, 23B, 23C to 23N.

As described above, each of the lower processing units 23A, 23B, 23C to 23N executes all of the actual processing of the test on the device under test under the control of the upper processing unit 21, and the upper processing unit 21 The entire IC test system is controlled to operate organically, such as execution control of program lines of the processing devices 23A, 23B, 23C to 23N and collection of test pass / fail judgment results.

Further, in the present invention, each of the lower processing units 23A, 23B, 23C to 2C
In 3N, in addition to storage devices 27A, 27B, 27C to 27N in which a control program for actually decoding and executing a program line given from a higher-level processing device 21 is stored, as well as an auxiliary storage device 28A, respectively. , 28B, 28C to 28N are provided, and a temporary program can be written into the respective auxiliary storage devices 28A, 28B, 28C to 28N from the higher-level processing device 21.

FIG. 2 is a configuration diagram showing an example of a main part of the present invention. The lower-level processing device 23 is provided with a general-purpose storage device 27 and an auxiliary storage device 28. The general-purpose storage device 27 includes a host processor 21.
A control program for controlling the hardware modules 25A, 25B to 25N is stored when executing the program line given from the storage device, while the auxiliary storage device 28 is a small-capacity storage device and changes the control by the control program. Temporary programs are temporarily stored. The temporary program is sent to the host processor via the control bus 22.
The data is supplied from the memory 21 and can be written from a specific address of the auxiliary storage device 28, for example, address 0.

The lower-level processing device 23 reads out the temporary program from a specific address of the auxiliary storage device 28, for example, address 0, and executes it. Accordingly, the lower-level processing device can immediately execute the temporary program without executing the temporary program without having to save the address and set a new address. Can be performed promptly.

FIG. 3A is a diagram showing a flowchart of the temporary processing according to the present invention. That is, the upper-level processing device 21 does not need to search for the address of the temporary program to be written to. The auxiliary storage device 28 held by the target lower-level processing device 23 is: ) Write a temporary program from.

: When the predetermined writing is completed, the lower processing device 23 is instructed to execute the temporary processing.

The temporary rewriting function of the program can be arbitrarily performed even during the execution of the test on the device under test. The test may be performed while changing the test conditions or the like according to the state of the device under test during the test. For example, when it is desired to determine the next test condition in accordance with the measurement value obtained during the test operation, the program changed in accordance with the measurement value can be written in the auxiliary storage device 28 to cope with it. .
Further, for example, it may be desired to change the test conditions for the device under test for every certain number of units. Even in such a case,
By writing the changed program only when testing the predetermined number of devices under test, a special test distinguishable from the others can be imposed.

On the other hand, FIG. 3B is a flowchart showing the temporary processing when the auxiliary storage device 28 is not provided. That is, the upper-level processing device 21 calls and executes a memory management routine in order to know in which area of the general-purpose storage device 27 the temporary program should be written. That is: Search for a free memory area remaining in the general-purpose storage device 27 in the memory management routine.

: Set the assigned address.

: The temporary program is written into the general-purpose storage device 27 while the address is being incremented.

: When the predetermined writing is completed, the execution address is transmitted to the lower order processing device 23 to instruct execution of the temporary processing.

As described above, if the auxiliary storage device 28 of the present invention is provided, it is clear from the comparison between the two flowcharts that the control of the IC test system can be easily and efficiently changed.

Further, according to the configuration of the present invention, the change program can be easily written from a higher-level processing device into the auxiliary storage device, and the control program can be debugged in real time. There is also an advantage that it becomes possible.

[Effects of the Invention] As described above, according to the present invention, a higher-level processing device exclusively controls execution of a program line, and actual execution of a program line is distributed to a plurality of lower-level processing devices. The configuration based on the hierarchical structure performed is adopted. With such a distributed architecture, we can improve processing speed,
An optimum instruction word system is used for each layer, processing until a control signal is output becomes very fast, and a test operation on a device under test can be performed at high speed.

Further, according to the configuration of the present invention, it is possible to change the test process according to the situation while executing the test on the device under test without substantially reducing the test speed. Can be executed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a main part of the present invention, FIGS. 3A and 3B are a flowchart of the present invention relating to temporary processing and a conventional flowchart, and FIG. FIG. 1 is a diagram showing a configuration example of a conventional IC test system. 11: Central processing unit, 12: Control line, 13: Hardware module, 14: Microprocessor, 21: Host processing unit, 2
2: control bus, 23: lower processing unit, 24: control line, 25: hardware module, 26: microprocessor, 27: general-purpose storage device, 28: auxiliary storage device.

Claims (1)

(57) [Claims] 1. A test program in which an execution command such as a command for setting a control signal to an input terminal of a device under test and a command for measuring an output signal from an output terminal of the device under test is recorded in a line unit. A high-level processing device that sends the read instruction to a plurality of low-level processing devices; and a control or process required to execute the instruction sent from the high-level processing device. A plurality of lower-level processing units that read and execute the plurality of hardware modules; a test signal is connected to the device under test according to control or processing from the lower-level processing device; A plurality of hardware modules for measuring signals, and the plurality of lower-level processing units are general-purpose storages storing programs necessary for executing the transmitted instructions. Besides, a small capacity than the general storage instrumentation, always written from a particular address, also IC test system comprising an auxiliary storage device to be executed from that particular address that includes a location.