JP2627751B2 - IC test system - Google Patents

Description

The present invention relates to an IC test system having a distributed architecture having a hierarchical structure.

[Prior Art] FIG. 4 is a diagram showing a configuration example of a conventional IC test system. In the IC test system, a program in which a test sequence for testing a device under test is described is stored in a storage device (not shown), and the central processing unit 11 reads out the test program from the storage device and sequentially executes the test program. The central processing unit 11 controls all test operations for testing a semiconductor memory device, for example.

The hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 via control lines 12, and the control signals output as the central processing unit 11 decodes and executes the test program are Hardware module 13A,
13B, 13C to 13N.

The central processing unit 11 has hardware modules 13A, 13B, 13
In order to control C to 13N according to a program, it is necessary to know the states of the hardware modules 13A, 13B, 13C to 13N. Therefore, each hardware module 13
The current state of A, 13B, 13C to 13N is recorded, and the control is advanced while examining the state. The state is, for example,
The connection destination of the pins of the hardware modules 13A, 13B, 13C to 13N, the output voltage of the signal, the state of the measurement range of the signal, and various other states.
Has data indicating these states in the storage device in the status table 16 collectively.

During the control of the test sequence, the central processing unit 11 records the control state in a corresponding part of the status table 16 when outputting a control signal to the hardware modules 13A, 13B, 13C to 13N. The status table 16 always contains the hardware modules 13A, 13B, 13
The latest status of C ~ 13N is recorded.

For example, the control signal for the hardware module 13A is a control signal for supplying a DC signal to the input terminal of the device under test, and
When the data of the control signal is recorded in 16A and this control signal is supplied, for example, the hardware module 13A supplies a specified DC signal to a specified input terminal of the device under test.

The control signal output from the central processing unit 11 is, for example, a control signal for instructing to measure the signal, and checks the status table 16 to find an empty hardware module 13B, and uses the corresponding module 16B in the corresponding column 16B. And then outputs a control signal. For example, a hardware module for measuring DC voltage
When the control signal is supplied, 13B is connected to a designated output terminal of the device under test, and measures the output voltage of that terminal.

"Problems to be Solved by the Invention" The central processing unit decodes and executes a program, that is, outputs a control signal for performing a test of the device under test to a hardware module and the like, and a signal output by the device under test. It is necessary to perform all kinds of arithmetic and control required for the operation of the IC test system, such as measurement of the measurement and judgment of the quality of the measurement result. In particular, in order to perform a DC test at high speed on a semiconductor device having a large number of input / output terminals, rapid processing control in each unit is required.

In addition, the number of hardware modules that need to be controlled is large, and the size of the status table that records the status is very large.

FIG. 5 is a flowchart showing an example of processing for checking the status table.

: Set the mode update flag to the initial state (f = 0, i =
1).

: Retrieve the status of one hardware module from the status table.

: Check the status. For example, is it necessary to change the mode (supply the test signal or measure the test signal)?

: If there is a mode change, the mode is updated and the mode update flag is set (f = 1).

: Select the next hardware module to be processed (i = i
+1). When the processing for all the hardware modules is completed (i = N), the process returns to the next step, or returns to the step if not completed.

: If the mode update flag is set (f =
1), perform exception processing.

As described above, the central processing unit fetches the status of each hardware module from the status table and controls the hardware module while checking the status, but the time required to check the status is determined by the size of the table. For example, a longer time is required in proportion to the increase. Therefore,
The time to check the large status table and change the contents of the status is not negligible. For example, in the worst condition, it may take 2 ms, which is an obstacle in improving the operation speed of the IC test system.

[Means for Solving the Problem] According to the present invention, an IC test system adopting a hierarchical structure by using a plurality of processing devices is configured, and a test program instruction for controlling operation of a hardware module is executed by a program line. The higher-level processing device controls the execution in units, and the actual decoding and execution of the control content described in the program line is entrusted to the lower-level processing device controlled by the higher-level processing device.

Further, each lower-level processing device is provided with a dedicated storage device for storing a status relating to each connected hardware module, and is provided with an instruction for updating the status and checking the status. The lower processing device accesses the hardware module using the dedicated instruction or updates the test status.

According to the configuration of the present invention, the higher-level processing device controls the execution of the test program on a line-by-line basis, and the actual decoding and execution of the program line is performed by a plurality of dedicated dedicated lower-level devices. This is performed in a distributed manner by the processing device.

Checking of status information indicating the state of the hardware module is performed by each of the lower processing units in a distributed manner, and the processing is promptly performed by using a dedicated instruction.

Embodiment FIG. 1 is a diagram showing a configuration example of an IC test system according to the present invention. This IC test system employs an architecture in which a plurality of processing devices have a hierarchical structure. That is, the IC test system of the present invention is particularly adapted to perform a DC test, for example, an input outflow current, a leak current, a withstand voltage, a threshold voltage test, and the like. That is, a higher-level processing device 21 that controls execution of a test program instruction for each row that controls the operation of a hardware module stored in a storage device, and a higher-level processing device
21 via a control line 22, and a higher-level processing device 21
A plurality of lower processing units 23A, 23B, 23C to 23N that actually execute program lines under the control of
Hardware modules 25A, 25B, 25C to 25N controlled by control buses 24A, 24B, 24C to 24N on 23A, 23B, 23C to 23N. Here, the program line refers to one line in which a control instruction program of a macro IC test system is described and expressed in units of lines. A plurality of instructions are registered at once, a new name is given to the plurality of instructions registered at once, and a plurality of instructions registered at once are designated by specifying a new name. Instructions are executed consecutively. The plurality of instructions registered together are called a macro instruction. A specific example of describing and executing a program of a control instruction of a macro IC test system in units of lines will be described later in detail.

That is, in the test program for testing the device under test, the test procedure is sequentially described in units of rows, and the higher-level processing device 21 sequentially reads the test program from the storage device in units of rows, and executes the read program line. Control whether or not.

Therefore, the higher-level processing device 21 must easily create a test program for a desired device under test by the user, and must perform all kinds of processing related to the IC test system. For this purpose, a general-purpose instruction word system is used.

The upper processing device 21 includes a plurality of lower processing devices 23A,
23B, 23C to 23N are connected, and the host processor 21 determines whether to execute the read program line while observing the test state of the device under test, and the actual execution of the program line determined to be executed is lower. Connected lower processing units 23A, 23
B, 23C to 23N.

Each of the lower processing units 23A, 23B, 23C to 23N is dedicated to supply a signal to the device under test via the hardware module 25A, 25B, 25C to 25N or to control the measurement of the signal. Is used to access any of the hardware modules 25A, 25B, and 25C to 25N connected to them, and to change the test status (terminal connection and measurement device status). It has a convenient command language system,
Moreover, it is made into a macro instruction. Therefore, the host processor
When the same processing is performed with the instruction word system used in 21, the processing speed is several tens times faster.

Each lower processing unit 23A, 23B, 23C to 23N is a higher processing unit
When the execution of the program line is requested from 21, the program line is decrypted and the execution of the program line is started. That is,
Each of the lower processing units 23A, 23B, 23C to 23N holds a control program in which a procedure for inputting / outputting a test signal to / from the device under test is stored in a storage device (not shown). The input / output control program is read based on the result of decoding the program line, and the procedure for controlling the input / output of the signal described in the program line is executed.

In addition, each of the lower processing units 23A, 23B, 23C to 23N not only executes the program line commissioned to be executed by the upper processing unit 21 as it is, but also decodes the program line and responds to the decoding result. Check the functional conditions for which information is given in advance to the device under test, for example, the minimum clock width, input conditions, signal timing relationships or prohibition conditions, etc. The program is programmed to control the supply of a test signal to the device under test or the measurement of the output signal while determining not to fall into a signal state that may cause damage to the device under test. That is, the lower processing units 23A, 23B,
23C to 23N perform limited processing, that is, in this IC test system, only control the hardware modules 25A, 25B, 25C to 25N, and a dedicated instruction capable of performing the control at high speed is configured. In addition, each of these lower processing units 23A, 23
B, 23C to 23N are configured to perform unified control processing instead of performing a test on the device under test separately.

The hardware modules 25A, 25B, 25C to 25N are supplied with control signals associated with the execution of the program lines of the lower processing units 23A, 23B, 23C to 23N, and supply test signals to designated input terminals of the device under test. It can output or measure a signal from a designated output terminal of the device under test.

The hardware modules 25A, 25B, 25C to 25N may include a microprocessor 26. The microprocessor 26 replaces a number of logic elements and performs a predetermined sequence operation without a complicated judgment function. As the microprocessor 26, a general-purpose processor is used, the operation of which is programmed in advance, and the input / output of signals to / from the device under test can be controlled by instructions from the processing units 23A, 23B, 23C to 23N.

As described above, each of the lower processing units 23A, 23B, 23C to 23N executes all of the actual processing of the test on the device under test under the control of the upper processing unit 21, and the upper processing unit 21 Only the control of the organic operation of the entire IC test system, such as the execution control of the program lines of the processing devices 23A, 23B, 23C to 23N and the collection of the test result pass / fail judgment results.

Further, in the present invention, for each of the lower processing devices 23A, 23B, 23C to 23N hierarchically configured in this manner, dedicated memories 27A, 27B, 27C to 27N are provided respectively. For example, the first lower processing unit 23A has a status table 27A, and the hardware modules 25A1, 25A2 to 25A.
Manages information about 25An.

FIG. 2 is a diagram for explaining a main part of the present invention.
Although not shown in this figure, the lower processing unit 23A is connected to hardware modules 25A1, 25A2 to 25An by a control line 24A, and is configured to take control of the hardware modules 25A1 and 25A2 to 25An according to a command from the upper processing unit 21. Is done. That is, the lower-level processing device 27A has a dedicated status table 27A, and the status table 27A has hardware modules 25A1, 25A2 each of which is assigned to control by the lower-level processing device 23A.
Status about ~ 25An can be stored. For example, status of the hardware module 25A2 is stored in the S ₂ address of the status table 27A to S ₃ -1 address. For example, the status is a signal supply mode or a signal measurement mode, an output range, a measurement range, a connection terminal number, an in-use flag, etc., and the lower processing device 23A uses the status table 27A to read the hardware modules such as these. Grasp the status of 25A1,25A2 ~ 25An,
Can be managed.

For example, if the status check or the update process is performed by a general-purpose instruction for performing general data processing or the like as in the higher-level processing device 21 which is a general-purpose processing device, program steps described in many instruction words are performed. To extract the status representing the state stored in the status table, that is, the bit pattern for each of the hardware modules 25A, 25B, 25C to 25N one by one, and illuminate / check those "0" or "1". . Such processing is performed by, for example, 128 hardware modules 25A and 25A.
If B, 25C to 25N are checked individually one after another, an enormous amount of time is required for the processing.

However, in the present invention, these statuses are shared by the plurality of lower-level processing devices 23A, 23B, 23C to 23N to perform check and update processes simultaneously and in parallel, and a dedicated instruction for performing status check and update processes is set. Is done.

FIG. 3 is a diagram showing an example of a dedicated instruction for checking the status. As described above, the control commands of the IC test system are macro-formatted and described and described in units of rows, and the lower-level processing device stores and holds the macro-formatted control commands in row units as dedicated commands.

In this dedicated instruction, one word is composed of 16 bits and is a variable length instruction word. The code OP is an instruction code. B
Is a flag for determining whether or not to synchronize with another lower processing device, f is an error flag, and N is the designation of the operand length. The next two words represent a check condition.
The operand portion having a length of N specifies a channel to be checked. × is not used.

As described above, when a dedicated instruction in which various designations are aggregated into one instruction and used as a macro is used, as shown in the flow chart of FIG. The processing units 23A, 23B, 23C to 23N of the present invention use a single unit to process the part indicated by reference symbol A in FIG. The state of each hardware module 25A1, 25A2 to 25An can be checked only by taking several tens of microseconds using an instruction. On the other hand, the upper-level processing device 21 only performs exception processing for the portion indicated by the reference numeral B in the figure, and therefore, it takes time to check and update the status, and the processing speed of the entire IC test system may decrease. Absent.

In addition, the following example is a DC test program for applying a voltage to a terminal pin of an IC to be measured.

VSIM DC1-3 = 5V, M10MA; Set DC test unit channels 1 to 3 to voltage generation / current measurement mode. Generated voltage is 5V. Current measurement range is set to 10mA.

LIMIT DC1-3 = 5MA, 3MA; Set the range of the pass area (area that can be judged as good) as a result of the measurement on channels 1 to 3 of the DC test unit to 3 mA to 5 mA.

MEAS DC1-3: Perform measurement on channels 1 to 3 of the DC test unit and determine the result.

In this example, the DC test is executed by the above three lines of the program.

Looking at VSIM DC1-3 = 5V, M10MA on the first line, to execute this: 1. Check the status.

The current DC1-3 mode, that is, the voltage generation / current measurement mode or the current generation / voltage measurement mode is checked. Check the current generated voltage and measurement range.

2. Access the module.

The necessary part is written to the module register according to the result of the status check.

According to the present invention, the above-described module access, determination of the measurement result, and other hardware module operation control processing are performed by a decentralized lower processing device.
Processing can be sped up. That is, the present invention can increase the operating speed of the software of the IC test system by decentralizing the lower processing units and entrusting only the operation control processing of the hardware modules to them. In the case of the conventional example in which a general-purpose microcomputer is simply used for decentralization, when a large number of test modules are accessed at a high speed for testing, the status is checked using a combination of general-purpose machine languages, or the modules are accessed. According to this, the number of steps does not significantly differ from the number of steps executed by the conventional single processing apparatus, and reaches a huge number.

According to the present invention, it is possible to increase the operating speed of the software of the IC test system to about several tens of times the conventional one.

[Effects of the Invention] As described above, according to the present invention, a higher-level processing device exclusively controls whether to execute a program line,
The actual execution of the program line is distributed to a plurality of lower processing units, and a hierarchical structure is adopted in which the execution contents are limited to only test program instructions in line units for controlling the operation of the hardware module. To run the test program,
Needless to say, in addition to the line-by-line test program command for controlling the operation of the hardware module, a command for controlling the peripheral devices of the computer such as a disc file transfer command, a data printing command, an arithmetic command relating to addition, subtraction, multiplication and division, and various other commands Although a large number of miscellaneous instructions are required, the execution of these various miscellaneous large numbers of instructions reduces the burden without leaving it to a lower-level processing unit, and these processings are performed at a high speed corresponding to this. The burden is placed on the upper processing unit. As described above, the processing speed is improved by the distributed architecture, and since the optimal instruction word system is used for each hierarchy, very fast control becomes possible, and the DC test on the device under test can be performed quickly.

Furthermore, according to the configuration of the present invention, each of the lower processing units 23A,
By distributing and processing the status tables 27A, 27B, 27C to 27N in 23B, 23C to 23N, the time required to check the state of the hardware modules 25A, 25B, 25C to 25N is shortened, and in the present invention, Furthermore, dedicated instructions for inspecting and updating the status tables 27A, 27B, 27C to 27N are provided, and the dedicated instructions are provided in the tables 27A, 27B, 27C.
~ 27N The most suitable instruction configuration for updating contents and checking contents is adopted. Therefore, much higher speed processing can be achieved compared to accessing the status table using program instructions used for normal processing, which is very effective for speeding up the test operation of the IC test system.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an IC test system of the present invention, FIG. 2 is a diagram for explaining a main part of the present invention, and FIG.
FIG. 4 is a diagram showing an example of a dedicated instruction for checking and updating the status used by each lower processing device. FIG.
FIG. 5 is a flowchart showing an example of the configuration of an IC test system, and FIG. 5 is a flowchart showing an example of checking and updating the status of a hardware module. 11: Central processing unit, 12: Control line, 13: Hardware module, 16: Status table, 21: Host processing unit, 2
2: control bus, 23: lower processing unit, 24: control line, 25: hardware module, 26: microprocessor, 27: status table.

Claims (1)

(57) [Claims] 1. A high-level processing device that controls execution of a test program, and executes a row-by-line test program instruction that is controlled by the high-level processing device and controls the operation of a hardware module, and an instruction that updates a test status. A plurality of lower-level processing devices, and a plurality of hardware modules that are controlled by the lower-level processing devices and generate a test signal for the device under test and measure an output signal of the device under test in accordance with the execution of the instruction. An IC test system comprising: a lower-level processing device, for each hardware module controlled by the lower-level processing device, a storage device for storing the status of the hardware module, and an update of the status of the corresponding hardware module. Instructions to check instructions and status are provided
IC test system.