JP2583057B2 - IC test system - Google Patents

Description

The present invention relates to an IC test system having a distributed architecture having a hierarchical structure.

[Prior Art] FIG. 3 is a diagram showing a configuration example of a conventional IC test system. In the IC test system, a program in which a test sequence for testing a device under test is described is stored in a storage device (not shown), and the central processing unit 11 reads out the test program from the storage device and sequentially executes the test program. The central processing unit 11 controls all test operations for testing a semiconductor memory device, for example.

The hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 by control lines 12, and the control signals output as the central processing unit 12 decodes and executes the test program are those hardware signals. Module 13A, 13
B, 13C to 13N.

The control signal is, for example, a control signal for supplying a DC signal of 5.25 V to a predetermined input terminal of the device under test, and when the control signal is supplied, for example, the hardware module 13A operates at a 5.25 V Is supplied to a designated input terminal of the device under test.

The control signal output from the central processing unit 11 is, for example, a control signal for instructing to measure a signal, and is, for example, a hardware module 13B for measuring a DC voltage.
When this control signal is supplied, it is connected to the designated output terminal of the device under test and measures its signal voltage.

The hardware modules 13A, 13B, 13C to 13N may incorporate the microprocessor 14. Even if a large number of logic elements are required when a test circuit is assembled using only general-purpose logic elements, the circuit board can be made compact by assembling many parts of the logic circuit with the microprocessor 14. In this case, the microprocessor 14 is merely a substitute for a logic element, and performs only a predetermined sequence control, and is not generally used in a manner that requires a special judgment control function.

In such an IC test system, the number of hardware modules 13A, 13B, 13C to 13N is usually several tens of circuits or more, and the number of devices under test having a relatively small number of input / output terminals is small. Can be tested simultaneously.

"Problems to be Solved by the Invention" The central processing unit decodes and executes a program, that is, outputs a control signal for performing a test of the device under test to a hardware module and the like, and a signal output by the device under test. It is necessary to perform all kinds of arithmetic and control required for the operation of the IC test system, such as measurement of the measurement and judgment of the quality of the measurement result.

For example, when a voltage signal described in a test program is supplied to a device under test, the central processing unit supplies the digital data value to a hardware module or measures an output signal of the device under test. In some cases, the obtained measured value is corrected and converted as necessary, and may be compared with a predetermined judgment table to judge the quality or rank.

As for the test results executed in this way, the test results or the measurement data are stored for each hardware module, and the stored test results are collected and comprehensively judged to determine whether or not the test result is good for the device under test. It is judged as defective. Furthermore, it takes a lot of time to judge the measured values of each test item and to synthesize them, and it is not possible to perform a quick test. In particular, it is impossible to perform a DC test such as a current signal input-voltage signal output characteristic and a voltage signal input-current signal output characteristic quickly and accurately on a device under test having a large number of input / output terminals. near.

Further, in the IC test system, if all of the system control is left to one central processing unit, the test speed becomes slow. Therefore, a distributed processing system configured using a plurality of processing units can be considered. In such a distributed processing system, a single main processing unit sequentially collects the test results of various test items performed by each processing unit, and examines the collected results. It is the same that it is necessary to determine whether the element is good or bad. In addition, when testing a plurality of devices under test at the same time, more complicated processing must be performed, and it takes time to collect, sort, and synthesize the test results. Cannot be obtained, and the test speed cannot be improved.

"Means for Solving the Problems" The IC test system of the present invention includes an instruction for setting a control signal to an input terminal of a device under test and an instruction for measuring an output signal from an output terminal of the device under test. A higher-level processing unit that reads a test program recorded in units of lines and sends the read instruction to a plurality of lower-level processing units, and is required to execute the instructions sent from the higher-level processing unit. A plurality of lower processing units that perform various controls and processes on a plurality of hardware modules by reading a program corresponding to the instruction; and a device under test according to the controls and processes from the lower processing units. A plurality of lower-level processing devices and a higher-level processing device. A plurality of signal lines are connected between the plurality of signal processing units, and the plurality of lower-level processing devices each determine whether the plurality of devices under test are good or bad, and transmit a result of the determination for each device under test to the device under test. Means for outputting to each of the signal lines corresponding to the test element.

According to the configuration of the present invention, the central processing unit controls the execution of the test program on a line-by-line basis, and the actual decoding and execution of the program line are performed in a distributed manner by a plurality of dedicated processing units. . The test results for a plurality of devices under test simultaneously tested are output to only one signal line for each device under test.

Embodiment FIG. 1 is a block diagram showing a configuration example of an IC test system according to the present invention. In this example, the IC test system is connected to a higher-level processing device 21 that controls the execution of a test program stored in a storage device (not shown) via a control bus 22. The plurality of lower processing units 23A, 23B, 23C to 23N that actually execute the program lines under the control of the higher processing unit 21 and the lower processing units 23A, 23B, 23C to 23N are controlled. It is configured hierarchically with hardware modules 25A, 25B, 25C to 25N controlled through the line 24.

That is, in the test program for testing the device under test, the test procedure is described in units of rows, and the host processor 21 sequentially reads the test program from the storage unit in units of rows, and determines whether or not to execute the read program line. Control.

The upper processing device 21 includes a plurality of lower processing devices 23A,
23B, 23C to 23N are connected, and the host processor 21 determines whether to execute the read program line while observing the test state of the device under test, and the actual execution of the program line determined to be executed is lower. A plurality of processing devices 23A provided in,
23B, 23C to 23N.

Each of the lower processing units 23A, 23B, 23C to 23N is a dedicated processing unit suitable for controlling a test signal for the device under test, and a hardware module connected thereto.
Machine language suitable for controlling 25A, 25B, 25C to 25N is defined as a programming language. When the processing device 23 is entrusted with the execution of the program line by the higher-level processing device 21, the processing device 23 decodes the program line and starts executing the program line. That is, the processing devices 23A, 23B, 23C to 23N hold a control program in which a procedure for inputting / outputting a test signal to / from the device under test is stored in a storage device (not shown). The control program is read out based on the result of decoding the program line, and the procedure for controlling the input / output of the signal described in the program line is executed.

The lower processing units 23A, 23B, 23C to 23N are respectively connected to hardware modules 25A, 25B, 25C to 25N.
It has a command language system that is convenient for accessing and changing the test status (connection of terminals and the status of the measuring instrument) and the like, and is macro-instructed.
However, the hardware modules 25A, 25B,
It is configured so that a processing speed several tens of times higher than performing the same processing directly on 25C to 25N can be obtained. IC in this way
The test system can perform quick control when performing a DC test on a device under test having many input / output terminals.

Further, the processing device 23 not only executes the program line requested to be executed by the host processing device 21 as it is, but also decodes the program line, and in accordance with the decoded result, information is previously stored in the device under test. Given functional conditions,
For example, check the minimum clock width, input condition, timing relationship or prohibition condition, etc., and make a judgment so as not to give an incorrect input signal or to fall into a signal state that may severely damage the device under test. The test signal is output to the device under test or the output signal is measured.

The hardware modules 25A, 25B, 25C to 25N are supplied with control signals associated with the execution of the program lines of the lower processing units 23A, 23B, 23C to 23N, and receive test signals for the designated input terminals of the device under test. For example, it can output a DC signal of 5.25 V or measure a signal from a designated output terminal of the device under test.

The hardware modules 25A, 25B, 25C to 25N may include a microprocessor 26. The microprocessor 26 performs a predetermined sequence at a high speed, which does not require a complicated judgment function, by replacing a large number of logic elements. As the microprocessor 26, a general-purpose processor is used, the operation of which is programmed in advance, and the input / output of signals to / from the device under test can be controlled by an instruction from the processing unit 23.

As described above, the lower processing units 23A, 23B, 23C to 23N execute all of the actual processing of the test on the device under test under the control of the upper processing unit 21, and the upper processing unit 21 The entire IC test system performs only organic operations, such as execution control of program lines of the processing devices 23A, 23B, and 23C to 23N and collection of test result pass / fail judgment results.

Further, in the present invention, the lower processing units 23A, 23B, 23C to 2C
The 3N determines the quality of the test data obtained for the device under test, and the result of the determination is supplied to the higher-level processing device via only one signal line 27A, 27B to 27N for each device under test.

FIG. 2 is a diagram showing a configuration example of a main part of an embodiment of the present invention. In this embodiment, four signal lines 27A, 27B to 27D are shown, which is a case in which a maximum of four devices under test 30A, 30B to 30D can be tested at the same time. The lower processing devices 23A, 23B, 23C to 23N and the upper processing device 21 are connected to each other through wired OR circuits 31A, 31B, 31C to 31N and 31P using signal lines 27A, 27B to 27D, respectively. Each of the lower processing units 23A, 23B, 23C to 23N indicates a status 32A, 32B, 32C to 32N indicating the internal state of the corresponding one of the signal lines 27A, 27B.
It is configured so that it can be put on ~ 27D.

The IC test system performs a number of tests on each of the test elements 30A, 30B to 30D, and usually determines that the device under test 30A, 30B to 30D is a good product only when all of those test items pass. I do. These signal lines 27A, 27B to 27D are
It is used to collect final judgment results for 30A and 30B to 30D, respectively.

For example, the output signal of the first device under test 30A is measured by the hardware module 25a, and the measurement data is read into the lower processing devices 23A, 23B, and 23C that control the hardware module 25a. Lower processing unit 23
A, 23B, and 23C correct the measured data as necessary, and compare the finally obtained data value with a reference value to determine the quality of each data value. Each determination result is output to the signal line 27A as a determination status 32a. With respect to the second device under test 30B, a test is similarly performed using the other hardware module 25b, and the measurement data is judged by the lower processing units 23B, 23C,. The status 32b is output to the signal line 27B. The tests on the third and fourth devices under test 30C and 30D are also performed using the other hardware modules 25c and 25d, and the respective determination statuses 32c and 32d are output to the signal lines 27C and 27D, respectively.

According to the configuration of the present invention, for each test item, the status is operated to “0” when it is determined to be good, and the status is operated to “1” when it is determined to be bad. Their "0" or "1" status is a wired or circuit
Since the signals are output to the signal lines 27A, 27B to 27D via 31A, 31B, 31C to 31N, for example, if at least one status 32a connected to the first signal line 27A is operated to "1" , First
A signal "1" is placed on the signal line 27A, and a signal "1" is supplied to the host processor 21. That is, the first device under test 30A is determined to be defective. On the other hand, if all the statuses 32a connected to the signal line 27A are set to "0", the signal "0" is put on the signal line 27A only in this case. When the signal of “0” is read by the host processor 21, the device under test 30A is determined to be non-defective. Therefore, the signals on the signal lines 27A, 27B to 27D up to the higher-level processing device 21 are read only once, and the devices under test 30A, 30
It is possible to know the final result of whether or not all the test items are good for each of B to 30D, so that the next processing can be promptly and appropriately performed.

In the description of FIG. 2, the hardware modules 25a, 25a
Although b to 25d (FIG. 2) have been described as being used specifically for each of the devices under test 30A, 30B to 30D, the same hardware module 25 is used for testing a plurality of devices under test 30A, 30B to 30D. It may be allocated in a time-sharing manner. For example, 1
It is also possible to control so that one hardware module 25A (FIG. 1) is used for two devices under test 30A and 30B. In this case, the two measurement data by the hardware module 25A are separated and processed inside the lower processing unit 23A that controls the hardware module 25A, and the two pieces of measurement data are output as different statuses via signal lines.
It is controlled so that it can be put on 27A and 27B.

Further, the connection from each of the lower processing devices 23A, 23B, 23C to 23N to the higher processing device 21 is not limited to the signal line 27 and the wired OR circuit 31, but using equivalent means for realizing the present invention. You may comprise.

[Effects of the Invention] As described above, according to the present invention, a higher-level processing device is configured to exclusively control execution of a program line, and actual execution of a program line is performed by a plurality of lower-level programs. Control in a hierarchical structure that is distributed to processing devices is adopted. In this way, the processing speed is improved by the distributed architecture, and since the optimal instruction word system is used for each layer, the processing up to output of the control signal becomes very fast, and the test for the device under test can be performed. Can be done at high speed.

Further, according to the configuration of the present invention, even when a plurality of devices under test are simultaneously tested for a large number of items, the test results of the multiple items are collectively output to different signal lines for each device under test. . Therefore, if the host processor reads the status only once through one signal line for each device under test, it can immediately know the quality of the status, and this has a great effect on improving the test speed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing a main part of the present invention, and FIG. 3 is a diagram showing a configuration example of a conventional IC test system. 11: Central processing unit, 12: Control line, 13: Hardware module, 14: Microprocessor, 21: Host processing unit, 2
2: Control bus, 23: Lower processing unit, 24: Control line, 25: Hardware module, 26: Microprocessor, 27: Signal line, 30: Device under test, 31: Wired OR circuit, 32: Status.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References Yukizo Kinoshita et al., "Testing and Reliability", 1st edition, 1st edition, published on April 20, 1982 by Ohmsha, p. 114-115

Claims (1)

(57) [Claims] 1. A test program in which an execution command such as a command for setting a control signal to an input terminal of a device under test and a command for measuring an output signal from an output terminal of the device under test is recorded in a line unit. A high-level processing device that sends the read instruction to a plurality of low-level processing devices; and a control or process required to execute the instruction sent from the high-level processing device. A plurality of lower-level processing units that read and execute the plurality of hardware modules; a test signal is connected to the device under test according to control or processing from the lower-level processing device; A plurality of hardware modules for measuring signals; a plurality of signal lines connected between the plurality of lower-level processing devices and the higher-level processing device; A processor configured to determine whether each of the plurality of devices under test is good or defective; and a unit configured to output a determination result of each device under test to one of the signal lines corresponding to the device under test. IC test system with