JP2587941B2 - IC test system - Google Patents

Description

The present invention relates to an IC test system having a distributed architecture having a hierarchical structure.

[Prior Art] FIG. 3 is a diagram showing a configuration example of a conventional IC test system. In the IC test system, a program in which a test sequence for testing a device under test is described is stored in a storage device (not shown), and the central processing unit 11 reads out the test program from the storage device and sequentially executes the test program. The central processing unit 11 controls all test operations for testing a semiconductor memory device, for example.

The hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 by control lines 12, and control signals output as the central processing unit 11 decodes and executes the test program are those hardware signals. Module 13A, 13
B, 13C to 13N.

The control signal is, for example, a control signal for supplying a DC signal of 5.25 V to a predetermined input terminal of the device under test, and when the control signal is supplied, for example, the hardware module 13A operates at a 5.25 V Is supplied to a designated input terminal of the device under test.

The control signal output from the central processing unit 11 is, for example, a control signal for instructing measurement of a signal, and the hardware module 13B for measuring a DC voltage, when supplied with this control signal, It is connected to the designated output terminal of the device and measures its signal voltage.

The hardware modules 13A, 13B, 13C to 13N may incorporate the microprocessor 14. Even if a large number of logic elements are required when a test circuit is assembled using only general-purpose logic elements, the circuit board can be made compact by assembling many parts of the logic circuit with the microprocessor 14. In this case, the microprocessor 14 is merely a substitute for a logic element, performs only a predetermined sequence control, and is not generally used in a manner that requires a complicated judgment function.

"Problems to be Solved by the Invention" The central processing unit decodes and executes a program, that is, outputs a control signal for performing a test of the device under test to a hardware module and the like, and a signal output by the device under test. It is necessary to perform all kinds of arithmetic and control required for the operation of the IC test system, such as measurement of the measurement and judgment of the quality of the measurement result.

For example, when a voltage signal described in a test program is supplied to a device under test, the central processing unit supplies the digital data value to a hardware module or measures an output signal of the device under test. In some cases, the obtained measured value is corrected and calculated as necessary, and may be compared with a predetermined judgment table to judge the quality or rank.

In addition, to accurately supply many test signals to dozens to hundreds of input / output terminals to the device under test and to measure their response signals in a precise time relationship, the timing relationship must be determined. And a control signal must be given to each hardware module, and it is also difficult to control with one central processing unit.

Further, in such an IC test system, if all system control is left to one central processing unit, the test speed is reduced. Therefore, a distributed processing system including a plurality of processing units can be considered. However, even in such a distributed processing system, a control signal accurately synchronized between the processing devices is supplied to each hardware module to output a test signal that is perfectly timed and a sequence signal whose time interval is accurate. It is very difficult to make or measure signals. For example, one main processing device instructs each processing device to start synchronized processing, or reads a signal indicating the state of the processing from each processing device separately, and sequentially reads the signals. It is necessary to perform the following processing comprehensively. As described above, it is difficult to accurately perform synchronized processing between the processing devices. Even if the processing is intentionally performed, strict synchronization processing is generally very complicated and requires a lot of processing time. At any time and in any situation,
It is doubtful whether accurate synchronization processing is possible.

"Means for Solving the Problems" The IC test system of the present invention includes an instruction for setting a control signal to an input terminal of a device under test and an instruction for measuring an output signal from an output terminal of the device under test. A higher-level processing unit that reads a test program recorded in units of lines and sends the read instruction to a plurality of lower-level processing units, and is required to execute the instructions sent from the higher-level processing unit. A plurality of lower processing units that perform various controls and processes on a plurality of hardware modules by reading a program corresponding to the instruction; and a device under test according to the controls and processes from the lower processing units. A plurality of hardware modules for connecting a test signal to the device or measuring an output signal of the device under test; The lower processor is connected to the same bidirectional bus as the status of the lower processor, and the upper processor determines in advance the status state of the upper processor when the lower processor executes the instruction. Means for monitoring the state of the bidirectional bus and determining that the state of the bidirectional bus is the other logical value and that all of the plurality of lower-level processing units have completed processing. , Each of the lower-level processing units has its status,
Means for capturing the state of the bidirectional bus with a common system clock, means for starting the processing of the lower processing device with the captured state using the one logical value, and Means for setting the status state to the other logical value.

According to the configuration of the present invention, the above-described processing device controls the execution of the test program on a line-by-line basis, and the actual decoding and execution of the program line are distributed and executed by the lower-level dedicated processing device. Will be

Further, according to the configuration of the present invention, the mutual exchange of the status information between the upper processing unit and each of the lower processing units can be performed by one exchange. Further, since the upper and lower processing units operate in synchronization with the same clock signal, a time-accurate test operation can be performed on the device under test.

Embodiment FIG. 1 is a block diagram showing a configuration example of an IC test system according to the present invention. In this example, it is configured to be suitable for a DC test, that is, a test such as a current signal input-voltage signal output characteristic or a voltage signal input-current signal output characteristic. The IC test system includes a host processor 21 for controlling execution of a test program stored in a storage device (not shown), and an actual execution of a program line under the control of the host processor 21. And a plurality of lower processing units 23A, 23B, 23C to 23N, and hardware modules 25A, 25B, 25C to 25N controlled by these lower processing units 23A, 23B, 23C to 23N. You.

That is, in the test program for testing the device under test, the test procedure is described in units of rows, and the higher-level processing device 21 sequentially reads out the test programs from the storage device in units of rows, and determines whether or not to execute the read program lines. Control.

The upper processing device 21 includes a plurality of lower processing devices 23A,
23B, 23C to 23N are connected, and the upper processing unit 21 determines whether or not to execute the read program line while observing the progress of the test on the device under test, and determines the actual execution of the program line determined to be executed. Execution is entrusted to any of the processing devices 23A, 23B, 23C to 23N connected to the lower level.

Each of the lower processing units 23A, 23B, 23C to 23N sends a test signal for the device under test to a hardware module 25A, 25B, 25C.
It is a dedicated processing device suitable for control using ~ 25N, and accesses the hardware modules 25A, 25B, 25C ~ 25N and changes the test status (terminal connection and measuring device status) etc. Has a convenient command language system. Also, since the instruction is a macro instruction, the host processor 21 uses its own instruction word system to execute the hardware modules 25A, 25B, 25C to 25N.
The processing speed is several tens of times faster than when the same processing is performed directly.

When each of the processing devices 23A, 23, 23C to 23N is entrusted with execution of a program line from the host processing device 21, it decodes the program line and starts executing the program line. That is, the processing devices 23A, 23B, 23C to 23N hold a control program in which a procedure for inputting / outputting a test signal to / from the device under test is stored in a storage device (not shown). The control program is read out based on the result of decoding the program line, and the procedure for controlling the input / output of the signal described in the program line is executed.

Further, the processing devices 23A, 23B, 23C to 23N are higher-order processing devices.
Not only the program line for which execution has been commissioned from 21 is executed as it is, but also the program line is deciphered, and the deciphered result is given to the function condition in which information is given in advance to the device under test, for example, Check the clock width, input conditions, timing relations, prohibition conditions, etc., and judge whether to give an incorrect input signal or to fall into a signal state that may cause damage to the device under test. The test signal is output to the test element or the output signal is measured.

The hardware modules 25A, 25B, 25C to 25N are supplied with control signals associated with the execution of the program lines of the lower processing units 23A, 23B, 23C to 23N, and supply test signals to designated input terminals of the device under test. It can output or measure a signal from a designated output terminal of the device under test.

The hardware modules 25A, 25B, 25C to 25N may include a microprocessor 26. The microprocessor 26 performs a predetermined sequence at a high speed without a so-called judgment function in which a large number of logic elements are replaced. As the microprocessor 26, a general-purpose processor is used, the operation of which is programmed in advance, and the input / output of signals to / from the device under test can be controlled by an instruction from the processing unit 23.

Furthermore, in the IC test system of the present invention adopting a hierarchical structure, the upper processing unit 21 and the lower processing units 23A, 23B, 23C to 2C
It is configured to improve the test speed of the test system by minimizing the amount of information exchange between the 3Ns, and complete control processing among the lower processing units 23A, 23B, 23C to 23N. It is configured to obtain synchronization. That is, a bidirectional bus 27 is provided, and the upper processing unit 21 and the lower processing units 23A, 23B, 23C to 2C are connected to the bidirectional bus 27.
3N is connected. Further, the system clock ck of the upper processing device 21 is supplied to each of the lower processing devices 23A, 23B, 23C to 23N.

FIG. 2 is a diagram showing a configuration example of a main part of the present invention. In this example, one bidirectional bus 27 is provided, and the processing devices 23A, 23B, 23C to 23N and the higher-level processing device 21 are connected to the bidirectional bus 27 by wired OR circuits 31A, 31B, 31C, respectively. Three
Statuses 32A, 32B, 32C to 32N and 32P, which are connected via 1N and 31P and indicate the respective internal states, are bidirectional bus 2
It is constructed so that it can be put on 7. In addition, the system clock ck of the host processor 21 is connected to the clock signal line 33.
Is supplied to each of the lower processing units 23A, 23B, 23C to 23N.

The system clock ck receives a signal delay of, for example, several nanoseconds per meter while propagating through the clock signal line 33, so that when reaching the respective processing devices 23A, 23B, 23C to 23N, the system clock ck The timing of the clock is later than when it is output. However, the length of the clock signal line 33 is set so that the delay time received by the system clock ck from the clock signal line 33 is sufficiently shorter than one cycle thereof. For example, the system clock ck used here is
It is a 50:50 rectangular wave signal of 10 MHz, and if the total extension of the clock signal line 33 is 1 m, the timing is delayed by several n seconds at the maximum.

The upper-level processing units 21 are lower-level processing units 23A, 23B, 23C to 2
When the processing is simultaneously started by 3N, the signal transmitted on the bidirectional bus 27 from the host processor 21 is treated as positive logic. That is, the higher-level processing device 21 sets the content of its status 32P to, for example, “1”. The status 32P propagates through the bidirectional bus 27 as a start signal, and the respective statuses 32A, 32B, of the lower processing devices 23A, 23B, 23C to 23N via wired OR circuits 31A, 31B, 31C to 31N.
It is reported to 32C ~ 32N. On the other hand, the system clock ck of the higher-level processing device 21 is supplied to each processing device via the clock signal line 33.
23A, 23B, 23C to 23N, and each of the processing devices 23A, 23
B, 23C to 23N can take in the start signal supplied to the wired OR circuits 31A, 31B, 31C to 31N at the system clock ck. In addition, the delay time is set to be sufficiently shorter than the time corresponding to one cycle of the system clock ck, so that it can be captured at the same timing of the same system clock ck. Therefore, each processing device 23A, 23B, 23
C to 23N can operate completely synchronously by the system lock ck.

In other words, the upper processing device 21 only sets its status 32P to "1" once as a synchronization processing start signal, and executes the synchronization processing assigned to each of the lower processing devices 23A, 23B, 23C to 23N. A test signal can be supplied to the device under test or measured so that it is almost perfectly synchronized.

Further, according to the present invention, each of the processing devices 23A, 23B, 23C to 23N completes the status 32A, 32B, 32
Change C ~ 32N to indicate that it has finished. In this case, the end signal is treated as negative logic. That is, the lower processing units 23A, 23B, 23C to 23N set their statuses 32A, 32B, 32C to 32N to "0" when the synchronization processing ends. These end signals are output to the bidirectional bus 27 via the wired OR circuits 31A, 31B, 31C to 31N. Therefore, when all the statuses 32A, 32B, 32C to 32N are operated to "0", the signal on the bidirectional bus 27 changes to "0" for the first time. The higher-level processing device 21 monitors the level of the signal loaded on the single bidirectional bus 27 so that each processing device 23
It is possible to know whether or not the synchronization test processing by A, 23B, 23C to 23N has been completed. Therefore, each processing device 23A, 23B, 23C-2
There is no need to separately read out the end signal of the 3N synchronization processing, and other processing can be performed by that amount, thereby enabling quick system control.

[Effects of the Invention] As described above, according to the present invention, an upper processing device exclusively controls execution of a program line, and actual execution of a program line is distributed to a plurality of lower processing devices. In a hierarchical structure. In addition to improving the processing speed by this distributed architecture, since the optimal instruction system is used for each layer, the processing up to the output of the control signal is very fast, and the test for the device under test is performed at high speed. It can be carried out.

Further, according to the configuration of the present invention, when a test on the device under test is divided by each of the lower processing units, the control program is processed almost completely in synchronization between the lower processing units. This makes it possible to supply and measure a test signal to the device under test synchronously or in an accurate time sequence.

In addition, since the system control processing by the host processing apparatus regarding these synchronous processings is performed quickly, the test speed is greatly improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of an IC test system according to the present invention, FIG. 2 is a diagram showing a configuration example of a main part of the present invention,
FIG. 3 is a diagram showing a configuration example of a conventional IC test system. 11: Central processing unit, 12: Control line, 13: Hardware module, 14: Microprocessor, 21: Host processing unit, 2
2: Control bus, 23: Lower processing unit, 24: Control line, 25: Hardware module, 26: Microprocessor, 27: Bidirectional bus, 31: Wired OR circuit, 32: Status, 3
3: Clock signal line.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References Yukizo Kinoshita et al., "Test and Reliability", 1st edition, 1st edition, published on April 20, 1982 by Ohmsha, p. 114-P. 115

Claims (1)

(57) [Claims] 1. A test program in which an execution command such as a command for setting a control signal to an input terminal of a device under test and a command for measuring an output signal from an output terminal of the device under test is recorded in a line unit. A high-level processing device that sends the read instruction to a plurality of low-level processing devices; and a control or process required to execute the instruction sent from the high-level processing device. A plurality of lower-level processing units that read and execute the plurality of hardware modules; a test signal is connected to the device under test according to control or processing from the lower-level processing device; A plurality of hardware modules for measuring signals, wherein the status of the upper processing unit and the status of the plurality of lower processing units are the same bidirectional bus. Means for setting the status of the higher-level processing device to one predetermined logical value when the higher-level processing device causes the lower-level processing device to execute the instruction; Means for monitoring the status of the bus and determining that the status is the other logical value and that the plurality of lower-level processing devices have all completed the processing. Means for capturing the state of the bidirectional bus with a common system clock, means for starting the processing of the lower processing device with the captured state using the one logical value, and status of the processing when the processing is completed. Means for setting the state of the above to the other logical value, and an IC test system comprising: