JP2583055B2 - IC test system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an IC test system for testing a device under test having a number of input / output terminals.

FIG. 2 is a diagram showing a configuration example of a conventional IC test system. In the IC test system, a program describing a test sequence for testing a device under test is stored in a storage device (not shown), and the central processing unit 11 reads out the test program from the storage device and sequentially executes the test program. The central processing unit 11 controls all test operations for testing, for example, a semiconductor memory device.

The hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 via control lines 12, and the control signals output as the central processing unit 11 decodes and executes the test program are Hardware module 13A,
13B, 13C to 13N are supplied through the control line 12. Although not shown in the figure, the device under test has input / output terminals ranging from several to several tens or more, and hardware modules 13A, 13B, 13
C-13N supply signals to their input / output terminals and are controlled to measure output signals.

The control signal is, for example, a control signal for supplying a DC signal of 5.25 V to a predetermined input terminal of the device under test. A V DC signal is supplied to a designated input terminal of the device under test.

The control signal output from the central processing unit 11 is, for example, a control signal for instructing to measure a signal, and is, for example, a hardware module 13B for measuring a DC voltage.
When this control signal is supplied, it is connected to the designated output terminal of the device under test and measures its signal voltage.

The hardware modules 13A, 13B, 13C to 13N may incorporate the microprocessor 14. Even if a large number of logic elements are required when a test circuit is assembled using only general-purpose logic elements, the circuit board can be made compact by assembling many parts of the logic circuit with the microprocessor 14. In this case, the microprocessor 14 is merely a substitute for a large number of logic elements, only processes a predetermined sequence, and is not used in a manner that requires a complicated judgment function.

"Problems to be Solved by the Invention" The central processing unit decodes and executes the program, that is, outputs a control signal for performing a test of the device under test to a hardware module or the like, and also outputs the device under test. It is necessary to perform all kinds of arithmetic and control required for the operation of the IC test system, such as signal measurement and determination of the quality of the measurement result.

In particular, current signal input-voltage signal output characteristics (IV characteristics)
Alternatively, a DC test for testing a voltage signal input-current signal output characteristic (VI characteristic) is a high-speed and accurate timing control or signal measurement as the number of input / output terminals of the device under test is large. Is required. Also, for example, even if a 5.25 V signal described in the test program is supplied to the device under test, the central processing unit converts the voltage value of 5.25 V into a digital data value and supplies the digital data value to the hardware module, It is necessary to calculate and provide the timing until the hardware module actually outputs the signal voltage to the device under test. Further, when the output characteristics of the hardware module deviate from the linearity, it is necessary to output digital data specifying a voltage value by performing a correction process with reference to a correction table stored in advance. is there.

In addition, even when measuring the output signal from the output terminal of the device under test, the data for changing the measurement range of the hardware module was sent in accordance with the signal, the range was changed, and the signal was measured. The measured values are corrected according to a correction table as needed. The determined measured value may be compared with a predetermined judgment table to judge pass / fail or rank of pass / fail.

For such tens of input / output terminals,
Since it is required that the central processing unit processes everything, the time required for the arithmetic processing required by the central processing unit increases. Therefore, the control of the test of the signal output and the signal measurement to the device under test via the hardware module becomes slow, and it is difficult to increase the test speed of the IC test system.

"Means for Solving the Problems" The IC test system of the present invention includes an instruction for setting a control signal to an input terminal of a device under test and an instruction for measuring an output signal from an output terminal of the device to be measured. A higher-level processing unit that reads a test program recorded in units of lines and sends the read instruction to a plurality of lower-level processing units, and is required to execute the instructions sent from the higher-level processing unit. A plurality of lower processing units that perform various controls and processes on a plurality of hardware modules by reading a program corresponding to the instruction; and a device under test according to the controls and processes from the lower processing units. And a plurality of hardware modules for connecting a test signal to the device and measuring an output signal of the device under test.

According to the configuration of the present invention, the upper-level processing device merely determines that the test program is to be executed in units of lines, and the execution is requested to a plurality of lower-level processing devices and described in the program line. It does not actually decode and execute the control contents being executed. Instead, the decoding and execution of the program line are performed in a distributed manner by a plurality of dedicated processing units connected below.

In addition, the program can be described simply in a high-level language line by line without being bound by the specific detailed conditions of the device under test, so that it is easy to create a test program, Debugging when changing is easy.

Embodiment FIG. 1 is a block diagram showing an embodiment of an IC test system according to the present invention. The IC test system according to the present invention has a plurality of processing devices arranged in a hierarchical structure. That is, although not shown, a higher-level processing device 21 that controls execution of a test program stored in a storage device, and is connected to the higher-level processing device 21 via a control bus 22 and has a higher-level A plurality of lower processing units 23A, 23B, 23C to 23N that actually execute the program lines under the control of the processing unit 21, and control lines 24A, 24B to these lower processing units 23A, 23B, 23C to 23N. 24C
Hardware module 25A, 2 controlled through ~ 24N
5B, 25C to 25N.

That is, according to the present invention, the procedure for testing the device under test is stored in the storage device as a test program. In the test program, test procedures are described in line units. For example, a command for setting an input condition for an input terminal of a device under test, a command for measuring an output signal output from an output terminal, and the like are simply described in units of program lines. The host processor 21 sequentially reads the test programs from the storage device in units of program lines, and controls whether to execute the read program lines.

That is, a plurality of lower processing units 23A, 23B, 23C to 23N are connected to the upper processing unit 21, and the upper processing unit
21 determines whether or not to execute the read program line while observing the progress of the test on the device under test, and the actual execution of the program line determined to be executed is determined by processing devices 23A, 23B, 23C connected to the lower order. N23N.

Each of the processing devices 23A, 23B, 23C to 23N sends a test signal to be supplied to the device under test to a hardware module 25A, 25B, 25C to 25N.
Is a dedicated processing device suitable for controlling via the, and a dedicated processing device suitable for measuring the signal output from the device under test via the hardware modules 25A, 25B, 25C to 25N, Hardware modules 25A, 25B, 25C to 25N
It has an efficient instruction word system for accessing any one of them and changing the test state (connection of terminals and the state of a measuring instrument), and is converted into a macro instruction. Accordingly, the hardware modules 25A, 25B, 25C to 25N can be controlled with a small number of instruction words, for example, one or two instruction words. For example, the lower processing units 23A, 23B, 23C to 23N can control the hardware modules 25A, 25B, 25C to 25N to take in the measured data and store it in the storage device with one instruction. The high-level processing unit 21 uses hardware modules 25A, 25B, 25
Processing speed several tens of times higher than performing the same control directly for C to 25N can be obtained. Therefore, the test conditions given to the device under test having a large number of input / output terminals are variously changed, and the V-
A DC test for examining I characteristics, IV characteristics, and the like can be performed at high speed using accurate timing signals.

When the processing device 23 is entrusted with the execution of the program line by the host processing device 21, the processing device 23 decodes the program line and enters the actual execution of the program line. That is, the processing device 23 holds a control program in which a procedure for inputting / outputting a test signal to / from the device under test is described in a storage device (not shown). The control program is read out, and the procedure for controlling the input / output of the signal described in the program row is executed.

In these procedures, for example, first, a given program line is decoded, and a specified hardware module 25 is accessed. Subsequently, the test status is changed. It is a process for supplying a DC signal of 5.25 V to the device under test, for example, as described in the input / output process of the conventional example, and a process for measuring the output signal of the device under test. .

In the present invention, the processing device 23 is
Not only the program line for which execution has been commissioned from 21 is executed as it is, but also the program line is deciphered, and the deciphered result is given to the function condition in which information is given in advance to the device under test, for example, Check the clock width, input condition, timing relationship or prohibition condition, etc., and determine the device under test while judging so as not to give an incorrect input signal or to fall into a signal state that may cause damage to the device under test. Is controlled to output a test signal or measure the output signal.

For example, at the time of a certain test state Q1 during the test of the device under test, when a signal is given to a certain input terminal as an instruction described in a program line in order to make the next test state Q2, the device under test becomes Prohibited state Q3 that must not be placed
In some cases. By executing the program line, the processing device 23 checks whether the device under test enters such a prohibited state Q3, determines a control procedure to avoid the prohibited state Q3, and executes the program line. I do.
For example, the processing device 23 determines the control operation such that the state of the device under test changes from the state Q1 to the state Q2 described in the program line via the state Q4, the state Q5,... And executes the program line.

Therefore, when creating a program, it is not necessary to sequentially describe the program line while taking into account the prohibited state Q3 of the device under test, and the processing device 23 makes a judgment based on the information supplied in advance. The control is performed so as not to fall into the prohibited state Q3. Therefore, it is configured such that the device under test does not enter the prohibited input / output state and is destroyed or fall into an indeterminate state, so that the device under test malfunctions and an incorrect test result is output.

Further, the processing device 23 can perform not only the measurement of the applied signal, but also the correction of the measured signal, for example, the linear correction, the logarithmic curve correction, or the change of the measurement range, if necessary. The measurement data obtained by such processing is compared with a reference value or a threshold value, and the quality of the measurement data is determined, and data logging of the data is performed.

Hardware modules that must be controlled
25A, 25B, lower processing unit 23A according to the number of circuits of 25C ~ 25N,
The number of units 23B, 23C to 23N increases and decreases. The upper processing device 21
Since the test described in the program line is not actually executed, ten or more lower processing units 23A, 23B,
23C to 23N can be controlled simultaneously.

In the present invention, the input / output control signals output when the lower processing units 23A, 23B, 23C to 23N actually execute the program lines are supplied to the hardware modules 25A, 25B, 25C to 25N. The hardware modules 25A, 25B, 25C to 25N output a test signal, for example, a DC signal of 5.25V to an input terminal specified separately for the device under test according to the supplied control signal, or the device under test is designated. The signal from the output terminal is measured.

These hardware modules 25A, 25B, 25C to 25N may include a microprocessor 26 as in a conventional IC test apparatus. The microprocessor 26 performs a predetermined sequence at a high speed without a so-called judgment function in which a large number of logic elements are replaced. This microprocessor 26
A general-purpose processor is used, and the operation of GO / NO-GO is programmed in advance, and the input / output of signals to / from the device under test can be controlled by an instruction from the processing device 23.

As described above, according to the present invention, a lower-level processing unit 23A dedicated to hardware module control has an instruction language system suitable for controlling the hardware module 25 below the upper-level processing unit 21 using a general-purpose program language. , 23B, 23
A distributed processing system with a hierarchical structure in which C to 23N are arranged was constructed. That is, the lower processing units 23A, 23B, 23C to 23N perform the actual processing of the test on the device under test (the input / output terminals of the device under test and the hardware modules 25A, 25B, The functions are dispersed by executing all of the steps of connection with 25C to 25N, setting of data, measurement and correction of signals and determination of good or bad, recording of measurement results, and the like.

[Effects of the Invention] As described above, conventionally, when testing a semiconductor device, a test sequence that cannot be divided and executed is processed by a single processing apparatus. A plurality of processing devices are arranged in a hierarchy, and a higher-level processing device exclusively controls execution of a program line, and an actual execution of a program line is performed by a plurality of lower-level processing devices. In other words, the higher-level processing unit controls the organic operation of the entire IC test system, which determines when to execute a program line written in a high-level language and allocates execution to each lower-level processing unit. A dedicated processing device is arranged, and the actual execution of a program line is controlled in a hierarchical structure distributed to a plurality of dedicated processing devices below the program line. As described above, with the improvement of the processing speed by the distributed architecture, a high-level language that is easy to program is used for a higher-level processing device, and a language system suitable for understanding the high-level language and performing overall control is provided. use. Also, the lower processing device is converted into a macro instruction using an instruction word system suitable for high-speed control of the hardware module when instructed by the higher processing device. Therefore, the processing from the decoding of the program line by the processing device to the output of the control signal becomes very fast, and the test on the device under test, especially the DC test, can be performed at high speed.

Further, since the test program for the device under test can be described in units of lines in a high-level language, the test program can be easily changed and debugged.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of an IC test system according to the present invention, and FIG. 2 is a diagram showing a configuration example of a conventional IC test system. 11: Central processing unit, 12: Control line, 13: Hardware module, 14: Microprocessor, 21: Host processing unit, 2
2: control bus, 23: lower processing unit, 24: control line, 25: hardware module, 26: microprocessor.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References Yukizo Kinoshita et al., "Test and Reliability", 1st edition, 1st edition, April 20, 1982, published by Ohmsha. 114-115

Claims (1)

(57) [Claims] 1. A test program in which an execution command such as a command for setting a control signal to an input terminal of a device under test and a command for measuring an output signal from an output terminal of the device under test is recorded in a line unit. A high-level processing device that sends the read instruction to a plurality of low-level processing devices; and a control or process required to execute the instruction sent from the high-level processing device. A plurality of lower-level processing units that read and execute the plurality of hardware modules; a test signal is connected to the device under test according to control or processing from the lower-level processing device; An IC test system comprising: a plurality of hardware modules for measuring a signal;