JPS63298178A - Ic test system - Google Patents

Abstract

PURPOSE:To achieve a higher testing speed, by a method wherein the execution by lines of a test program is controlled with a higher-order processor, actual execution of the program is done with lower-order processors and the results of testing are outputted with signal lines one per element to be tested. CONSTITUTION:A plurality of lower-order processors 23A-23N are connected to a higher-order processor 21. The processor 21 decides whether a program line read is executed or not checking a state of testing an element to be tested and assigns actual execution of the program line decided to be executed to any of the processors 23A-23N provided at a lower order. The processors 23A-23N judge the propriety of a test data obtained for the element being tested and the results of judgement are supplied to the processor 21 separately through signal lines 27A-27N one per element being tested.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to an IC test system having a hierarchical distributed architecture.

"Prior Art" FIG. 3 is a diagram showing an example of the configuration of a conventional IC test system. In an IC test system, a program containing a test sequence for testing a device under test is stored in a storage device (
(not shown), and the central processing unit 11 is configured to read the test program from the storage device and execute it sequentially. For example, the central processing unit is now under control.

Hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 by control lines 12, and the control signals output when the central processing unit 12 decodes and executes the test program are connected to these hardware modules. Module 13A.

13B, 13C to 13N.

The control signal is, for example, a control signal for supplying a 5.25V DC signal to a predetermined input terminal of the device under test, and when this control signal is supplied, for example, the hardware module 13A .25■ DC signal is supplied to the designated input terminal of the device under test.

Further, the control signal outputted by the central processing unit 11 is, for example, a control signal instructing to measure a signal, and when the hardware module 13B for measuring DC voltage is supplied with these four control signals, the It is connected to the designated output terminal of the test element and its signal voltage is measured.

These hardware modules 13A, 13B.

13C to 13N may have a microprocessor 14 incorporated therein. Even if a huge number of logic elements are required if the test circuit is constructed using only general-purpose logic elements, the circuit board can be made compact by constructing many parts of the logic circuit using the microprocessor 14. The microprocessor 14 in this case is simply a replacement for a logic element,
It only performs predetermined sequence control, and is not generally used in a way that requires a special judgment control function.

In such an IC test system, the hardware modules 13A, 13B, 13C to 13N are usually equipped with several dozen circuits or more, and the number of devices under test with a relatively small number of input/output terminals is several. individual devices can be tested simultaneously.

"Problem to be Solved by the Invention" The central processing unit decodes and executes programs, that is, outputs control signals for testing the device under test to hardware modules, and also outputs signals output by the device under test. It is necessary to carry out all kinds of arithmetic and control operations required for the operation of the IC test system, such as measuring and determining whether the measurement results are good or bad.

For example, when supplying the voltage signal described in the test program to the device under test, the central processing unit supplies the digital data value to the hardware module, or when measuring the output signal of the device under test. In some cases, the obtained measured values are corrected and converted as necessary, and compared with a predetermined judgment table to judge the quality or failure, or to rank them.

The test results or measurement data executed in this way are stored for each hardware module, and each time the stored test results are collected and comprehensively judged, the quality of the device under test is determined. It has been judged as defective. Furthermore, a large amount of time is spent in determining and synthesizing the measured values for each test item, making it impossible to conduct tests quickly. In particular, it becomes impossible to perform C tests quickly and accurately on devices under test that have a large number of input and output terminals, such as current signal manual input - voltage signal output characteristics and voltage signal manual input - current signal output characteristics. close.

Furthermore, in an IC test system, if all system control is left to one central processing unit, the testing speed will be slow, so a distributed processing system configured using a plurality of processing units can also be considered.

In such a distributed processing system, one main processing unit sequentially collects the test results for various test items performed by each processing unit and examines the collected results. The need to determine whether the test element is good or bad is the same. Moreover, when testing multiple devices under test at the same time, more complicated processing must be performed, and it takes time to collect, separate, and synthesize the test results, and the test results for the devices under test can be quickly obtained. Therefore, it is not possible to improve the test speed.

[Means for Solving the Problems 1] In this invention, a higher-level central processing unit controls the execution of a test program in which a test sequence is written line by line, and executes the control content written in each line of the program. Actual decoding and execution is left to lower-level processing units controlled by the central processing unit. The lower processing device executes a program line to access the hardware module or update the test status.

Furthermore, in this invention, each lower-level processing device determines whether the measured values for each test item obtained by simultaneously testing multiple devices under test are good or bad, and the determination results are sent to the devices under test that are simultaneously tested. The data are collectively output to a higher-level processing device on different data lines.

"Operation of the Invention" According to the configuration of the present invention, the central processing unit controls the execution of the test program line by line, and the actual decoding and execution of the program lines is performed in a distributed manner by a plurality of dedicated processing units. . Further, the test results for a plurality of devices under test that are tested simultaneously are outputted to only one signal line on the side of each device under test.

Embodiment FIG. 1 is a block diagram showing a configuration example of an IC test system of the present invention. In this example, the IC test system is connected to a higher-level processing device 21 that controls the execution of a test program stored in a storage device (not shown) and to this higher-level processing device 21 via a control bus 22. , a plurality of lower processing devices 23A, 23B, 2 which actually execute the program lines under the control of the upper processing device 21.
3C to 23N and their lower processing devices 23A and 23B
.

It is hierarchically constituted by hardware modules 25A, 25B, and 25C to 25N, which are controlled through control lines 24 to 23C to 23N.

That is, in a test program for testing the device under test, the test procedure is written line by line, and the host processing unit 21 sequentially reads the test program line by line from the storage device, and determines whether or not to execute the read program line. control.

This upper processing device 21 has a plurality of lower processing devices 23.
A, 23B, 23C to 23N are connected, and the host processing unit 21 determines whether or not to execute the read program line while checking the test status of the device under test, and actually executes the program line that it has decided to execute. is entrusted to any one of the plurality of processing devices 23A, 23B, 23C to 23N provided at the lower level.

The lower processing devices 23A, 23B, 23C to 23N are dedicated processing devices suitable for controlling test signals for the device under test, and are connected to hardware modules 25A, 25B, respectively.

The programming language is a machine language suitable for controlling 25C to 25N. When the processing device 23 is entrusted with executing a program line from the higher-level processing device 21, it decodes the program line and starts executing the program line. That is, the processing devices 23A and 23B.

23C to 23N hold a control program in a storage device (not shown in the figure) that describes the procedure for inputting and outputting test signals to and from the device under test, and the control program is controlled based on the result of decoding the given program line. Read the program and execute the procedure for controlling input/output of the signals written in the program line.

These lower processing devices 23A, 23B, 23C to 23N are connected to node/ware modules 2, respectively.
It has a command system that is convenient for accessing 5A, 25B, 25C to 25N and changing the test status (terminal connections and measuring instrument status), etc., and is converted into macro commands, so it can be easily processed by higher-level processing. The bag W21 is configured to obtain a processing speed several tens of times faster than when the hardware modules 25A, 25B, 25C to 25N directly perform the same processing using its instruction word system. In this way, the IC test system can perform rapid control when performing a DC test on a device under test having a large number of input/output terminals.

In addition, the processing device 23 not only executes the program line that has been entrusted to execute from the host processing device 21 as it is, but also decodes the program line and provides information in advance to the device under test based on the decoding result. given functional conditions,
For example, check the minimum clock width, input conditions, timing relationships, prohibition conditions, etc., and make judgments to avoid giving incorrect input signals or falling into signal conditions that could seriously damage the device under test. while outputting a test signal to the device under test or measuring the output signal.

Hardware modules 25A, 25B, 25C-25
N is supplied with a control signal accompanying the execution of the program line of the lower processing units 23A, 23B, 23C to 23N, and outputs a test signal 1, for example, a 5.25V DC signal to a specified input terminal of the device under test. Alternatively, signals from specified output terminals of the device under test can be measured.

These hardware modules 25A, 25B.

25C-25N may include a microprocessor 26. This microprocessor 26 simply replaces a large number of logic elements and executes a determined sequence at high speed without requiring complex judgment functions. This microprocessor 26 is a general-purpose processor,
The operation is programmed in advance and the processing device 2
The input and output of signals to and from the device under test can be controlled using three commands.

As described above, the lower processing devices 23A and 23B.

23C to 23N execute all of the actual processing for testing the device under test under the control of the higher-level processing device 21, and the higher-level processing device 21 executes all of the actual processing for testing the device under test under the control of the higher-level processing device 21.
It only controls the organic operations of the entire IC test system, such as controlling the execution of program lines 3C to 23N and collecting the pass/fail judgment results of test results.

Furthermore, in this invention, the lower processing device 23A.

23B, 23C to 23N judge whether the test data obtained for the device under test is good or bad, and the judgment result is sent to the signal lines 27A, 2, which are the only one for each device under test.
It is supplied to the upper processing device via 7B to 27N.

FIG. 2 is a diagram showing an example of the configuration of essential parts of an embodiment of the present invention. In this embodiment, four signal lines 27A.

27B to 27D are shown, and this is a case in which a maximum of four devices under test 30A, 30B to 30D can be tested simultaneously. Each lower processing device 23A,
23B, 23C to 23N and the upper processing device 21 form wired OR circuits 31A using respective signal lines 27A, 27B to 27D.

Connected via 31B, 31C to 31N and 31P,
Each lower processing device 23A, 23B, 23C to 23N has a status 32A, 32B, 3 indicating its internal state.
2C to 32N to each signal line 27A.

27B to 27D.

The IC test system has each test element 30A, 30B to 30
A number of tests are conducted on D, and normally the device under test 30A is tested only if it passes all of the test items.
, 30B to 30D are determined to be non-defective products. This signal line 27A
, 27B to 27D are the respective devices under test 30A, 30B to 30
It is used to collect the final judgment results regarding D.

For example, the output signal of the first device under test 30A is measured by the hardware module 25a, and the measurement data is sent to the lower processing devices 23A and 23B controlling the hardware module 25a.

Loaded into 23C. Lower processing device 23A.

23B and 23C correct the measured data as necessary, and compare the finally obtained data value with a reference value to determine the quality of each data value. Each determination result is output to the signal line 27A as a determination status 32a. The second device under test 30B is similarly tested using another hardware module 25b, and the measurement data is judged pass/fail by the lower processing devices 23B, 23C, etc., and each test item is The determination status 32b is output to the signal line 27B. Third. Fourth device under test 30C.

The test for 30D is also conducted using other hardware modules 25c and 25d, and the respective judgment statuses 32c and 32d are transmitted through signal lines 27C and 27, respectively.
Output to D.

According to the configuration of the present invention, when each test item is judged to be good, the status is changed to 'OJ', and when it is judged to be bad, the status is changed to '1'. Them"
0" or 'IJ status is wired OR circuit 3
Signal line 27A, via 1A, 31B, 31C to 31N,
27B to 27D, for example, even one status 32a connected to the first signal line 27A is "1".
'', the first signal line 27A carries the signal 'IJ', and the upper processing device 21 is supplied with the signal 'IJ'. In other words, the first device under test 30A is determined to be defective. On the other hand, if all the statuses 32a connected to the signal line 27A are operated to 'OJ', the 'OJ signal is carried on the signal line 27A only in this case.

When this "0" signal is read by the upper processing word W 21, the device under test 30A is determined to be non-defective. Therefore,
Signal lines 27A, 27B to 27 to the upper processing device 21
By reading the signal carried on D only once, you can know the final result of whether or not all test items were passed for each of the devices under test 30A, 30B to 30D, and the next processing can be carried out quickly and appropriately. You can proceed.

In the explanation in FIG. 2, the hardware module 25a
, 25b to 25d (Fig. 2) are 3OA of each device under test.
, 30B to 30D, the same hardware module 25 may be time-divisionally allocated to testing multiple devices under test 30A, 30B to 30D, for example, one hardware The hardware module 25A (Fig. 1) connects two devices under test 30A.
, 30B. In this case, the hardware module 25A
The two measurement data are separately processed inside the lower processing device 23A that controls the hardware module 25A, and are each output as a signal v as a separate status.
It is controlled to be placed on A27A and 27B.

In addition, each lower processing device 23A, 23B, 23C to 23N
The connection from to the higher-level processing device 21 is not limited to the signal line 27 and the wired-OR circuit 31, but may be constructed using equivalent means for realizing the present invention.

``Effects of the Invention'' As explained above, according to the present invention, the higher-level processing device is configured to exclusively control the execution of the program line, and the actual execution of the program line is controlled by the lower-level multiple processing units. Control was adopted in a hierarchical structure that was distributed among processing devices. In this way, the distributed architecture improves processing speed, and since the optimal command system is used for each layer, the processing up to the output of control signals becomes extremely fast, making it easier to test the device under test. It can be done quickly.

Further, according to the configuration of the present invention, even if multiple items are tested on multiple devices under test at the same time, the test results for the multiple items are output together to different signal lines for each device under test. . Therefore, by reading the status of each device under test only once through one signal line, the upper processing device can immediately know whether the devices are good or bad, which has a great effect on improving the testing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit block diagram showing essential parts of the present invention, and FIG. 3 is a diagram showing an example of the structure of a conventional ICC suspension system. 11: central processing unit, 12: control line, 13 hardware module, 14: microprocessor, 21: upper processing unit, 22: control lotus, 23: lower processing unit, 24: control line, 25: hardware module, 26
2 microprocessor, 27: signal line, 30: device under test, 31: wired OR circuit, 32: status.

Claims (1)

[Claims] (1) A higher-level processing device that controls the execution of the test program, and multiple lower-level processes that are controlled by the higher-level processing device and execute instructions that access the test program line by line module and instructions that update the test status. It is an IC test system consisting of a device and a plurality of hardware modules that are controlled by a higher-level processing unit and each generate test signals for the device under test and measure output signals of the device under test in accordance with the execution of instructions. It has means for determining pass/fail for multiple devices under test in each lower processing device, and the results are measured simultaneously for each device under test. An IC test system comprising means for outputting to different bit lines.