JPH05173986A - Programmable controller - Google Patents

Abstract

PURPOSE:To provide the programmable controller which enables respective CPU units to have access respective input/output units independently. CONSTITUTION:The CPU units 11 and 12 output select signals required to have access an I/O bus 2 to local I/O buses 51 and 52. The order of arrival of select signals of the CPU units 11 and 12 is decided to select the local I/O bus 51 or 52 to place the CPU unit whose select signal arrives later in a wait state in case of a conflict or select the local I/O bus 51 or 52 corresponding to the high-order CPU unit according to the predetermined priority when the select signals arrive at the same time. An I/O division and common use selection part 6 performs control over the division of select signals and clear signals to I/O units 110... or sharing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller.

[0002]

2. Description of the Related Art In a conventional programmable controller using a multi-CPU system, when accessing and outputting an I / O unit, a master CPU unit collects output data from each slave CPU unit via a shared memory or the like. Output the collected output data at once,
In addition, a method has also been used in which data is input collectively from an I / O unit and the input data is distributed to each slave CPU unit via a shared memory or the like.

[0003]

In such a case, since the slave CPU unit cannot independently perform I / O control, the master CPU unit and the slave CPU unit must be tested and debugged. Both had to be done on the motherboard.

The present invention has been made in view of the above points, and its purpose is to eliminate the distinction between a master CPU unit and a slave CPU unit, and to make each CPU unit independent of each I / O unit. It is possible to provide a programmable controller capable of accessing the CPU and performing test / debug for each CPU unit.

[0005]

To achieve the above object, the present invention comprises a power supply unit, a plurality of CPU units, an I / O unit, and a motherboard for mounting these units. CPUs connected to the I / O bus by determining the first-come-first-served basis of signals indicating access to the I / O bus from a plurality of CPU units
A means for selecting a local I / O bus from the unit and a means for weighting a CPU unit that arrives last when a signal conflicts are provided.
I / O bus is accessed by the CPU unit that issued the above signal, and CP is used in the case of contention.
After the access to the I / O bus of the U unit is completed, the access to the I / O bus of the CPU unit that arrives later is set, and there is a signal indicating that the I / O bus is simultaneously accessed from a plurality of CPU units. In addition to having a bus arbitration means for causing a CPU unit at a higher level in a predetermined priority order to access the I / O bus and putting the remaining CPU units in a standby state, a chip select signal and an output for each I / O unit are provided. It has means for controlling the division of the clear signal into the memory of each CPU unit and division or sharing based on shared data.

[0006]

According to the present invention, the bus arbitration means is provided, and the chip select signal for each I / O unit and the output clear signal are controlled based on the division and shared data set in the memory of the CPU unit. Since there is a means for
I / O bus can be accessed and therefore each I / O
Each CPU unit can be controlled independently, and as a result, each CPU unit can be separately tested and debugged. If each CPU unit is combined after the test and a comprehensive test is performed, testing and maintenance are efficient. You will be able to do well.

[0007]

EXAMPLES The present invention will be described below with reference to examples. Figure 1
Two C's used in the programmable controller of the present invention
PU unit 1 ₁1₂CPU unit using
2 shows the configuration of an embodiment of each CPU unit 1₁1₂
I / O centering on the microprocessor MPU
Get the access time needed to access bus 2
Has a unique CPU wait circuit 3 for I / O
The necessary signals to access bus 2 are CPU
To 1₁1₂To the local I / O bus via buffer 4
5₁5,₂Is output with.

In these configurations, since the other CPU unit is not accessed, the local I / O buses 5 ₁ , 5 ₂ are unidirectional, and the shared memory 7 for exchanging calculation data with each other is a CPU. It is provided outside the units 1 ₁ and 1 ₂ . Of course, this shared memory 7 does not include I / O access information. Further, the shared memory 7 is completed by using the CPU units 1 ₁ and 1 ₂ of the same type to construct a multi-CPU system.

The bus arbitration unit 8 comprises a bus selection unit 9 and a wait controller 10, and these hardwares are provided outside the CPU units 1 ₁ and 1 ₂ . Then, the bus arbitration unit 8 receives local I / O from each of the CPU units 1 ₁ and 1 _2.
When a select signal indicating access to the I / O bus 2 is output through the O bus 5 ₁ , 5 ₂ , the first-arrival order of this select signal is determined and the local I / O bus 5 ₁ or 5 ₂ is selected by the bus selector. 9, the weighting signal from the weight controller 10 is used for weighting the CPU unit of the later arrival in the case of competition, and in the case of the same arrival, CPU units of lower priority are assigned according to a predetermined priority order. Apply weight. The bus arbitration unit 8 inputs the sampling clock CLK, arrival order determination in the sampling clock CLK, wait width setting of the weight controller 10, CPU unit 1 ₁ has gained access
Alternatively, the bus cycle width for accessing the I / O bus 2 of 1 ₂ is obtained.

[0010] I / O division, sharing selector 6 is intended to perform I / O unit 11 ₀ ... chip select signal for, or to divide the clear signal in the CPU unit ₁ 1, 1 _2, the control to be shared, its control content is divided set by the CPU unit 1 _1, 1 ₂ in the memory external programmer (not shown) to (4), based on shared data.

FIGS. 2A and 2B show the overall configuration of this embodiment. In this embodiment, the CPU unit 1 ₁ ,
1 ₂ , I / O unit 11 _0, and the shape and dimensions of the power supply unit 12 are modularized, and the power supply unit 12, CPU units 1 ₁ , 1 ₂ , I / O are mounted on the motherboard 13.
The units _110, ... Are detachably mounted in this order to form a programmable controller.

3A to 3D show the contents of the registers provided in the I / O division / share selection unit 6, and FIG. 3A shows the CPU units 1 ₁ and 1 _2. Shows the status register of. D ₁ bit is multi-CP
Bits for distinguishing the positions of U units 1 ₁ and 1 _2. For example, if the content is 0, CPU unit 1 ₂
If 1, the CPU unit ₁₁ is indicated. The bit D _{3 is} a bit for detecting the presence or absence of another CPU unit. For example, if the content is 1, it indicates yes, and if it is 0, it indicates no. This register is a read-only register.

FIG. 1B shows a write-only register for clear and chip select division designation. D ₀ ... Corresponds to the I / O unit 11 ₀ ..., respectively, and 1 can be written in that bit. For example, CPU for the relevant I / O unit
The unit 1 ₁ indicates access, and writing 0 indicates that the CPU unit 1 ₂ accesses the I / O unit.

FIG. 3C shows a write-only register for clearing and specifying chip select sharing. D ₀ ... Corresponds to the I / O unit 11 ₀ . When written, it indicates sharing with the I / O unit, and when 0 is written, it indicates division. FIG. 6D shows a write-only register for notifying the mounting of the CPU unit, and when 1 is written in the bit of D ₀ , the presence / absence of another CPU unit is detected.

FIG. 4 is a CPU for storing division / share designation data for setting in the I / O division / share selection unit 6.
Shows the memory provided in units 1 ₁ and 1 ₂ ,
This memory has an area for storing 8-bit division designation data D _A and 8-bit shared designation data D _B. Then, the power is turned on as shown in FIG.
_1, when 1 ₂ start, written by the start register indicating the CPU existence flag in Figure 3 (d). After that, the status register shown in FIG. 3A is read out, and it is determined whether two CPU units are mounted in the multi-state or whether the CPU units 1 ₁ and 1 ₂ are located. Then, after this determination, create a refresh table, and if the above determination result is not a multi-state but a single state, move to step, and if it is a multi-state, in step,
It is determined whether or not the position of the CPU unit 1 ₁
At the position of the unit 1 ₁ , the chip select and clear division data are set in the register of FIG. 3B based on the division designation data D _A shown in FIG. 4, and further based on the sharing designation data D _B. It is set in the register of (c) and the process proceeds to other initialization.

[0016] If it is determined that the position of the CPU unit 1 ₂ in step step, skipping the process proceeds to the next initialization. In other words, in the multi-CPU state, C
The PU unit 1 ₁ sets division and sharing. By performing the processing described above, the CPU units 1 ₁ and 1 ₂ independently operate the I / O unit 11 _0.
... becomes controllable.

[0017]

The present invention has means for controlling the chip select signal and the output clear signal for each I / O unit based on the division and shared data set in the memory of the CPU unit, as well as having the bus arbitration means. Since it has, the CPU units can access the I / O bus without conflict, and each I / O unit can be controlled independently for each CPU unit.
It is possible to perform testing / debugging separately for each unit, and if each CPU unit is connected after the test and a comprehensive test is performed, there is an effect that the test and maintenance can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of a multi-CPU system according to an embodiment of the present invention.

FIG. 2A is a schematic top view showing a state of being mounted on a motherboard according to an embodiment of the present invention. (B) is a schematic front view showing a state of being mounted on a motherboard according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a register of an I / O division / share selection unit used in an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a division / share setting memory of a CPU unit used in an embodiment of the present invention.

FIG. 5 is a flowchart for explaining the operation of the embodiment of the present invention.

[Explanation of symbols]

1 ₁ , 1 ₂ CPU unit 2 I / O bus 5 ₁ , 5 ₂ Local I / O bus 6 I / O division / share selection unit 8 Bus arbitration unit 11 ₀ ... I / O unit

Claims (1)

[Claims] 1. A power supply unit, a plurality of CPU units, an I / O unit, and a motherboard for mounting these units, and showing access to an I / O bus from the plurality of CPU units. Means for selecting the local I / O bus from the CPU unit connected to the I / O bus by judging the first-arrival order of the signal, and means for weighting the CPU unit that arrives last when the signal conflicts. And I / in the case of non-conflict
Accessing the O bus The I / O bus is accessed by the CPU unit that issued the above signal, and in the case of conflict, the CPU
After the access to the I / O bus of the unit is completed, set the access to the I / O bus of the CPU unit that arrives later,
When there is a signal indicating that the plurality of CPU units simultaneously access the I / O bus, the upper CPU unit in the predetermined priority order accesses the I / O bus, and the remaining CPU units are in the standby state. In addition to the bus arbitration means, a chip select signal for each I / O unit and an output clear signal for each C
A programmable controller having means for controlling division and sharing based on shared data set in a memory of a PU unit.