JPH05173985A - Programmable controller - Google Patents

Abstract

PURPOSE:To provide the programmable controller which enables respective CPU units to control respective I/O units independently and can perform test debugging by the CPU units. CONSTITUTION:A bus arbiter circuit part 3 connects the CPU units 11... through local I/O buses 21... and also connects the I/O units 51... through an I/O bus 4. This bus arbiter circuit part 3 arbitrates a conflict when conflicting select signals indicating to have access the I/O units 51... are outputted from the respective CPU units 11... one CPU unit which is given priority among the CPU units 11... by the arbitration can control the corresponding I/O unit among the I/O units 51... through the local I/O bus selected among the 21... and the I/O bus 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller.

[0002]

2. Description of the Related Art In a conventional programmable controller using a multi-CPU system, when accessing and outputting an I / O unit, a master CPU unit collects output data from each slave CPU unit via a shared memory or the like. Output the collected output data at once,
In addition, a method has also been used in which data is input collectively from an I / O unit and the input data is distributed to each slave CPU unit via a shared memory or the like.

[0003]

In such a case, since the slave CPU unit cannot independently perform I / O control, the master CPU unit and the slave CPU unit must be tested and debugged. Both had to be done on the motherboard.

The present invention has been made in view of the above points, and its object is to eliminate the distinction between a master CPU unit and a slave CPU unit, and to make each CPU unit independently an I / O unit. An object is to provide a programmable controller that can be accessed and can be tested and debugged for each CPU unit.

[0005]

In order to achieve the above-mentioned object, an invention according to claim 1 is a power supply unit, a plurality of CPU units, an I / O unit, and a motherboard for mounting these units. And a bus arbitration unit that arbitrates conflicts when a plurality of CPU units access an I / O unit, and a shared memory that allows random access from each CPU unit and exchanges data between the plurality of CPU units. A parameter for setting an I / O unit to be controlled by the CPU unit is written from each CPU unit to the bus arbitration means, and the bus arbitration means arbitrates the competition based on the written parameter. .

According to a second aspect of the invention, in the invention of the first aspect, the I / O units to be controlled by the CPU units can be duplicated in each CPU unit. According to a third aspect of the present invention, in the second aspect of the invention, the programs of the respective CPU units are described in a programming language corresponding to the I / O unit to be controlled by the CPU unit.

[0007]

According to the first aspect of the invention, the power supply unit, the plurality of CPU units, the I / O unit,
Motherboards for mounting these units, bus arbitration means for arbitrating conflicts when a plurality of CPU units access I / O units, and random access from each CPU unit, data between a plurality of CPU units. I / O controlled by each CPU unit by a shared memory for exchanging
A parameter for setting a unit is written in the bus arbitration means, and the bus arbitration means arbitrates the competition based on the written parameter, so that each CPU unit does not conflict with each other and the I / O of the preset control target is controlled. The units can be controlled so that each CPU unit can independently perform test and debug independently.

In particular, according to the second aspect of the invention, when it is difficult to divide the control program into I / O units, it is possible to control from a plurality of CPU units. According to the third aspect of the present invention, a programming language suitable for controlling the I / O unit can be used. As a result, the program is simplified, the debug effect is improved, and the visibility of the program is improved.

[0009]

EXAMPLES The present invention will be described below with reference to examples. Figure 1 shows a schematic construction of the embodiment, connecting a plurality of CPU units 1 ₁ ... a in this embodiment the local I / O bus 2 ₁ ... via the respective bus arbitration circuit unit 3, the bus arbitration circuit section Three
A plurality of I / O units 5 ₁ ...
Are connected. Bus arbitration circuit section 3 performs the arbitration control described later, the CPU unit 1 ₁ ... has a built-in random access shared memory 6 for exchanging data with each other inside.

The bus arbitration circuit section 8 comprises a bus selection function and a wait controller, and when each CPU unit 1 ₁ ... Outputs a select signal indicating access to the I / O unit 5 ₁ ... Of the local I / O bus 2 ₁ ... Is selected by the bus selection function, the CPU unit of the last arrival is weighted in the case of contention, and in the case of the same arrival, according to a predetermined priority order. , A weight is applied to a CPU unit having a low priority. Of course, the conflict may be avoided from the beginning only by the priority order.

2 (a) and 2 (b) show the overall construction of this embodiment. In this embodiment, the CPU unit 1 described above is used.
₁ ..., I / O unit 5 ₁ ... and the power supply unit 6 are modularized in shape and size, and the power supply unit 6, the CPU unit ₁₁ ...
_The programmable controller is configured by detachably mounting in the order of ₁ ...

Therefore, in the programmable controller of the present invention, the CPU unit ₁₁ ...
I / O unit that U unit exclusively accesses 5 ₁
... is determined, and parameters corresponding to the I / O unit 5 ₁ used exclusively in the initial stage are sent to the bus arbitration circuit unit 3 and written in a storage unit such as a register of the bus arbitration circuit unit 3.

Here, for example, the CPU unit ₁₁ is an I / O
If the CPU units 1 ₂ occupy and use the units 5 ₁ and 5 ₂ and the I / O units 5 ₃ and 5 ₄ occupy and use, the CPU unit 1 ₁ uses the I / O units 5 ₁ and
5 ₂ may be written the program that controls the likewise may be only a description program for controlling the CPU unit 1 _2, I / O unit 5 _3, 5 _4. Each of the CPU unit 1 ₁ ... program capacity thus decreases, for example, the program capacity X in the case of controlling the four I / O unit 5 ₁ to 5 ₄ by one CPU unit was FIGS. 4 (a) Against the two CPs as above
When controlling separately by U units 1 ₁ and 1 ₂
As shown in (b), the respective program capacities are X ₁ , X ₂
Therefore, the execution time T of one scan of the program can be shortened to T'as shown in the figure.

When the CPU units 1 ₁ ...
Initialization is performed to write the parameters of the unit 1 ₁ ... Into the register of the bus arbitration circuit section 3. Then, the bus arbitration circuit section 3 changes from the CPU unit 1 ₁ to the I / O unit 5 ₁
When a select signal for access to ... Is output, in the case of conflict, arbitration is performed to determine the priority CPU unit 1 ₁ ... And the I / O unit 5 ₁ corresponding to this CPU unit is determined. The local I / O bus 2 ₁ ... Is selected so that control is possible. If there is no conflict, the local I / O bus 2 ₁ is selected so that the accessed CPU unit 1 ₁ can control the corresponding I / O unit 5 ₁ .

In this way, each CPU unit can independently control the corresponding I / O unit regardless of the presence or absence of other CPU units. In the above embodiment, the I / O units 5 ₁ ... Are exclusively used so that the CPU units 1 ₁ ... Which are subject to use control do not overlap, but the control program may be divided in units of I / O units. Multiple Cs for difficult cases
It may be possible to control from the PU unit 1 ₁ .
For example, the I / O units 5 ₁ , 5 ₂ , and 5 ₅ are set to be controlled by the CPU unit 1 ₁ , and the I / O unit 5
_{If 3} , 5 ₄ , 5 ₅ are set to be controlled by the CPU unit 1 ₂ , it is possible to control the I / O unit 5 ₅ from both CPU units 1 ₁ and 1 ₂ . is there.

Each I / O unit 5 ₁ has a characteristic function, and therefore there is a programming language suitable for each function. For example, I / O unit 5
_{When 1} and 5 ₂ are digital I / O units and I / O units 5 ₃ and 5 ₄ are communication control I / O units, CPU units 1 ₁ and 1 that occupy each of them are controlled.
_{The second} program may be described in a language corresponding to each I / O unit 5 ₁ .

That is, the CPU unit 1 ₁ describes a program in a ladder language suitable for I / O control, and the CPU unit 1 ₂ uses Bas suitable for data processing, character string processing, etc.
All you have to do is write the program in the ic language. Data required between the respective CPU units 1 ₁ ... Can be exchanged via the shared memory 6 in the bus arbitration circuit section 3.

By using a programming language suitable for controlling the I / O units 5 ₁ ... In this way, the program is simplified, the debugging effect is improved, and the visibility of the program is improved.

[0019]

According to the invention described in claim 1, a power supply unit, a plurality of CPU units, an I / O unit, a motherboard for mounting these units, and a plurality of C's.
Each CPU unit includes a bus arbitration unit that arbitrates contention when the PU unit accesses the I / O unit, and a shared memory that can be randomly accessed from each CPU unit and exchanges data between a plurality of CPU units. A parameter for setting the I / O unit to be controlled by the CPU unit is written from the unit to the bus arbitration means, and the bus arbitration means arbitrates the competition based on the written parameter. It is possible to perform control for the set I / O unit of the usage control target without conflict, so that each CPU unit can independently perform test / debug, and as a result, efficient debug adjustment of the program can be performed. There is an effect.

Particularly, the invention according to claim 2 has an effect that it is possible to control from a plurality of CPU units in case that it is difficult to divide the control program into I / O units. Further, the invention according to claim 3 can use a programming language suitable for controlling the I / O unit, and as a result, the program can be simplified, the debugging effect can be improved, and the visibility of the program can be improved. is there.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of an embodiment of the present invention.

FIG. 2A is a schematic top view showing a state of being mounted on a motherboard according to an embodiment of the present invention. (B) is a schematic front view showing a state of being mounted on a motherboard according to an embodiment of the present invention.

FIG. 3A is an explanatory diagram of a program capacity of a comparative example corresponding to an embodiment of the present invention. (B) is an explanatory view of a program capacity of one embodiment of the present invention.

[Explanation of symbols]

1 ₁ ... CPU unit 2 ₁ ... Local I / O bus 3 Bus arbitration circuit section 4 I / O bus 5 ₁ ... I / O unit 6 Shared memory

Claims (3)

[Claims] 1. A power supply unit, a plurality of CPU units, an I / O unit, a motherboard for mounting these units, and a bus for arbitrating conflicts when the plurality of CPU units access the I / O unit. Random access is possible from the arbitration means and each CPU unit,
A shared memory for exchanging data between a plurality of CPU units is provided, and a parameter for setting an I / O unit to be controlled by the CPU unit is written from each CPU unit to the bus arbitration means, and the written parameter is written. A programmable controller characterized in that the bus arbitration means arbitrates the competition based on the above. 2. The programmable controller according to claim 1, wherein the I / O units to be controlled by the CPU unit can be duplicated in each CPU unit. 3. The programmable controller according to claim 1, wherein the programs of the respective CPU units are described in a programming language corresponding to the I / O unit to be controlled by the CPU unit.