SU1483491A1 - Memory control unit - Google Patents

Abstract

The invention relates to computer technology and can be used in microcomputer-based systems for controlling operational and permanent storage devices. The aim of the invention is to increase the reliability of the operation. The device contains an address register, a comparison circuit, an address control block, a diagnostic signal generating unit, triggers 7, NOT elements, AND elements, OR elements 23, AND-NOT elements 26, control inputs and outputs, a data bus — addresses. The goal is achieved by expanding the possibilities of monitoring and diagnosing errors. 2 hp f-ly, 3 ill., 2 tab.

Description

The invention relates to computing and can be used in micro-VM based systems with a common core for managing operational and permanent storage devices.

The purpose of the invention is to increase the reliability of the operation.

At AIG.1, a functional diagram of the proposed device is presented; in FIG. 2, the block diagram of the address path control block is functional; FIG. 3 is a functional block diagram of the formation of diagnostic signals.

In the Figures, the following symbols are accepted: address register 1, - circuits 2 "- 2 comparisons, address control block 3; block 4 Lorii diagnostic signals; bidirectional switches 5 ,, - 53; triggers

6 elements of 9-12; elements And 13-21; SchS elements 22-24; elements AND NOT 25-27; the inputs 28 of the byte write feature, the inputs 29 of the write mode feature, the inputs 30 of the read mode feature; inputs 31-33 signs of address decoding mode; an input 34 of blocking address delays, an exchange synchronization input 35, a sample input 36; input 37 is a sign of erroneous memory operation, input 38 is a sign of an error in the low byte; input 34 indicates an error in the high byte; Input 40 is a sign of an error in the exchange cycle; initial installation input 41, input 42 of a pulse indication of a memory error; an input 43 of an indication of a power source failure; input 44 of the write-read control signals; pin connection control input 45

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data addresses; the input 46 is a sign of readiness of the memory; input 47 low-order data device addresses; resolution outputs of the lower 4th and higher 49 bytes; read resolution output 50; output 51 permit the issuance of data devices; the first device control output 52; output 53 synchronization of the exchange device; yields 54 and 55 signs of the condition; output 56 sign of erroneous operation of the device; a second device control output 57; address output 58 of the device; input-output 59 of the area code code of the device; bus 60 data addresses of the device; communication glands 61-75 between device elements; multiplexers 76 - 76jf 77; the decoder 78, the outputs 79 - 79 #. multiplexers; output 80 bidirectional commutator; triggers 81 and 817; elements EXCLUSIVE OR 82, and 82g, elements OR 83, 86; elements 87 and 90; the element is NOT 91; elements 92 and 99; element OR 100; inputs 10 - multiplexers; inputs 102 and 103 logical units and zero; Trig834914

to the memory address output 57 of the memory selection and output 64 of the block 3 corresponding to the address code. Upon the arrival of any of the signals

e, at the inputs 35 and 36 of the device, the address code arriving at pin 60 is fixed in the address register 1 simultaneously with fixing the levels of the signals at input 28 in the 6 n trigger on the input signal.

U de 47 in trigger 7. Next, the device performs a read cycle or a write cycle in a controllable memory, or in a read or write in block 4 trigger schemes, depending on the presence

15 signals at the inputs 29, 30, 35, 36 devices. The reading cycle begins upon arrival of the signal at input 30 and after Tynaiorjero through the elements NOT 10, AND 19, AND-NOT 25 at the output 50 of the signal

20 permitting the reading of a word from the controlled memory, subject to the presence of a permission signal at the output 64 of block 3 and the absence of a blocking signal at the output 73 of block 4, the write cycle starts at arrival at the input 29 of the signal input through the HE element 11, elements 20 and 21 and NAND elements 26 and 27 to outputs 48 and 49 in accordance with the signal level at the output

Hera 104-1 1 1; the element OR 2; elements 30 and 28 and trigger values of 7, with a VALUE OF, 114; the element PE 115, the element 116 delay; the input 137 is a logical zero; elements NOT 118-120; trigger group 121; elements And 122-124; elements OR 125-128, elements OR-NO 129-133, elements of communication 134-138 between the elements.

The device works as follows.

The memory management device operates in the absence of active levels of blocking signals at inputs 34, 44 and 45. At inputs 31-34, the device is assigned one of the address selection modes shown in Table 1.

In accordance with the address selection mode specified by the device, the device is assigned the code of the controlled memory number by the inputs 59, i.e. the values of one, two or three address code bits are set, if they match (the address code bits received on the bus 60 through block 5 (, address register 1 and block 3) circuit 2 (comparison gives the active signal level at output 67, allowing the output of the active signal level

35

40

45

50

55

the presence of a permission signal at output 64 of block 3 and the absence of a blocking signal at output 73 of block 4. In response to signals at outputs 48–50 of the device, the controlled memory must output a signal to input 46 of the device, which through HE and 12 elements and 18 A trigger 8 is set. At the same time, the active level of the signal at the output 53 of the device is formed and the element 18 issuing the control signal to connect to the shared bus of the controlled memory at the output 51 of the device during the read cycle is allowed. The reset of the trigger 8 to the initial state is carried out through the element OR 22 at the synchronous input of the trigger 8 by the end of the signals at the inputs 28 or 30.

The blocking signal for issuing control signals at output 73 of block 4 is formed by element I 22 in it when the active level of the signal- arrives at the device input 40, as well as when there are errors in the device by means of control or at the inputs 37-39, 42 and 43 of the device signals are signs of errors. On the elements And 13-16 implemented a control that displays incorrect

five

0

five

0

five

the presence of a permission signal at output 64 of block 3 and the absence of a blocking signal at output 73 of block 4. In response to signals at outputs 48–50 of the device, the controlled memory must output a signal to input 46 of the device, which through HE and 12 elements and 18 A trigger 8 is set. At the same time, the active level of the signal at the output 53 of the device is formed and the element 18 issuing the control signal to connect to the shared bus of the controlled memory at the output 51 of the device during the read cycle is allowed. The reset of the trigger 8 to the initial state is carried out through the element OR 22 at the synchronous input of the trigger 8 by the end of the signals at the inputs 28 or 30.

The blocking signal for issuing control signals at output 73 of block 4 is formed by element I 22 in it when the active level of the signal- arrives at the device input 40, as well as when there are errors in the device by means of control or at the inputs 37-39, 42 and 43 of the device signals are signs of errors. On the elements And 13-16 implemented a control that displays incorrect

514834916

combinations of signals at the inputs 28 - 30, trigger values

46 and 47 devices, as well as output 64. The controls of unit 3 are implemented on the duplicate main address selection path multiplexers 76z, 4 -c circuits, and comparison; Triggers 8 (g, elements EXCLUSIVE- 1 GAY OR.

If the results of the selection of the address code in the main and duplicate paths do not coincide, block 3 outputs a signal to output 65. At elements 94-99 and element OR 00, the signals at the outputs 57 of the device, i.e. When more than one active level appears at outputs 57, a signal is generated at output 66 of block 3. Signals at inputs 37-39 of the device are fixed at block 4 at the time of their reliable value in triggers 104, 105, -I 107 according to signals at inputs 67 or 68 units 4, and in the triggers 106 and 108 - the signals at the outputs 48 and 49 of the device, respectively. The flip-flop triggers 104-108, as well as flip-flop 111, the output of which generates a signal for detecting an error at the output 56 of the device, are reset when there is no access to the device via the common bus, i.e. in the absence of signals at inputs 67, 58 of block 4. The active levels of signals at outputs 134-138 of flip-flops 104-108, as well as other signs of errors received at inputs 42, 43, 65, 66, and block 4, establish the corresponding discharge pattern The trigger groups 121, through the OR elements 125-128 and the OR-NOT 129 element, set the trigger 111. In addition, the state of the triggers 109, 110 can change in accordance with Table 2.

The outputs 75 of the group of flip-flops 121 are accessible through the switch 5 for reading over the device bus 60 with special accesses to it in the read cycle as an external device at the address corresponding to the specified selection mode and controlled memory number from the address area (170000 + 170008) B. Upon completion of this call, zero values are written to all bits of the trigger group 121. When the device is addressed to this address, the installation is performed in a write cycle.

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Claims (3)

the signal levels of the block 4. By actively entering the inputs 41, the devices have the initial mouths 109 and 110 and all the triggers 121, i Formula from 1, a device containing a comparison circuit, tr 15 re element NOT, nine virgin elements OR, and where the input is a sign of the device connected to the input of the first tr input to the first element of the first and second output of the first trigger element is NOT connected to the second alt connecting the recording mode and reading the device to the second and third t, the second output to the first input, the second input, the first inputs of the third and fifth elements of the third element H to the second input, the second to the third inputs, third and third elements of the sixth hands and the seventh register clock to the strobe I n, sync inputs n flip-flops, inverse trigger connected to the first element OR input of the first element and information trigger connected to the second input of the second and to the input of the lower p address of the device, in the second elements And respectively to the second and fifth elements of which are connected to the first inputs first steps are NOT, the second ones are connected to the input of the recording control unit, the output is one third connected to the sync thirty 35 40 45 50 55 trigger values 0 five 09 and BUT by the value of the signal levels at the input 61 of block 4. The active level of the signal at the input 41 of the device is the initial setting of the triggers 109 and 110 and all bits of the group of triggers 121, i Q Invention formula 1, A memory management device containing the address register of the comparison circuit, three flip-flops, four NOT elements, nine II elements, three OR elements, three AND-NOT elements, the input sign of the device bytes being written to to the input of the first trigger, the first input of the first element I, the first inputs of the first and second elements of the SLI, the output of the first trigger of the Cherr, the first element is NOT connected to the first input the second of the I5 Bxoni write mode and the read mode of the device are connected to the inputs of the second and third element NO, the output of the second element of the NP pg, gklchen to the first input of the third element AND, the second input of the primary element I, the first inputs of the third, fourth and fifth elements 1Г71Т, r - the course of the third element is NOT connected to the second input of the second element 21 tm L, the second inputs of the third element And the third element 1, the first input of the sixth and seventh elements And, the synchronous input address register is connected to the gate input of the comparison circuit, the synchronous inputs of the first and second triggers, the inverse output of the second trigger OR and to the third input of the first element AND, the direct output and the information input of the second trigger are connected respectively to the second input of the second OR element and to the low-order input of the device address data, the outputs of the first and second OR elements are connected respectively to the second inputs of the fourth and n H elements whose outputs are connected respectively to the first inputs of the first and second NAND elements, the second inputs of which are connected to the input of blocking the read-write control signals of the device, the output of the third lementa OR connected to the clock terminal of the third 0 five 0 five 0 five the trigger, the information input and the input of the installation in 1 of which are connected respectively to the input of the logical zero of the device and to the output of the eighth element II, with the fact that, in order to increase the reliability of the operation, the control unit is entered into it addresses, a diagnostic signal generation unit and a bidirectional switch, with the inputs of the first to eighth address control unit being connected to the inputs of the read mode, first, second, third signs of the address decoding mode, blocking, respectively. address radios, exchange synchronization, device sampling, address register output, comparison circuit output, input control of the address control unit connected to the device’s output-code of the address space of the device, output of the bi-directional switch connected to the address register information input, ninth input of the address control block and to the first input of the diagnostic signal generation unit, the inputs of which from the second to the nineteenth are connected respectively to the output of the comparison circuit, the first, second and third outputs of the unit control of addresses, entrances of the sign of erroneous memory operation, sign of an error in the low byte, sign of an error in the high byte, sign of an error in the exchange cycle, initial setting, impulse sign of a memory error, sign of a failure of the device’s power source, outputs of the second, third first and nine elements II, the outputs of the second, first and third elements of the NAND, the outputs from the fourth to the ninth address control block are connected respectively to the first and second information inputs of the comparison circuit, strobe input of the comparison circuit , the first and second outputs of the sample control and to the address output of the device, the tenth output of the address control block is connected to the first input of the ninth AND element, the second input of the sixth And element, the third inputs of the fourth and fifth elements II, the sign of readiness of the device memory through the fourth element is NOT connected to the second input of the ninth AND element and to the first input of the eighth AND element, the second input of which is connected to the third output0 five 0 five 0 five 0 five 0 five The control unit for the address control, the output of the sixth AND element is connected to the first input of the third NAND element, the second input of which is connected to the input of blocking the read control signals of the device, the outputs of the diagnostic signal generating unit are connected respectively to the transmission direction input and the bi-directional information input the switch, the first and second outputs of the device state, the output of the sign of erroneous operation of the device and the third inputs of the first, second and third elements AND-NOT, the outputs of which are Parameters respectively for the low-byte, high-byte and device read permission outputs, the forward and inverse outputs of the third trigger are connected respectively to the second input of the seventh And element, and to the device synchronization output, the seventh And output of the device is connected to the output output of the device, The device address bus connection control input is connected to the control input of a bidirectional switch, the input / output of which is connected to the device address data bus, 2. The device according to claim 1, wherein the address control unit contains five multiplexers, a decoder, two triggers, two EXCLUSIVE OR elements, three comparison circuits, two bidirectional switches, twelve AND elements, five OR elements and a NOT element, with the first input of the block connected to the first control input of the first multiplexer, the first input of the first AND element and the first OR element, the second input of the block connected to the second inputs of the first AND and OR elements, the second control first multiplexer output the first elements AND and OR and the second input of the block are connected to the control inputs of multiplexers from the second to the fifth, to the control input of the first bidirectionally on the switch, the third input of the block is connected to the first input of the second element AND, the fourth input of the block is connected to the first input of the third element And to the sample inputs of the first and second bidirectional switches, the fifth input of the unit is connected 91483491 to the second input of the third element AND, the first input of the fourth element AND, the first input of the second element OR, the sixth input of the block is connected to the third input, through the first element NOT to the second input of the fourth AND element and the first input of the third element OR, the seventh input of the block is connected to the first and second information inputs - JQ elements And from the seventh through twelve multiplexers from the first to the third, information inputs of the first and second bidirectional switches, inputs from the first to the eighth fifth element And, the control panel input of the bidirectional switch is connected to the input of the logical zero of the device, the eighth block input is connected to the first input of the first element EXCLUSIVE OR, the second input is the third - 2Q input of that element AND, the output of which thirty 35 its element OR, the gate input of the decoder, the input-output of the block is connected to the input-output of the first bidirectional switch, the ninth input of the block is connected to inputs from the first to the eighth sixth element And, the first and second information inputs of the fourth and fifth multiplexers, the outputs of the fourth and The five elements AND are connected to the first} and second outputs of the block, the output of the first comparison circuit is connected to the first input of the second element EXCLUSIVE OR, and to the third output of the block, the output of the second multiplexer is connected to a quarter th output unit, an output of the first bidirectional commutator is connected to the fifth output block, the first data inputs of the first, second and third comparison circuits .-. nor, the second inputs of which are connected respectively to the outputs of the third, fourth and fifth multiplexers, the output of the fourth element I is connected to the synchronous input of the first trigger and to the sixth output of the block, the output of the second element OR is connected to the seventh output of the block, the output of the decoder is connected to the eighth output of the block, the output of the second bidirectional multiplexer is connected to the ninth output of the block, the output of the third element OR is connected to the tenth output of the block, the first discharge of the decoder is connected to the first inputs of the seventh, The eighth and ninth elements And the second bit of the output of the decoder is connected to the second input of the seventh element And, the first inputs of the tenth and 50 55 poi o is connected to the stropra: with the input of the first comparison circuit, the gate inputs of the second and third comparison circuits are connected respectively to the input of the logical unit of the device to the output of the sixth element And, the outputs of the second and third comparison circuits are connected respectively to the information inputs of the first and second triggers, outputs which: are connected respectively to the second inputs of the first and second elements EXCLUSIVE OR, the outputs of which are connected respectively to the first and second inputs of the fourth element OR. 3. The device according to claim 1, characterized in that the diagnostic signal generating unit contains eight triggers, five elements OR NOT, five elements OR, five elements AND, four elements NOT, a delay element and a group of triggers, the first input block is connected to the information inputs of the first and second triggers, the second input of the block is connected to the first input of the first OR element, the output of which is connected to the trigger inputs from the third to the seventh and to the first installation input of the eighth trigger, and through the delay element clock terminal of the third, fourth and sixth flip-flops, the output of the first AND element is connected to the clock terminal of the first and second flip-flops, a group of flip-flops connected to outputs of the first output unit, an output of the second AND element is connected to the second output unit and the clock terminal of flip-flops group informaJO the eleventh And elements, the third bit of the decoder output is connected to the first input of the twelfth And element, the second inputs of the eighth and eleventh And elements, the fourth digit of the decoder output is connected to the second inputs of the eleventh, tenth and ninth elements And, outputs connected to the inputs from the first to the sixth fifth element OR, the first output of the first multiplexer is connected to the first input of the decoder, the second output of the first multiplexer is connected to the second input of the depot, and the output of the second tripod the second 25 thirty five .-. 0 five poi o is connected to the stropra: with the input of the first comparison circuit, the gate inputs of the second and third comparison circuits are connected respectively to the input of the logical unit of the device to the output of the sixth element And, the outputs of the second and third comparison circuits are connected respectively to the information inputs of the first and second triggers, outputs which: are connected respectively to the second inputs of the first and second elements EXCLUSIVE OR, the outputs of which are connected respectively to the first and second inputs of the fourth element OR. 3. The device according to claim 1, characterized in that the diagnostic signal generating unit contains eight triggers, five elements OR NOT, five elements OR, five elements AND, four elements NOT, a delay element and a group of triggers, the first input block is connected to the information inputs of the first and second triggers, the second input of the block is connected to the first input of the first OR element, the output of which is connected to the trigger inputs from the third to the seventh and to the first installation input of the eighth trigger, and through the delay element sync third, fourth and sixth triggers, the output of the first element And is connected to the sync inputs of the first and second triggers, the outputs of the group triggers are connected to the first output of the block, the output of the second element And are connected to the second output of the block and the synchronous inputs of the group triggers, information inputs of which are connected to the logical input device zero, the third block input is connected to the first input of the second element OR and the setup input to 1 of the first trigger of the group, the fourth block input is connected to the first input of the third element and OR to the installation input in 1 of the second trigger of the group, the fifth input of the block is connected to the second input of the first element OR and to the first inputs of the first second element AND, the sixth input of the block is connected to the information input of the third trigger, the output of which is connected to the first input of the fourth element OR to the installation input in 1 of the third group trigger, the seventh block input is connected to the information inputs of the fourth and fifth triggers, the outputs of which are connected respectively to the installation inputs in the fourth and fifth triggers of the group, output Fourth and fifth triggers are connected respectively to the first and second inputs of the fifth OR element, the output of the sixth trigger is connected to the third input of the fifth OR element and to the installation input of the 1st sixth group trigger, the output of the seventh trigger is connected to the fourth input of the fifth the OR element and the setup input into the 1st seventh group trigger, the eighth block input is connected to the information inputs of the sixth and seventh flip-flops, the ninth block input is connected to the first inputs of the third, fourth and fifth elements AND, the tenth block input Through the first element is NOT connected to the installation input of the eighth group trigger O and to the first inputs of the first and second PLI-PE elements, the outputs of which are connected respectively to the first installation inputs of the first and second triggers, the KOS outputs are connected respectively to the third and fourth outputs of the unit , the output of the eighth trigger is connected to the fifth output of the block and to the second input of the fifth AND element, the output of which is connected to the sixth input of the fourth OR element and to the output of the installation of the 1st ninth group trigger, the twelfth input unit connected to Q § 0 5 0 0 five 0 five the second input of the second OR element and the installation input of the tenth group trigger, the thirteenth block input is connected to the third input of the fourth OR element and the installation input to the 1st eleventh group trigger, the fourteenth input of the block is connected to the installation input 1 twelfth trigger group, nth nineteenth. the input of the block is connected to the third input of the third OR element and to the installation input of 1 thirteenth group trigger, the sixteenth input of the block is connected to the fourth input of the fourth OR element and to the installation input of 1 fourteenth group trigger, the seventeenth input of the block is NOT connected to syncro through the second element input of the seventh trigger, the eighteenth input of the block through the third element is NOT connected to the second input of the first element AND and to the synchronous input of the fifth trigger, the nineteenth input of the block through the fourth element is NOT connected to the second One of the second element AND, the output of the second element OR is connected to the second input of the first element OR NOT and the first inputs of the third and fourth elements OR NOT, the output of the third element OR is connected to the second inputs of the third element AND and the fourth element OR, the output of which is connected to the second setup input of the eighth trigger, the output of the fourth element OR is connected to the first input of the fifth element OR NOT, the second input of the second element OR NOT, and the third input of the fourth element OR NOT, the output of the fifth element OR is connected to the second th input of the fourth element AND to the fourth input of the fourth element OR-GE, the output of the third element AND is connected to the second input of the third element OR-AND to the third input of the first element OR NOT, the outputs of the third and fifth elements OR NOT are connected respectively to the second installation inputs of the first and second triggers, the output of the fourth element AND is connected to the second input of the fifth element OR NOT and to the third input of the second element OR NOT. T a b l i and a 1 Note. X - the value of the signal does not matter. Table 2 Editor S. Lisin Compiled by M.Silin Tehred M.Hodanich Fig.z Proofreader M.Sharoshi