SU1183976A1 - Interface for linking computer with indicator and group of peripheral units - Google Patents

Description

The invention relates to computing, and in particular to devices for interfacing computers with external devices measuring equipment and display. five

The aim of the invention is to expand the scope due to the ability to refer to a group of external devices and connect the standard indicator data type, IMG-1-03.

FIG. 1 is a block diagram of the device; in fig. 2 - node address modification option.

The proposed device contains 15 registers of the address of page 1, signs 2, indicator 3, register 4 of data, registers 5 of address and address of sensor 6, triggers 7 of readiness for reception, indicators of readiness 8, readiness 20 for issue 9 and blocking 10, And 11- elements 15, elements AND-NOT 16 and 17, element OR 18, delay elements 19 and 20, comparison node 21, one-shot 22-24, address 25 modification node 25, information switches 26, sensor addresses 27, output readiness signal 28, addresses page 29, ready to receive 30, first switch 31, second switch 32, third switch 33.

Node.25 modification of the address contains (Fig. 2) elements And 34 and 35.

The device works as follows. 25

The structure of this device allows the exchange of information between the computer "Electronics-60", alphanumeric indicators IMG-1-03 and a group of external devices, the output of which is presented in the form of a parallel code and is accompanied by a ready signal.

The initial setup of the device triggers is done by signal 45

"Reset", which comes from the computer or from the switch 33. In this case, the signal "Reset" from the output of the element OR 18 enters the output of the device reset and can be used to set ₅₀ to the initial state of the triggers of external devices. The reset signal comes from the output of the element OR 18 to the input of the installation in "1" of the trigger 7, 8, 10 and sets the data of the trigger to "1". The trigger 9 signal-ν scrap "Reset" is set to "0". The signal from the output of the trigger 8 coming?

on the second information, the input of the switch 30, the first input of which receives a signal from the output of trigger 7, which is set to "1".

Thus, regardless of the signal at the control input of the switch 30, the signal "Reset" results in the appearance of a logical "1" at the readiness output to receive the device. This signal is the flag of the device readiness to receive information from the computer.

Consider the operation of the device when displaying information on the indicator IMG-1-03. This device allows you to record the displayed information in the indicator memory block. Having received the device readiness signal to receive information, the computer issues to the register 2 signs of an address sign and a sign of an IMG, the values of the logical "1" respectively mean that the information received on the register 3 of the indicator is the address to which the character code will be written and that the exchange is carried out with the indicator. This information is recorded in the register of 2 signs by the "Output" signal from the computer. The "Output" signal is received through the delay element 19 to the second input of the And 13 element, at the first input of which there is a logical "1" from the output of the sign of the IMG characteristic register. In the case when there is no blocking of the output, a logical "1" is set at the third input of the And 13 element and the Output signal goes to the output of the And 13 element. The signal from the output of the And 13 element records the memory page address in the address register register 1, writing the address to the register 3 of the device resets the trigger 8 to "0" and goes to the second inputs of the AND-NOT elements 16 and 17. The logical input "1" is output to the first input of the IS-NOT 16 element from the output of the register 2 address sign. signs. As a result, at the output of the element AND-NOT 16, a signal of the address of the character appears (active level - logical "O"), arriving at the output of the device. The response readiness signal of the indicator, indicating that the byte is received, arrives at the trigger input 8 of the trigger 8 and sets the trigger to the unit, the switch 30 in accordance 1183976 4

with the value of the control bridge, the control of these devices,

entry, skips ready-to-exit. It is assumed that information from

These devices receive a signal from the output of the trigger 8 to receive information. In the next output cycle, the code of the output symbol is input to the input of register 5.

The inputs of the signs of the address and the sign of the IMG are served logical "O" and logical "G, respectively. This means that the exchange takes place with the IMG, 1 ° and the input of the register 3 is not the address, but the character code. Writing information to the registers is carried out by the same signals as in the address output cycle. 15

The first (inverse) input of the element AND-NOT 17 receives a logical "O" from the output of the register 2 address sign, allowing the signal from the output of the AND 13 element to pass through the 20 AND-NOT element 17 to the device information recording output and through the delay element 20 one-shot input 23. Signals from the output of the NAND 17 element and from the inverse output of the one-shot 25 23 respectively record the information on the current address and the subsequent increase in the current address by 1. On the indicator readiness signal, the ready-to-receive signal is set. and Information on the output of the device.Further, you can display another address (with the indication of the address) 'or continue to display information in auto-increment mode - using the automatic increment of the address in the indicator by one.

The address of the memory page of the indicator ι is automatically displayed in every ¹ before the address output cycle. If it is necessary to study the information displayed on a memory page, it is possible to feed the address of the desired page using the multi-channel switch 31 via the switch 29. The selection of the switch input is controlled by the output blocking signal received from switch 32. This signal passes the logic zero value the output of the switch 29 signals from the output of the switches 31 and blocks the display of information on the indicator. 55

Consider the operation of the device in the mode of receiving information from a group of external devices and, if necessary, a specific external device is accompanied by the address of this device. In this mode, in the register of 2 signs, the values of the sign of the address and the sign of an IMG equal to a logical zero should be written. These characteristic values ensure the correct functioning of the device in the 'specified mode. Signs are recorded in the register of 2 signs by the "Output" signal coming from the EVM. At a zero value of the IMG attribute, information from trigger 7 is sent to switch 30 output. In this case, the device’s readiness to receive one of the external device's address is determined by trigger state 7. Signal " Reset "trigger 7 is set to" 1. " Having received the device readiness signal to receive information, the computer outputs on the register of 2 signs zero values of the signs and on register 5 of the address — the address of one of the external devices. Signal "Output" signs are recorded in register 2, the same signal is fed to the first input of the element 12, the second (inverse) input of which is logical "0" from the output of the sign IMG register '2 signs, and passes to the output of the element 12. Signal from the output of the element, And 12 writes the address to the register 5 of the address, resets the trigger 7 to "0" and passes to the device start output. The address from the output of register 5 through the node 25 of the address goes to the control inputs of the switches 26-28 and causes the information coming from the given information input to be switched to the switch output. The signal "Start" can be started preparing information. The readiness of information for issuing to a computer is accompanied by a readiness signal of an external device. The readiness signal of the external device through the switch 28 is fed to the input of the one-shot 24, the pulse from the output of which sets the trigger 9 to readiness for output to "1", and through the element C 15, opened by a single value of the trigger 10, passes to the recording inputs of registers 4 and 6 and writes to the register 6 information about the address of the external device arriving at the register from the output of the switch 27, and to the register $

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information from the output of the switch 26. Information from the output of the register 6 is fed to one input of the comparison node 21, to the other input of which information comes from the output of the register 5. In the case of coincidence of both addresses at the output of the comparison node 21, a logical "1" appears, which enters to the input of the one-shot 22 and causes the appearance of a pulse, dropping the trigger 10 into "O".

The unit, from the output of the comparison node 21, arrives at the second input of the And 14 element, the first (inverse) input of which is the logical "0" from the output of the sign of the IMG register of 2 signs. Thus, the signal readiness to release information from the output of the trigger 9 through the open element And 14 passes to the output device. The computer receives information and generates an "Input" signal, which through the open element I 11 enters the synchronous inputs of the trigger 7, 9, and 10 and sets the triggers 7 and 10 to "1", and the trigger 9 to "0".

The exchange cycle is over.

If you need to enter information into the computer from another external device, you must output the corresponding address. In this mode, the readiness of the device to receive or transmit information is confirmed by the states of the corresponding triggers, which allows the exchange of external devices at the rate of work and eliminates synchronization errors.

Consider the functions performed by the address mapping node 25.

This node expands the field of application of the device by providing connectivity to one input of switches 26-28 of external devices that have several addresses. For example, the node

> address translation (Fig. 2)

’Provides a connection to the zero input of a four-input device switch with 10 addresses. When issuing to the register 5 address located between 0-8 and 12, the switches 28-28 connect to the output "Zero input". Information about the address of the sensor is recorded in the register 6 by the signal from the output of the element 15. As soon as the address recorded in the register 6 coincides with the required address recorded in the register 5, the comparison node 21 issues a logical signal "1", the trigger 10 is set to "0" ^ and element 15 will be closed, i.e., further recording in registers 6 and 4 will be blocked and a readiness signal for issuance will be generated. After the information is given to the computer, the device is ready to receive a new address.

Thus, the invention allows to significantly expand the scope of the device compared to the known device due to the possibility of accessing instead of 8 to 2 ¹⁶ devices, displaying information on the standard indicator IMG-1-03 and connecting autonomous external devices (not operated by the interface device) . The increase in the number of connected devices is achieved by using another exchange protocol, in which the exchange is carried out with an external device, whose address is output in the address register 5, the width of which

in order to increase speed for *

the output count of the address in one word is limited to the digit capacity of the machine word of the computer "Electronics-60", equal to 16 bits.

In order to increase the reliability of the information entered, the device contains: there is a knot 21 sravneiiya. It is assumed that information from the external device is accompanied by its address, which arrives at the switch 27, or is rigidly set at the corresponding input of the switch 27. Information from the external device will be entered into the computer if the required and real address match. *.

The presence of the comparison node allows the exchange of information with multi-channel devices that conduct a cyclic survey of channels offline (that is, independently of a computer). The required channel of the device is determined automatically by the comparison node.

In addition to entering information, the device allows for the output of information on the alphanumeric indicator IMG-1-03, which in specialized systems can be used instead of alphanumeric displays such as RIN-609 or 15IE-00-013.

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Claims (2)

DEVICE FOR CONNECTING ELECTRON-COMPUTER MACHINE WITH INDICATOR AND GROUP OF EXTERNAL DEVICES, containing information switchboard, data register, feature register, address modification node, and the information information input group of the information switch is connected to the information bus of the external device group, the first and second information inputs of the attribute register are connected with outputs of signs of the address and information of the electronic computer, the output of the data register is connected to the information bus of the electronic computer machine clock terminal attribute register is the first strobe input device, output data switch coupled to the data input of the data register, address modification unit coupled to the control output information switch input, characterized in that, in order to expand the application area by increasing the number of different external devices, a sensor address switch, a ready-to-issue switch, a readiness-to-receive switch, a page-address switch, a readiness trigger, a trigger are entered into it readiness for issuance, indicator readiness trigger, blocking trigger, sensor address register, address register, indicator register, page address register, three single vibrators, comparison node, five elements And, two ele I-NOT, element OR, two delay elements, three switches, the indicator readiness trigger synchronization is connected to the indicator readiness output, the first input of the OR element is connected to the reset output of the electronic computer, the information input of the address register is connected to the address output of the electronic computer, the group of inputs of the switches of the address of the sensor and the signal of readiness for output is connected respectively to the address output of the address and the output of readiness for the issuance of external devices of the group, information in the progress of the register of the address of the page is connected to the output of the address of the page of the electronic computing machine, the information input of the indicator register is connected to information output of the electronic computing machine, the first input of the first element And is the second gate input device, the output 5TS "1183976 1183976 switch ready to receive is connected to the input ready to receive an electronic computer, the output of the OR element is connected to the single inputs of the ready to receive triggers, indicator readiness, interlock, zero output of the ready to issue trigger and is the device reset output, the output of the second And element is connected to the input of readiness for issuing the electronic computer.the machine, the output of the third element I is connected to the synchronous input address register, the zero input of the readiness trigger for receiving and is the output of the device start The output, the output of the first NAND element is connected to the input of the indicator address recording, the output of the second element NAND is connected to the input of the first delay element and connected to the record input of the indicator information, the output of the first one-vibrator is connected by the gate input of the indicator, the output of the page address switch is connected to the address of the address of the indicator page, the output of the register of the indicator is connected to the information input. the indicator house, the first input of the third element I is connected to the input of the second delay element and connected to the first gate input of the device, the outputs of the readiness triggers and the readiness of the indicator are connected to the first and second information inputs of the receive readiness switch, respectively, the control input of which is connected to the second the inputs of the first and third elements And, the first inputs of the second and fourth elements And and the first output of the register of signs, the second output of which is connected to the first inputs of the first о and the second NAND elements, the second inputs of which are connected to the synchronous inputs of the page address register and indicator register, the zero input of the indicator readiness trigger and the output of the fourth element X, the second input of which is connected to the output of the second delay element, the output of the first delay element is connected to the input of the first one-shot, the input of the second one-shot is connected to the output of the switch signal ready to issue, control input which is connected to the control inputs of the information switch and the sensor address switch, the output of the switch of the sensor address switch is connected to the information input of the sensor address register, the output of which is connected to the first input of the comparison node, the second input of which is connected to the input of the address modification node and the output of the address register, output of the comparison node connected to the input of the third one-shot and with the second input of the second element I, the third input of which is connected to the output of the readiness trigger for issuance, the synchrovescent of which is connected to the sync On the trigger readiness input, the output of the first element I and the synchronous input of the blocking trigger, the zero input of which is connected to the output of the third one-oscillator, and the output to the first input of the fifth element I, the second input of which is connected to the output of the second readiness trigger for output, the output of the fifth element And is connected to the synchronous inputs of the register of the sensor address and the data register, the output of the register of the address of the page is connected to the first information input of the page address switch, the second information input Which is connected to the moving contact of the first switch, the third input of the fourth element I is connected to the control input of the page address switch and the moving contact of the second switch, the second input of the OR element is connected to the moving contact of the third switch, the closing and opening contacts of the first, second and third switches are connected to tires of zero and unit potentials of the device, respectively, 3-inputs for ready-to-receive triggers, indicator readiness, blocking and K-input of ready-to-release trigger are connected to the unit potential bus of the device, K-inputs of receive-ready triggers, indicator readiness, blocking and 3-input of ready to issue trigger are connected to bus zero potential of the device. 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