SU890442A1 - Device for testing rapid-access storage units - Google Patents

Description

The invention relates to computing, namely, to memory and devices, and can be used in the manufacture and testing of operational storage units. A device for controlling operative storage blocks is known, which contains an address counter connected to the drive's input inputs, number registers connected to the drive's numerical inputs, logic circuits, delay elements, error fixing circuits, control and control registers and a one-bit counter, the output of the counter address bits through the delay element connected to the input of the control register, the other input of which is connected through the first matching circuit with the output of the drive, and the output of the control register is connected to About the input of the second matching circuit, the other input of which is connected to the output of the low address bit counter, and the output is connected to the input of the number register through the assembly and directly to the input of the high order address counter whose output is connected to the input of a one-bit counter, the outputs of which connected respectively to the input of the first matching circuit and to the register input is controlled. The known device does not provide effective control of the operational storage units throughout the entire set of control tests, and also does not allow It can be used as part of an automated system with a small digital computer. A device for controlling operative storage blocks, which is also known, contains the first counter, a number register and a control unit connected to the output buses of the device, main switches whose outputs are connected to the inputs of the number register, the second counter, the third counter driver, the counting trigger.

a half-adder, additional switches and an element I, the inverse input of which is connected to the output of the imaging unit, the direct input and input of the third counter to the output of the control unit, and the output to one of the output buses of the device and the input of the first counter whose output is connected to the input through the counting trigger the driver, the outputs of the third counter and the counting trigger are connected to the inputs of the half-adder, the output of which is connected to one of the outputs of the main switches, the other inputs of which are connected to the corresponding outputs of the additional The switches, whose information is connected to the outputs of the third counter, and the control inputs to the outputs of the second counter, the input of which is connected to the output of the counting trigger.

A disadvantage of this device is that it does not allow its use as part of an automated control system with a small digital computer and does not provide reliability of control of operational storage units across the entire set of control tests,

The closest in technical terms to the proposed is a software-controlled controlling system containing a multi-program block, an addressing device, a control data generator, a check drive, an output data collector, a comparison block, an address register, a control data register, an output data register, a circuit for blocking rewriting from the addressing device to the address register, from the control data generator to the control data register and from the output data accumulator to the output data register The main disadvantage of this device is the inability to use a small digital computer, which reduces the overall speed of the system and does not ensure the reliability of the control of the operative storage units across the entire set of control tests.

The purpose of the invention is to increase the speed of the device and increase the reliability of monitoring of operational storage units.

The goal is achieved by the fact that the device for controlling operational storage blocks, containing the first information register, whose inputs are connected to the outputs of the first switch, the first output to the first input of the second switch,

and the second output is to the first input of the comparison unit, the second information register, the first input of which is connected to the second input of the second switch, the second output to the first

the input of the third switch, the third output of the second information register is connected to the second input of the comparison unit, the first output of which is connected to the third input of the second comm mutator, the second output of the comparison unit is connected to the first input of the control unit, the register unit, the first output of which is connected to the input of the third switch, and the second output of the block, the registers is connected to the first input, the first switch of the first switch, the second input (of which is connected to the first output

control unit; the address register, the first input of which is connected to the second output of the control unit, and the output to the fourth input of the second switch, the decoder, the first input of which is connected to the second input of the control unit, and the second output to the fifth input of the second switch, synchronization block, the outputs of which are connected to the third inputs of the control unit; the third inputs of the control unit are connected to the second inputs of the third switch; the first drive is additionally added, the first output of which is connected to the input of the register block, and the second output is to the second input of the address register, the address counter, the first input of which is connected to the third output of the decoder, the second inputs to the fourth inputs of the control unit, and the first output to the first input of the first drive and the second output to the sixth input of the second switch, the fourth switch, the inputs of which are connected to the fourth outputs of the decoder, and the outputs to the second inputs of the first storage device, the second storage device, the first input of which is connected to the third output of the address counter, and the outputs to the inputs of the second information register, and the fifth switch, the inputs of which are connected to the fifth outputs of the decoder, and the outputs 5 to the inputs of the second storage device.

FIG. 1 is a block diagram of the device; in fig. 2 is a block diagram of an address counter; in fig. 3 - block diagram of the fourth switch; in FIG., k is a block diagram of the nth switch. The device contains a synchronization unit 1, a control unit 2, an address register 3, a decoder 4, a first switch 5, a first information register .6, a second switch 7, a third switch 8, a register block 9, a comparison block 10, a second information register 11, a counter 12 addresses, the first drive 13, the second drive I, the fourth switch 15 and the fifth switch 16. The address counter 12 contains a counter 17 and three groups of amplifiers l8-l8n; 19-19p; 20-20p (where n is the number of bits of the counter 17). The fourth switch 15 contains a command amplifier 21 and a group of elements 22-22p (where n is the number of bits of the output channels of the digital computer). The switch 16 contains a command amplifier 23 of the commands and groups of elements And (where n is the number of times of the output channels of the digital computer) . The device works as follows. The address codes of calls to the monitored operational storage unit, the instructions for selecting the treatment mode corresponding to the selected supervisory test, and the numerical information corresponding to each address of the supervisory test, from the memory of the digital computer, are sequentially fed to the inputs of the fourth switch 15 and the fifth switch 16. Using commands from the decoder, the interpreter commands from the digital computers, the signals from the outputs of the switches 15 and 16 are sequentially fed to the inputs of the first drive 13, where the addresses and commands are stored, and the second to kofitel 1, where the number of information is stored. The selection of the write address in drives 13 and 1 is produced by signals from the outputs of counter 12, addresses. Setting the address counter 12 to the required state is performed by commands coming from the memory of the digital computer using signals from the decoder 4. After the recording from the memory of the digital computer is completed, the codes of addresses and commands and the numeric information of the address data of the selected supervisory control are placed in identical addresses of the accumulators 13 and I . At the command of the digital computer using the signal from the output of the decoder k, the signals from the output of the synchronization unit 1 through the control unit 2 are fed to the input of the address counter 12. The initial 2 address code signals from the outputs of the 12 address counter simultaneously arrive at the inputs of the first accumulator 13, second accumulator 1. From the outputs of the accumulator 13 block, the signals of the address address code to the monitored real-time storage unit are fed to the input of the address register 3, the signals of the access mode selection command input block S register, the signals from the output of which is fed to the input of the third switch 8 when writing the first switch or when reading. From the output of the second accumulator 1, the numerical information signals corresponding to the selected code of the address of the monitoring test are fed to the input of the second information register 11 and then from its first output to the second input of the third switch 8, from the second output to one of the inputs of the comparison unit 10. The signals from the output of the synchronization unit 1 through the control unit 2 are fed to the inputs of the address register 3, the third switch 8 and the first switch 5. One cycle is made to access the monitored random access memory. In the recording cycle, the signals of numerical information from the output of the first register 11 through the third switch 8 are fed to the input of a controlled operational storage unit. The next signal from the output of the synchronization unit 1 through the control unit 2 controls the state of the address 12 counter by one, selects the next code and command from the accumulator 13, as well as the corresponding numerical information from the accumulator H, and the cycle to access the monitored random access memory unit repeats . In the read cycle, the si | - lines from the output of the controlled random access memory block through the first switch 5, allowed by the signal from the output of block 9 of registers, are fed to the input of the first information register bis of one of its inputs to the first input of block 10 cara-. where they are compared with signals from the output of the second information register 11. When comparing the signal from the output of the synchronization block 1 of the setting of the time diagram through the control block 2, the state of the counter 12 of the address is increased by one, and the operation cycle of the device is repeated.

If the signal from the second output of the comparator unit 10 is not compared, the operation of the control unit 2 is prohibited, and the signal from the second output of the comparator unit 10 through the second switch 7 in the digital computer signals the presence of an illegally controlled random access memory. According to the signals from the decoder, output signals from the output of register 3 of address, register 6 and register 11, corresponding to the address of accessing a controlled operational storage unit, at which control there is an incomparison between the read and reference value of the numerical information, are fed into the memory via the second switch 7 their further processing. The device continues to operate at the next command of the digital computer with a signal from the output of the decoder 4, which is fed to the input of the control unit 2. The cycle of operation of the device is repeated. References are made to the controlled on-line storage unit throughout the controlled test, the codes of addresses and commands of which are entered into the accumulator 13, and the numerical information into the accumulator 1k before the end of the selected control test. Commands of the digital computer using signals from the decoder k of the address address command to the monitored real-time storage unit, the write control command and the numerical information of the next monitoring test. through the fourth switch 15, the fifth switch 16 is brought into the accumulators 13 and 1, respectively. Device operation | is repeated for the next monitoring test. The signals from the output of the counter 12 of the address are fed to the input of the switch 7 and on the command of the digital computer from the decoder k to the memory of the digital computer for software analysis of the state of the counter 12 of the address.

The counter 12 addresses works as follows. Signals from one of the outputs of control unit 2 are sent to the first input of counter 17 in the mode of accessing the controlled random access memory, to the second input are signals Ajjo "from one of the decoder outputs k, in the mode of writing address codes and commands and numeric information from the memory Digital computers into drives 13 and T signals of a parallel address code from the outputs of counter bits 17 through three groups of amplifiers 18-18p; 19-19p; 20–20 pins (where n is the number of bits of the counter 17) are fed to the inputs of the accumulator 13, the accumulator 1A, and the second switch .7, respectively.

The fourth switch 15 operates as follows. The input of the amplifier 21 in the recording mode of test information from the memory of the digital computer to the drive 13 receives the Icom signal from one. from the outputs of the decoder k. The signal from the output of amplifier 21 is supplied in parallel to the control inputs of the groups of elements 22-22p and the second inputs

which Addr, AjjQp are connected to the outputs of the output channel of a digital computer. Signals of the code of the address of the controlling test and the commands Addr, Ajtoj from the outputs of the group of elements 22-22p and from the decoder come to the corresponding inputs of the numerical information of the accumulator 13 and stored at the address selected by the counter 12 of the address. Block 16 schemes And write numbers works as follows. The input of the amplifier 23 in the recording mode of test information — from the memory of the digital computer to the drive H — receives a signal from one of the outputs of the decoder 4. The signal from the output of the amplifier 23 goes to the control inputs of a group of elements 24-2in, the second inputs of which are connected to the outputs of the output channel Digital computers, numeric information signals

the control test A, from the outputs of the group of elements AND 2, by a command from the decoder, arrive at the corresponding inputs of the numerical information of the accumulator H of the operational memory of numbers and are stored at the address selected by the address counter 12 identical to the address selected by the address counter 12 in the accumulator 13 block.

Thus, the introduction of new features and relationships provides an increase in the reliability of the control of operational storage units, the ability to implement any set of control tests without

Q changes in the device circuit, as well as the ability to connect the device with a small digital computer, which allows to automate the control of the operative storage blocks and increase the speed

5 devices, reducing the total time control.

Claims (3)

Invention Formula A device for controlling operational memorized blocks containing 9 first information register, whose inputs are connected to the outputs of the first switch, the first output to the first input of the second switch, and the second output to the first input of the comparison unit, the second information register the first output of which is connected to the second the input of the second switch, the second output to the first input of the third switch, the third output of the second information register is connected to the second input of the unit, the first output of which is connected to to the third input of the second switch the second output of the comparison unit is connected to the first input of the control unit; a register unit, the first output of which is connected to the input of the third switch; and the second output of the register unit is connected to the first input of the first switch, the second input of which is connected to the first output of the control unit 1, register addresses, the first input of which is connected to the second output of the control unit, and the output to the fourth input of the second switchboard, the decoder, the first you of which is connected to the second input of the control unit and the second output is to the fifth input of the second switch, the synchronization unit, the outputs of which are connected to the third inputs of the control unit, the third outputs of the control unit are connected to the second inputs of the third switch, different from the fact that, in order to increase the speed of the device and increase control accuracy, it contains the first drive, the perm output of which is connected to the inputs of the register block, and the second output - to the second input of the address register, the address counter, the first input of which is connected to the third output of the decoded | ", The second inputs are to the fourth outputs of the control unit, the first output goes to the first input of the first drive, and the second output goes to the sixth input of the second switch, the fourth switch, whose inputs are connected to the fourth outputs of the decoder, and the output to the second inputs of the first drive, the second drive, the first input of which is connected to the third output of the account 1-: address, and the outputs to the inputs of the second information register, and the fifth switch, the inputs of which are connected to the fifth outputs of the decoder, and the outputs to the inputs of the second storage device. Sources of information taken into account during the examination 1. USSR author's certificate ff, cl. G 11 C 29/00, 1972. 2. USSR author's certificate fP 5 “7837, cl. G 11 C 29/00, 1977. 3. For the Germany FR2 М2408990, cl. G 11 C 29/00, published. 1976 (prototype). control W / f- 17  fyfff