SU1608673A1 - Device for debugging programs - Google Patents

Abstract

The invention relates to computing and can be used to debug programs and test microprocessor systems. The purpose of the invention is to increase the speed of the debugging process by using syntax information and speeding up debugging procedures. The device contains a setup memory block 1, a return address register 2, an AND block 3, a subtraction block 4, triggers 6 and 7, three AND elements 8-10, an NOT element 11 with corresponding connections that ensure the substitution of debugging procedure commands into given place of the computational process. 2 Il.

Description

The invention relates to computing and can be used for debugging programs and testing microprocessor systems (MPS).

The purpose of the invention is to increase the speed of the debugging process by accelerating the execution of debugging procedures.

Figure 1 shows the functional diagram of the device; figure 2 - timing diagrams.

The device contains a setup memory block 1, a return address register 2, an AND block 3, a subtraction block 4, an address selector 5, the first 6 and second 7 triggers, the first 8, the second 9 and the third 10 And elements, the HE element 11, input address bus 12, data input and output bus 13, control input bus 14, device startup input 15, main memory access enable output 16, command feature input 17, sync pulse input 18, input 19 acknowledgment: read, input

20 block sample 1 input

21 registry entries 2.

Through tires 12-14, the device is connected to the corresponding tires of the MPS being debugged,

Setup memory 1 contains codes for commands and data for the debugging procedure. In the channel of the debugged MPS, the memory unit 1 is connected only for the duration of the debugging procedure by a signal at the input 20.

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Register 2 of the return address is designed to memorize the address from the channel of the IPU according to the signal at input 21.

Block 4 subtraction serves to convert the current addresses Aj in the channel IPM to the address A V of the setup memory block 1, calculated relative to

but addresses A. return on the formula of

A; - A.

The device works in one of

two modes: standby and debug.

In standby mode, the triggers 6 and 7 are cleared (the initial installation circuit is not shown), the first element And 8 is locked with a zero signal level at the input 15.

Each sync pulse at the input 18 of the address cycle of the IPU, pass through; the element is NOT 11 and the third element is AND 10,. its frontline captures those

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five

The address of the IPU in the register 2 return address. Both inputs of subtraction unit 4 are supplied with the same address code, therefore, from its output, the address input of setup memory 1 in each machine cycle receives an address code equal to 0, however, the sample of this block in standby mode is prohibited by zero signal level on the direct output 20 of the first trigger 6.

To switch to debug mode, a enable signal is applied to the device start input 15. Another sign at the input 17 of the command received by the first discharge of the control bus from the MPS is the first trigger 6. The signal from the direct output 20 of this trigger allows sampling of the setup memory block 1, and the signal from the inverse output 16 prohibits sampling of the main memory MPS. The next address formed by the MPS processor on the bus 12 is converted to a zero physical address at the address input of the memory setup unit 1.

On the leading edge of the clock at the input 18 of the address cycle (the second bit of the control bus 14), the second trigger 7 is set,. the signal from the inverse output of which locks the third element AND 10, as a result of which, the change in j of the address received in register 2 is blocked. This return address A is stored in register 2 all the time while the device is in debug mode. .

Since the sampling of the setup block, 1 of the memory is allowed, the contents of its zero cell are inserted into the bus 13 of the MPS data and are perceived by the processor as the code of the next instruction. From this point on, the control of the MMS is carried out by the program stored in the setup memory block, which organizes the execution of debugging procedures. At the same time, in the MPS processor, the natural time remains until the i change of the command counter, i.e. addressing, since the conversion of current addresses on bus 12 to addresses of setup memory 1 is performed automatically by subtraction unit 4.

Consequently, the transition to a debugging program does not require a special command to transfer control. Any restrictions on the commands used by debugging dp, including,;

on the type of the first team, while not shuffling.

The exit from the debugging mode is carried out as a result of the execution of the transfer control command at the address in which the reprogramming program must end. The source of the return address in this command is the address of the register 2, which passed to the latter in the address space of the IPM. When the MPS processor addresses this address, the selector 5 is triggered, its output signal triggers the passage of a signal — a sign at the input 19 of the reading (3rd bit of the control) 14 of the control) through the second element IT 9 to the input of the block 3 elements AND

Block 3 is opened, the contents of register 2 (return address code) is sent to the data bus 13 and is read by the processor IPU.

The falling edge of the signal from the output of the first element And 9 is reset by the first trigger 6, turning off the memory 1 and turning on the main memory of the MMS.

The processor addresses the return address of the command, continuing the execution of the program being debugged.

Frzmula from-bren

A device for debugging programs containing a setup memory block, a return address register, a block of MeiTOB AND, the first and second triggers, the first and second elements of AND, and the output of the block of AND elements via the bus. connected to the input-output of the memory setup block and to the input-you device, the start and input inputs of the device command are connected respectively to the first and second inputs of the first element I, the output of which is connected to the unit

five

0

five

0

five

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the first input, the information input of the first trigger is connected to the zero potential of the device, the direct output of the first trigger is connected to the sample enable input of the setup memory block, to the first input of the second element I, and the information output of the second register is connected to the information input of the block of elements And, the input of the sign of reading the device is connected to the second input of the second element And, the output of which is connected to the control input of the block of elements And and to the clock input of the first trigger, the inverse output of which is the output of the sampling resolution of the main memory of the device, characterized in that, in order to improve speed, a subtraction unit, a third AND element, an NOT element and an address selector are inserted into the device, and the device clock input is connected to the clock selector input addresses and through the NOT element - with the clock input of the second trigger and with the first input of the third element, And, the output of which is connected to the input of the register of the return address, the output of which is connected to the input of the subtracted block The device address input is connected to the input of the decremented subtraction unit, the output of which is connected to the address input of the memory setup unit, the device record sign input is connected to the recording input of the setup memory block, the device address input is connected to the information input of the address selector, the output of which is connected to the third input of the second element, And, the inverse output of the second trigger co; united with the second input of the third element I.

Claims (1)

E rm u l e rs e n g A device for debugging programs that holds a setup block of memory, a return address wizard, an AND block, the first and second triggers, the first and second AND elements, and with If the output of the block of elements AND is connected through the data bus to the input-output of the adjustment memory block and to the input-output of the first inputs of the first element AND whose course is connected to the unit device, the trigger inputs of the device command flag are connected respectively to the first and second outputs first trigger, information input of the first trigger with connected to the zero potential bus of the device, the direct output of the first trigger is connected to the sampling enable input of the adjustment memory block, to the first input of the second element And and to the information input of the second trigger, the information output of the address register is connected to the information input of the element block And, the input of the reading indicator of the device is connected with the second input of the second element And, the output of which is connected to the control input of the block of elements And and with the clock input of the first trigger, the inverse output of which is the resolution output selection of the main memory of the device, characterized in that, in order to improve performance, a subtraction unit, a third AND element, an NOT element and an address selector are introduced into the device, the synchronization input of the device being connected to the clock input of the address selector and through the NOT element to the clock input of the second trigger and with the first input of the third element And, the output of which is connected to the record entry of the return address register, the output of which is connected to the input of the subtracted subtraction block, the address input of the device is connected to the input of the unit to be reduced subtraction, the output of which is connected to the address input of the adjusting memory block, the input of the recording attribute of the device is connected to the record input of the adjustment memory block, the address input of the device is connected to the information input of the address selector, the output of which is connected to the third input of the second element And, the inverse output of the second trigger with -; one with the second input of the third element I.