SU1509905A1 - Device for diagnosis and simulation of faults - Google Patents

Abstract

The invention relates to computing and can be used to synthesize tests, diagnose and simulate faults in various components of computer systems in an experimental study of reliability. The aim of the invention is to expand the functionality of the device by synchronizing the moment of introducing a fault with the internal states of the test object. To this end, a comparison circuit and a second multiplexer are introduced into the device containing the system register, diagnostic register and the first multiplexer. 4 il.

Description

The invention relates to computing; It can be used to synthesize tests, diagnose and simulate faults in various components of computer systems in an experimental study of reliability.

The aim of the invention is to extend the functionality of specifying the type of device malfunction by synchronizing the moment of introducing the malfunction with the internal states of the test object.

Fig. 1 shows a functional diagram of a device comprising a control device based on a microprogramming control device I (MSD) with feedback; figure 2 - examples of the implementation of the first and second

multiplexers and comparison circuits; in fig. 3 shows an example of the implementation of a diagnostic register in fig. 4 - time diagram of the device.

The device 1 for diagnosing and simulating faults (Fig. 1) is connected to the device 2 of the firmware control of the DPR and contains the first multiplexer 3 (MS), system register 4, (CP4). diagnostic register 5 (RD5), which is conventionally divided into three parts 5 (1) -5 (3), the second multiplexer 6 and the comparison circuit 7 .-.

The information read from device 2 is fed to the first information inputs of blocks 3, 6 and 7. Three signals control the operation mode of multiplexer 3: M - Information loading control in diagnostic register register

;about

QD recounted

 Inversi transmitted and without distortion.

3,150

ki; HB - Fault enter; PC - Comparison result (output of comparison circuit 7).

Depending on the state of the control signals, register 4 records from information from the output of device 2, multiplexer 6, or the first part of register 5.

In register 5, consisting of three parts, the following information is recorded:

in RD 5 (1) - code. dp entries in regist 4 (through the third input of the multiplexer 3); in RD 5 (2), the code for adjusting the Comparison 7 scheme to extract certain signals and set the level of these signals (coming from the output of device 2);

in RD 5 (3) - the code for specifying the type of distortion for each of the device bits 2 - Constant O, Constant 1 bit

Fig. 2 shows one of the possible implementation options for blocks 7, 6 and 3 for one information bit from the output of device 2. Comparison circuit 7 is used to set information about the number of analyzed signals (which correspond to 1 in RD5 (2) and their Level x (О or 1 - is also specified in РД 5 (2)). Comparison circuit 7 (Fig. 2) includes the element AND 8 on and inputs (where n is the information output of the SHZU 2), n elements Equality (adder module 2) 9.1-9. П and п elements 2И-НЕ 10.1-10оП. The first inputs of the elements 9.1-9. П are connected to the outputs of the device 2 , the second input of elements 9.1-9.P and 10.1-10.p are connected to the outputs of RD 5 (2).

With the help of elements 10.1-10. P a set of signals is set, with which synchronization is carried out with the help of elements 9.1-9. P is the level (O or 1 signal with which synchronization is performed.

Multiplexer 6 is designed to specify the type of fault for each of the 2 signals transmitted by the device. Fault Type Constant

O, Constant 1, Inversi or; without distortion, is encoded with two bits in RD 5 (3) for each of bits of device 2.

The table specifies a funck F, depending on the input information (MSPU 2) and the type of distortion (R1, R2 with RD 5 (3)). .

.

The reduced ejection for F is: F R1 SHZU + MPZU. R2.

The information width and communication structure of the system register 4 with the input of the register 5, the address input of the device 2 (A,) and the output (Output) of the object is shown in FIG. 1. The output of device 2 includes n bits, which are fed to the inputs of multiplexer 3 and blocks 6 and 7. From the output of multiplexer 3, bits come to the input of register 4, from the output of which all n bits are connected to the input of register 5., m bits - to the address input SHZU2 and. to n-m bits - on output: object.

Register 5 has a bit, and 2.P bits are connected to the input of block 6 and the type of distortion is encoded, 2 n bits are connected to the input of block 7; And the synchronization conditions are coded (two bits are set and information on whether it is highlighted or not). The register bit 5.2 can only set the signal level, so the output of register 5.2 is one. From output 5.1, bits are connected to the input of multiplexer 3.

The time diagram of the various modes of operation of the device (Fig. 4) includes four periods of time - in which RD 5 is recorded through the serial code DB 1. The start of the recording mode is the presence of a signal. With the arrival, the RD is shifted by 5 by 1 bit. Dp records of the entire register 5 require 5 steps. In parallel with this pres, the system register 4 is entered at 15

DU is recorded information from the output of the SHZU 2, since,, RS (). Information from the output of register 4 arrives at A ,. The change of information on L is also made on the leading edge T, after which the data on the outputs of the device 2 and block 6 change.

Simultaneous translation of the M, HB, DV1 signals into 1 means the end of the recording mode of the RD 5 and the beginning of the modes of storing information in it, selecting by block 7 the moment of the occurrence of a certain code at the output of the MFD 2 (synchronization)

The appearance of signals PC 1 means that the given code from the output of device 2 is highlighted and leads to writing to register 4 distorted in block 6 (distorted information - AI) code from the output of device 2. Thus, a fault can be entered (simulated) synchronously with the appearance of a specific code at the output of the device 2.

The moment of introducing a malfunction can be known in advance (if the sequence of code changes at the output of device 2 is known) or the PC code can be output to the external connector (contact) of the IC (module, TEC).

The signal transfer DVGv O (when) leads to the writing in RD 5 of the code from the register register 4, followed by the reading mode of RD 5 - shifting (at) by 1 bit with each clock signal T.

The operation of the device in the diagnostic mode is completely similar to the operation of the known device. In this mode, in RD 5 (1) in accordance with the fourth mode, information can be recorded via the serial input DV 1, which is then loaded into register 4. Information from register 4 can be recorded in RD 5 (1) and then read from him through the serial output DV 2.

In the fault simulation mode, the RD 5 (2) and RD 5 (3) are recorded, which set up blocks 6 and 7 for the introduction of certain faults4 (15

When certain conditions are highlighted, the time instant at which the fault simulation mode begins is set by the control signal. Fault enter (HB), which can be triggered from an external (with respect to this component) synchronization circuit. The device allows

0 modular capacity. The output DV 2 of one device can be connected to the input DV1 of the next device, etc.

5 claims

A device for diagnosing and simulating faults, containing a system register, a diagnostics register and the first multiplexer, the output of which is connected to the information system register, the output of which is connected to the first information input of the diagnostic register,

5 whose first output is connected to the first information input of the first multiplexer, characterized in that, in order to extend the functionality by

0 assignment of the type of failure and synchronization of the moment of its introduction with the internal states of the control object, a comparison circuit and a second multiplexer are entered into it, the output of the second multiplexer is connected to the second information input of the first multiplexer, the control input of which is connected to the output of the comparison circuit, the first input which is connected

l to the second output of the diagnostic register, the third output of which is connected to the control input of the second multiplexer, whose information input and the second input of the comparison circuit

c are connected to the third information input of the first multiplexer and together they form the input of the device for connection to the output of the control object, and the information output of the system register is the output of the device for connection to the input of the control object.

Out

, From tzugM i From mpzugi-l)

Fi.Z

- ° -11 ё i

 n

X x x x 4

U

with

h

ki x 5 -

Claims (1)

Claim A device for the diagnosis and simulation of faults, comprising a system register, the register diagnosis and a first multiplexer, the output of which is connected to the information WMOs _m from system register, whose output is connected to a first data input of the diagnostic register whose first output is connected to the first data input of the first multiplexer, wherein In order to expand the functionality by setting the type of malfunction and synchronizing the moment of its introduction with the internal states of the object, control circuit, a comparison circuit and a second multiplexer are introduced into it, and the output of the second multiplexer is connected to the second information input of the first multiplexer, the control input of which is connected to the output of the comparison circuit, the first input of which is connected to the second output of the diagnostic register, the third output of which is connected to the control input the second multiplexer, the information input of which and the second input of the comparison circuit are connected to the third information input of the first multiplexer and together they form the input of the device CTBA for connection to the output of the control object, and information output system register is the output device for connection to the input of a control object. Fig.Z FIG. 2 Fig.Z