SU1432528A2 - Apparatus for monitoring the functioning of logical modules - Google Patents

Abstract

The invention relates to digital computing and can be used to control the operation of logic blocks containing LSI RAM (memory), under production conditions and in the maintenance of computer equipment and automation. The aim of the invention is to expand the functionality of the device, in order to monitor and diagnose sequential blocks. For this purpose, a device containing an address counter, a memory unit, a command decoder, a programmable pulse train driver, a control unit, a test set counter, a pulse generator, a synchronization unit, a display unit, an addition element modulo two, a switch, a contact decoder, N programmable matching nodes and two AND elements; a signature analyzer, test generator, switch and comparison unit are introduced. 9 il. 1 tab. with S (L

Description

N)

The invention relates to digital computing, which can be used to control the operation of logic blocks containing LSI RAM (memory), under production conditions and during maintenance of computer equipment and automation, and is an improvement of the device according to the main auth. No. 1327107.

The purpose of the invention is to expand the functionality by providing monitoring and diagnostics of sequential blocks.

FIG. Figure 1 shows a block diagram of a device for controlling the operation of logical blocks containing LSI memory; in fig. 2 shows an example of execution of the control unit; in fig. 3 shows an example of performing a decryption- (Command gate; Fig. 4 shows an example of a switch; Fig. 5 shows an example of a display unit; Fig. 6 shows an example of a signal analyzer; Fig. 7 shows an example of a comparison block ; Fig. 8 is an example of the execution of a programmable matching node; and Fig. 9 is an example of the execution of a test generator.

A device for testing diagnostics of logic blocks containing an LSI memory (FIG. 1) contains a counter 1 address, a block 2 of memory, a decoder of 3 commands, a programmable driver of 4 series of pulses, a block 5 of control, a counter of 6 test sets, a generator of 7 pulses, synchronization unit 8, display unit .9, modulo two element 10, switch 1 1, decoder 12 contacts, programmable nodes 13 ,, ..., 13 (ij matching by the number of contacts of the control object, control object 14, signature analyzer 15, 16 test generator, switch 17, bl approx. 18 comparisons, elements AND 19 and 20.

The device has an output bus 21 of the memory block 2, the third 22, the second 23 and the fourth 24 outputs of the decoder 3 commands, the fifth output 25 of the command decoder, the first output 26 of the command decoder, the first and second outputs 27 and 28 of the programmable driver 4 pulse series, the first 29, the second 30 and the third 31 outputs of the control unit 5, the output 32 of the counter 6 test sets, the output 33 of the generator 7 to them

- Yu

five

. 0 5 0

. „

five

pulses, the first 34, the second 35, the third 36 and the fourth 37 outputs of the synchronization unit 8, the output 38 of the addition element 10 modulo two, the output 39 of the switch 11, the outputs 40 ,, ..., 40 decoder 12 contacts (by the number of contacts of the control object ), the second outputs 41 (, -..., 41c programmable nodes 12 matching, the third outputs 42, ..., 42 ||, programmable nodes 13 matching, the first outputs 43 ,, ..., 431 (programmable nodes 13 matching , one of the output contacts 44 of the object 14 control, a group of outgoing contacts 45 of the object 14 control, output 46 of the signature analyzer 15, the first Output 47, ..., 47y (address output) of the generator 16, second output 48 ,, ..., 48-g (record output) of the generator 16, third output 49 (data output) of the generator 16, quarter and fifth outputs 50 and 51 (outputs of the sign of the test and the indication of resolution) of the generator 16, outputs 52 ,, ..., 52ts of the switch 17, output 53 of the comparison unit 18, output 54 of the first element AND 19, output 55 of the second element And -20.

The control unit 5 of FIG. 2) contains (element NOT 56, button 57, B-trigge 58, display element 59, element NOT 60, element 2I-NOT 61, element I 62, switches 63 and 64, element 2I-NOT 65, element NO 66, elements 2I-NOT 67 and 68, element 2I 69, switch 70, element NO 71, button 72.

The decoder 3 (fig.Z) contains the element 2I-NOT 73, vir binary code decoder 74.

The switch 17 (FIG. 4) contains a connector with pins 47, -47y, 48, -48-j., 49 and a connector with pins 52 ,.

The display unit 9 (phage 5) contains display elements 75, 764, ..., 76ts, indicators 77 and 78 digital, D-trigger 79, display element 80, RS-trigger 81, display element 82, element ZI 83 , RS flip-flop 84, display element 85, RS flip-flop 86, display element 87.

The signature analyzer 15 (Fig. 6) contains an element 88 modulo two, an element 2I-2I-OR 89, a shift register 90-93.

Comparison unit 18 (Fig. 7) contains elements 94 ,, .. ,, 94 c of modulo two addition, elements 2И 95 -95 | g D-flip-flops 96, ..., 96 (c.

Matching node 13 (FIG. 8) contains a four-frequency trigger register 97 with a common synchronization input, a two-bit trigger register 98, a first register 99, a HE element 100, a diode 101, a relay 102, elements 2I – HE 103, and 104 a TTL level driver 105 with three output states, the second resistor 106, the transducer 107 of the TTL levels - ECL, the transducer of 108 levels. OESL-TTL, the addition element 109 modulo two, the element 2I 110 ,. D-trigger 111, the element 112 display.

The test generator 16 (FIG. 9) contains a Y-bit trigger register.

113, Y-bit binary counter

114, Y-bit trigger register

115, element 2И 116 D-trigger 117, frequency divider 118, multiplexer

119, P-bit binary counter

120, a decoder 121.

The test generator 16 is designed to form an algorithmic test for checking the operation of the LSI memory embedded in the logic blocks, has the first information input directly connected to the memory block bus. This input to the generator 16 receives information in binary codes about the amount of the generated RAM (memory) and the frequency of checking. The generator 16 has a setup input connected to the output 30 of the control unit 5, a receiving input of pulse signals connected directly to the output 33 of the generator name, pulses, a start input connected to the output 24 of the command decoder} information recording inputs, connected to the output group 25 decoder 3 teams. The generator 16 has outputs for generating signals Address Record 48, -48t, Data 49, connected to the inputs of the switch. At the output 50 of the generator 16, a signal is generated - Vkp.alg.test (the inclusion of an algorithmic test), inputs to the inputs of the control unit 5 and the display unit 9.

The output 51 of the generator 16 is designed to supply a strobe signal to the comparator unit 18 and a signature analyzer 15 (Strobe signal).

FIG. 9 shows an example of an implementation of a generator 16 implemented on 531 series microcircuits. The generator forms a test consisting of an alternation

no record of zeros and ones over the entire amount of RAM (memory), i.e. units will be written to all odd addresses,

and for all even-nons,

However, any other algorithmic tests such as running zero, running unit, march, dock, canter, background recording of zeros, background recording of units, etc. can be used in the device for testing diagnostics of logical blocks containing LSI RAM. In each case, the hardware implementation of the generator 16 changes while maintaining the assignment and number of inputs and outputs.

The switch 17 is designed to provide signals from the generator 16 to any of the programmable matching nodes 13. - This is due to the fact that the corresponding address and information inputs and inputs of the LSI RAM entry embedded in the logic unit can be wired to the different contacts of the logic unit. The one shown in FIG. 4 illustrates the implementation of switch 17 in that it consists of two connectors, one of which is supplied with generator 16 (outputs 47, -47, 48, 49), and the contacts of the second connector are directly connected to the eighth inputs of the programmable matching nodes 13.

The signals are switched manually by wire jumpers, or by a device specific for each object, which consists of two connectors with the necessary switching.

Comparison unit 18 is designed to generate the results of testing the operation of the LSI RAM at each step of the algorithmic test. It has a reset input associated with the output 30 of the control unit 5, a signal receiving input from the output 51 of the generator 16 into a group of information inputs, each of which can be connected to any outputs of the control object BIS RAM with each wired jumper. The output of the comparator unit 18 is connected directly to the inputs of the display elements. The reject of the RAM of the display unit 9. Comparison unit 18 may be implemented on elements 531TM2, 531LP5.

Signature analyzer 15 is designed to verify the functioning of both the entire logical block and embedded LSI RAM, as well as to search for defects in logical blocks.

Signature analyzer 15 has an initial setup input connected directly to the output 30 of the control unit 5, a start input connected to the output 31 of the control unit 5, a enable input connected directly to the output 51 of the generator 16, a result recording input connected to the output 37 of the unit 8 synchronization and information input, which is connected to any of the outputs of the control object. The output of the analyzer 15 is connected to the inputs of the Signature of the display unit 9. Signal analyzer can be implemented on a chip series 155 or 531,

The signature analyzer 15 in the device can operate in two modes: the signature generation mode from the BIS RAM output when the algorithmic test is submitted to the control object and the signature generation mode from any contact of the control object when deterministic tests are sent from the memory block of the device.

In the first mode, the synchronization of the signature analyzer 15 is performed by the signal of the generator 16, in the second case by the signal ZP REZ (recording the result) from the output 37 of the synchronization unit 8.

In the second mode of operation of the signature analyzer, a search is performed for the defect in the logic blocks on the deported tests to remove the signatures from their contacts and compare them with the reference signature values for these contacts.

The device works as follows.

In the absence of controlled logical blocks BIS RAM, the device operates similarly to the known device. The control program is encoded in the same way. To ensure control of logical blocks,) Containing BIS RAM, the control program must contain in addition to the six command words of the known device three additional command words listed in the table .. These three command words Alg.test, RAM sampling cycle, RAM capacity provide0

five

0

five

0

five

0

five

0

five

At a certain stage of passing a control pattern, programming generator 16, stopping the reading of the control program from block 2 of the device memory and running the algorithmic test. After the end of the algorithmic test, the corresponding signal from the generator 16 ensures that the control unit 5 of the device is started to further pass the monitoring program.

If the logic block control program includes running an algorithmic test, then at a certain stage of passing it from memory block 2 to the decoder of 3 commands, three command words are received successively. The first of them contains in the address byte the command code of the RAM size, and in the data byte the code of the volume of the BIS RAM being checked.

The content of the data bits of this command word goes directly to the first group of input-generator 16 (Fig. 9). On the sync load signal generated at the output 35 of the synchronization unit 8, a control pulse appears at the corresponding output 25 of the decoder 3 commands; this information is recorded in the register 16 of the generator 16 (FIG. 9).

The second command word coming from memory block 2 contains in the address byte the command code RAM sampling cycle (table), and in the data byte the command code the sampling cycle of the LSI RAM. The contents of the data bits are fed directly to the information input of the generator 16. A clock pulse appears at the corresponding output 252 of the decoder 3 commands, which records information about the sampling cycle of the LSI RAM in the register 115 of the generator 16 (FIG. 9).

The third command word contains in the address byte the command code Alg. Test. A clock signal is loaded at the output 24 of the decoder 3 command and a low-level control pulse appears simultaneously to the fifth input of control unit 5 and the second input of generator 16. When this signal arrives, the trigger 58- (figure 2) is reset to zero state The start signal is removed from output 31, the Start indication is turned off, and in generator 16 trigger 117 is set to one, thereby triggering an algorithmic test. At the same time, on signal 50, an On signal appears, alg. test, ensuring the inclusion of the element 75 of the display Alg. test in display unit 9 (figure 5).

Signal Dismissing The start-up blocks the operation of the synchronization unit 8, while the sync signals on the outputs of AP-37 are not generated (Fig. 1), i.e. work of the counter of 1 address, the decoder of 3 commands, the counter of 6 test sets is blocked. Information and building signals are generated in the generator 16.

After installation and the unit state of the trigger 117 (Fig. 9), the frequency divider 118 is enabled, at the outputs of which the pulse sequences of signals of different follow-up periods appear. The output of the multiplexer 119 is the one of which, the code of which is specified in the Sample Cycle command, is recorded in register 115 and is present at the address inputs of the multiplexer 119. The selected pulse sequence with period T goes to the counting input of the binary counter 120, the information on the installation inputs of which determines the conversion factor of the counter, and hence the period for changing the address on the address outputs of the generator 16. The address change clock signal is generated at the transfer output of the counter 120 and fed to the count input of the binary counter 114. The recalculation coefficient of the counter 114 is determined by the number of addresses of the checked LSI RAM, that is, the information that goes to the installed inputs Hell, ..., Ay from the outputs of the register 113. At the address outputs 47, ..., 47y of the counter 114 are formed signals Address of inputs A,

Oh, Ay. Junior Counter Size

114 at the same time is for the illustrated example of the generator 16 output Data 49.

The signals from the outputs of counter 120 arrive at the address inputs of the decoder 121. The outputs of the decoder 121 appear at different times with discreteness T signals Recording and the Strobe signal 51, which is removed in this example,

five

0

five

0

five

0

five

0

five

generator 16 from the last but one output of the decoder 121.

The use of a decoder 121 allows a signal to be written to the tested LIS RAM at any time with a resolution of T within the period of the address change at the inputs of the LSI RAM. The minimum interval between the end of the {Signal Signal and the Strobe signal is T.

The switch 17 provides the signals Address, Data, Record to the eighth inputs of those programmable nodes-13 matching, which are connected to the inputs of the tested LSI RAM (figure 1).

The matching unit 13 provides the passage of a signal from the input 52 (Fig. 8) through the shaper 105 to the output 43, which is connected to the contacts of the logical block being checked.

In accordance with the selected control mode, information from the outputs of the tested LSI RAM can be applied either to the signature analyzer block or to the comparison block.

Let compare mode with reference data be selected. In this case, the output of the tested LSI RAM, i.e. the corresponding contact of the checked logical block is switched by a jumper to the second input of any of the elements, the comparison block 18 (Fig. 7). 1a, the first input of this element receives the reference signal of the generated data from the corresponding output of the switch 17. In each clock cycle of the algorithmic test, the reference information is compared. Data and information recorded and read in this clock at the corresponding address in the BIS RAM. Strobe signal appears after the end of the Record signal, when information has already been recorded in the LSI RAM. By the time the Strobe signal arrives, the output of element 94 will establish the result of the comparison of the reference information read from the LSI, which will be written into the trigger 96j and the logical level of the signal will be set at the corresponding output 53 in accordance with the comparison result.

If there is a discrepancy between the read out of the LSI RAM and the reference information, the output 53 will be low; the corresponding element 76 of the Marriage RAM indication is turned on. Indication Marriage

The RAM is already present until the end of the algorithmic test run and it can only be turned off by the Reset button.

Comparison unit 18 and display unit 9 contain not one, but N elements of comparison and indication to provide control in the compare mode of the LSI RAM,

When a defect is detected by a verifiable logical block and the need to search for a defect in it, the signature locator is used to obtain the control point signatures of the logical block, which the operator compares with the reference signatures for these block points specified in those

; having multiple data outputs (on the th-th logical documentation

When a defective logical block is detected and a defect is found in it, the signature analyzer is used to obtain the control point signatures of the logical block, which the operator compares with the reference signatures for these block points specified in the technical documentation for logic

I example when organizing a 1Kx4 memory, as well as to provide control of several single-bit BIS RAM with parallel-connected address I inputs).

In the mode of comparing signatures before: running an algorithmic test information; | Macyon input of signature analysis; Com. 15 is connected to the required contact of control object 14 (Fig. 1).

After running an algorithmic test, at each step of checking information from the checked contact of the logical unit, at output 44, I goes to the fifth input of the element 88 (Fig. 6) and, accordingly, at each step, the test at the output of the element 88 will be; new information coming in: 16-bit sequential register: built on shift registers 90-93, register gating in mode 1, algorithmic test carried out-. with a strobe signal passing through i) e3 element 2I-OR 89,

The group of outputs 45 is directly connected to the inputs of the digital indicator Signature 77 (FIG. 5), which indicates on each check cycle the status of the signature register ana-; lysator. The total signature from the given output of the control object is displayed after a complete pass of the algorithmic test. .

After completing the algorithmic test at the output of the counter. 114 (FIG. 9) a transfer signal appears, which, through element 116, enters the reset input of trigger 117 and ensures that the generator 16 stops, i.e. the counter 114 and the frequency divider 118 are blocked, simultaneously with the output 50 the signal is turned off and the indication element Alg is turned off accordingly. test 75 (FIG. 5, 5), and start trigger 58 (FIG. 2) is set to one again, allowing further operation of the entire device.

block.

The signature of the controlled points of the logical block is obtained each time after a single test run,

Commute to the information input of the signature analyzer each time a new point of the logic block is possible. to search for defects in logical blocks.

Claims (1)

Invention Formula A device for controlling the operation of logical blocks according to the author. St. No. 1327107, which differs from the fact that, in order to expand (functional possibilities of bots by providing monitoring and diagnostics sequential blocks, a test generator, a switch, a comparison unit and a signature analyzer are entered, the output of the memory unit is connected to the information input of the test generator, the fourth output of the command decoder is connected to the fifth input of the control unit and the first sync of the test generator, the second syncro - the input of which is connected to the fifth output of the command decoder, the second output of the control unit is connected to the reset input of the test generator and the inputs of the initial installation of the signature analyzer and the comparison unit, The pulse generator is connected to the third synchronous input of the test generator, the output of the address, the write output and the data outputs of which are connected respectively to the first and second control inputs and information inputs of the switch, the output of the test generator test characteristic is connected to the sixth input of the block the control unit and the seventh input of the display unit, and the output of the permission indication of the test generator is connected to the resolution input of the signature analyzer and the control input of the comparison unit, the information input of the signature analyzer is input devices for connecting to the first output of the monitored logic block; the first information input of the comparison unit is the input of the device for connecting the second output of the monitored logic block; End of test Delay SI1 SI2 PPE SI4 Alg. Test RAM capacity Sampling cycle Ram H is a 16-part presentation system. the comparison input and the signature analyzer are connected to the eighth and ninth inputs of the display unit, the fourth output of the synchronization unit is connected to the recording input of the signature analyzer output, the start input of which is connected to the monitor. Delay code Pulse number code Also ti if Do not use the volume code BIS RAM RAM sample cycle code iffiff Q fusifliectna 2i 23 21 35 , 9uz, 5 If PU2. 2 Fy 9uiff ig.7 id csl rr lo "H QO esi : i Bt- About f tSt SO " 7 SO fu2. 9