JPS6074883A - Video recording and reproducing system - Google Patents

Abstract

PURPOSE:To obtain stable still pictures despite the disturbance of H signals by storing not only the picture element information but the corresponding H signal to a memory and obtaining the still picture information from the H signal and the picture element information read out of the memory. CONSTITUTION:A write timing signal WT is delivered from a timing signal generating circuit 13 synchronously with the vertical synchronization of a video signal VID given from an FF16 and from an H-position preceding place within a period H with a prescribed time width. The signal VID undergoes A/D conversion or is written to a memory based on the signal VID according to the signal WT. Thus the video signals including the signal H are recorded to the memory. In a reproduction mode, the data are read out of the memory and undergo D/A conversion. As a result, a reproduced video signal contains the signal H. This signal H is used to a video reproducer. Thus the video reproduction is possible with the same signal H as a video record mode. In this way, the shift among pictures is prevented.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an image processing system in which an m-image signal is converted from analog to digital and stored in a memory, and data read from the memory is converted from digital to analog to reproduce an image signal. Concerning recording and reproducing methods.

[Technical background of the invention and its problems]

In recent years, a method has been widely used in which an image signal (for example, an NTSC signal) is converted from analog to digital and stored in a memory, and data read from the memory is converted from digital to analog to reproduce the image signal. In conventional image recording and reproducing means of this kind, during image recording, every time the image signal to be recorded is horizontally synchronized, the signal of the actual image part (pixel information part) is recorded based on the detection timing of the horizontal synchronization signal. Analog-to-digital conversion and storage in memory.

Furthermore, when reproducing an image, the image data read from the memory is digital-to-analog converted and mixed with an externally generated horizontal synchronizing signal to obtain a reproduced image signal. Generally, real image data according to the number of horizontal synchronizations for one screen is recorded in the memory and reproduced and output as still image information.

Figures 1 (-) to (f) show the signal timing of each part at this time. When storing an image, the video signal (NTSC composite image signal) shown in Figure 1 (a) is converted to the video signal (NTSC composite image signal) shown in Figure 1 (b). The horizontal synchronization signal (No. i (HO)) is extracted as shown in FIG. Extract the actual image signal shown in , that is, the pixel information that actually constitutes the pixel, convert it from analog to digital, and sequentially store it in memory from address O. Also, when playing back and outputting, external Figure 1 (
Create the horizontal synchronization signal (H(E)) f shown in e), read it from the memory above, and mix it with the analog-converted pixel information to create reproduced image (still image) information as shown in (f) of the same figure. I was getting it.

However, such conventional image recording and reproducing means had the following drawbacks.

That is, conventionally, as mentioned above, 16 pixel signals are stored in memory using the horizontal synchronizing signal (H) included in the video signal that is the subject of the stored image, and during playback, the horizontal synchronizing signal (H) that is generated externally is used. a(g)) t Since the configuration is such that the reproduced image (still image) information is obtained by mixing, the horizontal synchronization signal in the video signal that is the target of the stored image may be affected for some reason (for example, switching of the recording/reproducing head of a VTR, vertical If the image is disturbed due to the influence of a synchronizing signal (such as the influence of a synchronizing signal), it cannot be synchronized with a horizontal synchronizing signal (H(E)) generated externally during reproduction, and therefore, when reproduced as a still image, image shift occurs.

[Purpose of the invention]

The present invention was made in view of the above-mentioned circumstances, and it digitally converts pixel information in a video signal and stores it in a memory.
In an image processing device that obtains still image information for one screen from pixel information read from the memory, even if the synchronization of the horizontal synchronization signal in the video signal suddenly becomes disrupted,
It is an object of the present invention to provide an image recording and reproducing method that does not cause image shift in reproduced (still) images according to the information read from the memory.

[Summary of the invention]

The present invention has a timing signal generating means for extracting pixel information for each horizontal scanning period including horizontal synchronization from the video signal in synchronization with a vertical synchronization signal included in the video signal, and When storing image data, not only pixel information but also a corresponding horizontal synchronization signal is stored in the memory according to the timing signal, and still image information is obtained from the horizontal synchronization signal and pixel information read out from the memory. As a result, even if a disturbance occurs in the horizontal synchronization signal in the video signal during memory writing, a stable still image can be obtained without causing any shift in the reproduced (still) image.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is a circuit block diagram showing the circuit configuration of the main part in one embodiment of the present invention, and FIGS. 3(a) to 3(c) are diagrams showing signal timings of the main part in the above embodiment, respectively. In the figure, 11 is the video signal (N
12 is a synchronization separation circuit that outputs vertical and horizontal synchronization signals (V, H)' (i = separate output) from VID (TSC composite image signal), and 12 outputs vertical synchronization signals (
This is a vertical synchronization separation circuit that separates and outputs V). 13 is a vertical synchronization signal (V)K obtained from the vertical synchronization separation circuit 12
Synchronized write timing signal (WT) for each scanning period unit (63.5 μS) as shown in FIG. 3(b)
This is a timing signal generation circuit that generates and outputs J4.
16 to 16 are its constituent elements, 14 is a counter, 15Fi decoder, and 16 is a flip-flop. Among these components, the counter 14 receives the vertical synchronization signal (v) and the counter load signal (v) from the decoder 15.
LD) and the basic clock (CLK), and synchronized with the vertical synchronization signal (V) - horizontal scanning period (63.5μ
The counting operation of am is repeated, and one counting operation period is indicated by T in FIG. Further, upon receiving the count output of the counter 14, the decoder 15 outputs a counter load signal (LD) of low level "0" every time the count of the period (63, 5μ11) shown in FIG. 3 is completed. At the same time, the low-level timing signal (ST) is activated every time the count period shown by t in FIG.
Output. This timing signal (ST) is set to be generated at the end of a count that includes at least the horizontal synchronizing signal (H) and the actual image portion, that is, the pixel information portion, within the -horizontal period. Furthermore, upon receiving the timing signal (ST), basic clock (CLK), and vertical synchronization signal (v) output from the Fritsuno flop J6I'i decoder 15, the write timing signal shown in FIG. 3(b) is generated. (w'r) f: Generate and output.

In addition, FIG. 3(e) shows the video signal VID'i stored in the memory based on the write timing signal (WT) shown in FIG.
is pixel information, which is shown here in a digital-to-analog converted state.

The operation of one embodiment will now be described with reference to FIG. 2 and FIGS. 3(a) to 3(c). When an NTSC composite image signal, that is, a video signal is given to the sync separation circuit 1, and a vertical sync signal (V) is separated and output from the vertical sync separation circuit 12, the counter 14 is initialized by this vertical sync signal (V). At the same time, the flip-flop 16
is reset, and thereafter the counter J4 performs a counting operation according to the basic clock (CLK), and the flip-flop 16 reads the timing signal (ST) output from the decoder J5. At this time, the decoder 15
Until the count value of counter J4 reaches the count value corresponding to time t, the timing signal (S
Therefore, the flip-flop 16 is in a set state. When the counter J4 reaches the count f which corresponds to time t, the timing signal (ST) output from the decoder 15 remains at a low 60'' level from then on until the counter 14 is cleared. The flip-flop f16 enters the reset state in synchronization with the counter 14 for one hour (63,
When the count reaches 1, which corresponds to 5 μS), the decoder 15 outputs a counter low signal (LD
) is output, and as a result, the counter J4 is once cleared and returned to the initial value state, and the timing signal (ST) and counter load signal (LD) output from the decoder 15 both go to the high 11# level state.

Such an operation is repeated, and the flip-flop 1
From 6 onwards, as shown in FIG. 3(b), in synchronization with the vertical synchronization of the video signal, from before the horizontal synchronization signal (H) position within the horizontal period, a high "1" indicating the write permission state is set at time @.
A write timing signal (WT) in a level state is output. Based on this write timing signal (Wr), analog-to-digital conversion of the video signal (VID) and writing to the memory are performed. Therefore, the video signal including the horizontal synchronization signal (I()'t) is recorded in the memory. During playback, the data in the memory is read out and digital-to-analog conversion is performed to generate the played video. The signal includes a horizontal synchronization signal, which is connected to the image reproduction device's water-+Tl-1lk+lk
112 1 1? ) L Iy? h muscle 1112
Image reproduction is performed using the Fm horizontal synchronization signal, eliminating the need for external mixing of the horizontal synchronization signal and suppressing image shift.

〔Effect of the invention〕

As described in detail above, according to the image recording and reproducing method of the present invention, pixel information in a video signal is digitally converted, stored in a memory, and still image information for one screen is generated from the pixel information read from the memory. In the image processing device that obtains the image processing apparatus, even if the synchronization of the horizontal synchronization signal in the video signal suddenly becomes disrupted, stable reproduction without causing image shift of the reproduced (still) image according to the information read from the memory. You can get the image.

[Brief explanation of drawings]

1 (&) to (f) are time charts for explaining conventional image recording and reproducing means, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIG. 3 (-) to (
C) is a time chart for explaining the operation of each of the above embodiments. 1 No... Synchronization separation circuit, J2... Vertical synchronization separation circuit, 13... Timing signal generation circuit, 14... Counter, 15... Decoder, 16... Flip frog O

Claims (1)

[Claims] In a device that performs analog-to-digital conversion on a real image signal for each horizontal period included in the image signal, stores it in a memory, and obtains a reproduced image from read data of the memory, the horizontal period is converted according to vertical synchronization of the image signal. It has a timing signal generation circuit that generates a timing signal for extracting an image signal including a horizontal synchronization signal for each horizontal period, and the timing signal generated by the timing signal generation circuit generates a horizontal synchronization signal and an actual image for each horizontal period. An image recording and reproducing method characterized in that a signal is digitally converted and stored in the memory.