JPH0542196B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an image recording method in which an image signal is converted from analog to digital, stored in a memory, and data read from the memory is converted from digital to analog to reproduce the image signal. Regarding the playback method.

[Technical background of the invention and its problems]

In recent years, a method has been widely used in which an image signal (for example, an NTSC signal) is converted from analog to digital and stored in a memory, and data read from the memory is converted from digital to analog to reproduce the image signal. In conventional image recording and reproducing means of this kind, during image recording, every time the image signal to be recorded is horizontally synchronized, the signal of the actual image part (pixel information part) is recorded based on the detection timing of the horizontal synchronization signal. Analog-to-digital conversion and storage in memory. Also, during image reproduction, the image data read from the memory is converted from digital to analog,
The reproduced image signal was obtained by combining (mixing) with an externally generated horizontal synchronization signal. Generally, real image data according to the number of horizontal synchronizations for one screen is recorded in the memory and reproduced and output as still image information.

Figure 1 a to f show the signal timing of each part at this time. When storing an image, the video signal (NTSC composite image signal) shown in Figure 1 a is started from the video signal shown in Figure 1 b.
The horizontal synchronizing signal H _{(I) is} extracted as shown in FIG. Pixel information constituting a pixel is extracted, analog-digital converted, and sequentially stored in memory starting from address 0. In addition, when outputting a reproduction, a horizontal synchronizing signal H _(E) shown in Figure 1e is generated externally, and this is read out from the memory and mixed with the analog-converted pixel information to produce a reproduced image as shown in Figure 1f. (Still image) I was getting information.

However, such conventional image recording and reproducing means has the following drawbacks. That is, conventionally, as described above, pixel information is stored in memory using the horizontal synchronization signal H _(I) included in the video signal that is the target of the stored image, and during playback, the horizontal synchronization signal H _(I) generated externally is used. ₎ to obtain playback image (still image) information,
If the horizontal synchronization signal in the video signal that is the target of the stored image is disturbed for some reason (for example, switching the recording/playback head of the VTR, the influence of the vertical synchronization signal, etc.), the horizontal synchronization signal H _(E) generated externally during playback may be distorted. There was a drawback that synchronization could not be achieved, and therefore, when reproduced as a still image, image shift occurred.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides an image processing device that digitally converts pixel information in a video signal, stores it in a memory, and obtains still image information for one screen from the pixel information read out from the memory. To provide an image recording and reproducing method that does not cause an image shift of a reproduced (still) image according to information read from the memory even if the synchronization of a horizontal synchronizing signal in the video signal is suddenly disturbed. With the goal.

[Summary of the invention]

The present invention has a timing signal generating means for extracting pixel information for each horizontal scanning period including horizontal synchronization from the video signal in synchronization with a vertical synchronization signal included in the video signal, and When storing image data, not only pixel information but also a corresponding horizontal synchronization signal is stored in the memory according to the timing signal, and still image information is obtained from the horizontal synchronization signal and pixel information read from the memory. As a result, even if a disturbance occurs in the horizontal synchronization signal in the video signal during memory writing, a stable still image can be obtained without causing a shift in the reproduced (still) image.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit block diagram showing the circuit configuration of the main parts in one embodiment of the present invention, and FIGS. 3a to 3c are diagrams showing signal timings of the main parts in the above embodiment, respectively. In the figure, 11 is the video signal (NTSC composite image signal) shown in Figure 3a that is to be converted from analog to digital and written to the memory.
This is a synchronization separation circuit that separates and outputs vertical and horizontal synchronization signals V and H from VID, and 12 is a synchronization separation circuit 1.
This is a vertical synchronization separation circuit that separates and outputs a vertical synchronization signal V from the output of 1. 13 is vertical synchronization separation circuit 1
2, synchronized with the vertical synchronization signal V obtained from
One horizontal scanning period unit (63.5μs) as shown in Figure b
This is a timing signal generation circuit that generates and outputs a write timing signal WT for each write timing signal WT.
14 is a counter, 15 is a decoder, and 16 is a flip-flop. Among these components, the counter 14 is
It receives the vertical synchronizing signal V, the counter load signal LD from the decoder 15, and the basic clock CLK, and repeats the counting operation every horizontal scanning period (63.5 μs) in synchronization with the vertical synchronizing signal V. One count operation period is indicated by T in FIG. Further, upon receiving the count output of the counter 14, the decoder 15 outputs a counter load signal LD of low level "0" every time the count period (63.5 μs) shown in FIG. 3 is completed. Before that, a low-level timing signal ST is output every time the count period shown by t in FIG. 3 ends. This timing signal ST is set to be generated at the end of a count that includes at least the horizontal synchronizing signal H and the actual image portion, that is, the image information portion, within one horizontal period. Further, the flip-flop 16 receives the timing signal ST outputted from the decoder 15, the basic clock CLK, and the vertical synchronization signal V, and generates and outputs the write timing signal WT shown in FIG. 3b.

Incidentally, FIG. 3c shows the video signal VID stored in the memory based on the write timing signal WT shown in FIG. −
Shown after analog conversion.

The operation of one embodiment will now be described with reference to FIG. 2 and FIGS. 3a to 3c. When an NTSC composite image signal, that is, a video signal is given to the synchronization separation circuit 11, and a vertical synchronization signal V is separated and output from the vertical synchronization separation circuit 12, this vertical synchronization signal V causes
The counter 14 is initialized (cleared) and the flip-flop 16 is reset. From then on, the counter 14 performs a counting operation according to the basic clock CLK, and the flip-flop 16 is reset.
6 is the timing signal output from the decoder 15
Load ST. At this time, the decoder 15 receives a timing signal of high "1" level until the count value of the counter 14 reaches a count value corresponding to time t.
ST is output, so flip-flop 1
6 is in the set state. When the counter 14 reaches a count value corresponding to time t, the timing signal ST output from the decoder 15 becomes a low "0" level from then on until the counter 14 is cleared, which causes the flip-flop to be activated in synchronization with the basic clock CLK. 16 is in the reset state. When the counter 14 reaches a count value corresponding to time T (63.5 μs), the decoder 15 outputs a counter load signal LD of low “0” level, thereby once clearing the counter 14 and setting it to the initial value. state and decoder 1
Both the timing signal ST and the counter load signal LD outputted from 5 become high "1" level state. This operation is repeated, and as shown in FIG. 3b, the flip-flop 16 outputs write permission in synchronization with the vertical synchronization of the video signal for a time width of t from before the horizontal synchronization signal H position within the horizontal period. A write timing signal WT having a high "1" level state indicating the state is output. Based on this write timing signal WT, analog-to-digital conversion of the video signal VID and writing to the memory are performed. Therefore, a video signal including the horizontal synchronization signal H is recorded in the memory.
During reproduction, by reading the data from the memory and converting it from digital to analog, the reproduced video signal includes a horizontal synchronizing signal, and by using this as the horizontal synchronizing signal of the image reproducing device, Image reproduction is performed using the same horizontal synchronization signal used for image recording, eliminating the need for external mixing of horizontal synchronization signals and suppressing image shift.

〔Effect of the invention〕

As detailed above, according to the image recording and reproducing method of the present invention, pixel information in a video signal is digitally converted, stored in a memory, and still image information for one screen is generated from the pixel information read from the memory. In the image processing device that obtains the image processing device, even if the synchronization of the horizontal synchronization signal in the video signal suddenly becomes disrupted, stable playback that does not cause image shift of the reproduced (still) image according to the information read from the memory is provided. You can get the image.

[Brief explanation of the drawing]

1A to 1F are time charts for explaining conventional image recording and reproducing means, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIGS. 3A to 3C are respectively diagrams of the above embodiment. This is a time chart to explain the operation. 11... Synchronization separation circuit, 12... Vertical synchronization separation circuit, 13... Timing signal generation circuit, 14...
...Counter, 15...Decoder, 16...Flip-flop.

Claims (1)

[Claims] 1. In a device that converts an actual image signal for each horizontal period included in an image signal into an analog-to-digital value, stores it in a memory, and obtains a reproduced image from data read from the memory, the actual image signal is converted for each horizontal period according to vertical synchronization of the image signal. The timing signal generation circuit generates a timing signal for extracting an image signal including a horizontal synchronization signal, and the horizontal synchronization signal and the actual image signal for each horizontal period are generated by the timing signal generated by the timing signal generation circuit. An image recording and reproducing method characterized in that the image is digitally converted and stored in the memory.